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| author |   drahn <drahn@openbsd.org> | 2009-05-11 12:50:23 +0000 |
|---|---|---|
| committer | drahn <drahn@openbsd.org> | 2009-05-11 12:50:23 +0000 |
| commit | 10c0205c4754e485f7689712dd4c7f7cada1ff4d (patch) | |
| tree | 495857e6b086799670a0355b312b36240bee8491 | |
| parent | driver address fix. (diff) | |
| download | wireguard-openbsd-10c0205c4754e485f7689712dd4c7f7cada1ff4d.tar.xz wireguard-openbsd-10c0205c4754e485f7689712dd4c7f7cada1ff4d.zip | |
Add some (not used yet) control regiser bit definitions.
| -rw-r--r-- | sys/arch/arm/include/armreg.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h index b1ce7f9d296..d54448b3965 100644 --- a/sys/arch/arm/include/armreg.h +++ b/sys/arch/arm/include/armreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: armreg.h,v 1.5 2009/05/08 02:57:32 drahn Exp $ */ +/* $OpenBSD: armreg.h,v 1.6 2009/05/11 12:50:23 drahn Exp $ */ /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ /* @@ -290,6 +290,19 @@ #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ +/* below were added by V6 */ +#define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */ +#define CPU_CONTROL_U (1<<22) /* U: Unaligned */ +#define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */ +#define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */ +#define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */ + +/* added with v7 */ +#define CPU_CONTROL_NMFI (1<<27) /* NMFI: Non Maskable fast interrupt */ +#define CPU_CONTROL_TRE (1<<28) /* TRE: TEX Remap Enable */ +#define CPU_CONTROL_AFE (1<<29) /* AFE: Access Flag Enable */ +#define CPU_CONTROL_TE (1<<30) /* TE: Thumb Exception Enable */ + #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE /* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ |