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author | 2015-06-29 04:16:32 +0000 | |
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committer | 2015-06-29 04:16:32 +0000 | |
commit | 17c381cc468dd35e28c52d70f81f7cb3367e57ea (patch) | |
tree | 74f0a4381c10f3ef877e61e7c9ecbcb4531480eb | |
parent | Fix trap setup for double faults; error pointed out by Wei Liu a few months (diff) | |
download | wireguard-openbsd-17c381cc468dd35e28c52d70f81f7cb3367e57ea.tar.xz wireguard-openbsd-17c381cc468dd35e28c52d70f81f7cb3367e57ea.zip |
Implement membar_* for armv7 with the dmb instruction. The previous
sys/sys/atomic.h default of __sync_synchronize() resulted in "dmb sy",
a full system barrier for all memory operations. With this change
membar_producer() switches to "dmb st" (StoreStore).
earlier version ok rapha@
-rw-r--r-- | sys/arch/arm/include/atomic.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/sys/arch/arm/include/atomic.h b/sys/arch/arm/include/atomic.h index ba80cb085eb..3f2db652bc8 100644 --- a/sys/arch/arm/include/atomic.h +++ b/sys/arch/arm/include/atomic.h @@ -1,4 +1,4 @@ -/* $OpenBSD: atomic.h,v 1.10 2014/11/14 09:56:06 dlg Exp $ */ +/* $OpenBSD: atomic.h,v 1.11 2015/06/29 04:16:32 jsg Exp $ */ /* Public Domain */ @@ -193,5 +193,19 @@ atomic_clearbits_int(volatile unsigned int *uip, unsigned int v) restore_interrupts(cpsr); } +#if defined(CPU_ARMv7) +#define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0) + +#define membar_enter() __membar("dmb sy") +#define membar_exit() __membar("dmb sy") +#define membar_producer() __membar("dmb st") +#define membar_consumer() __membar("dmb sy") +#define membar_sync() __membar("dmb sy") + +#define virtio_membar_producer() __membar("dmb st") +#define virtio_membar_consumer() __membar("dmb sy") +#define virtio_membar_sync() __membar("dmb sy") +#endif /* CPU_ARMv7 */ + #endif /* defined(_KERNEL) */ #endif /* _ARM_ATOMIC_H_ */ |