Some more defines for bge(4). Mainly bits for accessing

info from the firmware. Some of it will be required for
further work on both older and newer chipsets.

Gleaned from the Linux tg3 driver.  From Brad.

1 files changed, 128 insertions, 3 deletions

diff --git a/sys/dev/pci/if_bgereg.h b/sys/dev/pci/if_bgereg.h
index 4948caf1df5..f564d2d4de8 100644
--- a/sys/dev/pci/if_bgereg.h
+++ b/sys/dev/pci/if_bgereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_bgereg.h,v 1.95 2009/06/04 00:59:21 naddy Exp $	*/
+/*	$OpenBSD: if_bgereg.h,v 1.96 2009/06/19 14:31:51 naddy Exp $	*/
 
 /*
  * Copyright (c) 2001 Wind River Systems
@@ -76,8 +76,17 @@
 #define BGE_SOFTWARE_GENCOMM		0x00000B50
 #define BGE_SOFTWARE_GENCOMM_SIG	0x00000B54
 #define BGE_SOFTWARE_GENCOMM_NICCFG	0x00000B58
+#define BGE_SOFTWARE_GENCOMM_VER	0x00000B5C
+#define    BGE_VER_SHIFT			16
 #define BGE_SOFTWARE_GENCOMM_FW		0x00000B78
-#define    BGE_FW_PAUSE			0x00000002
+#define    BGE_FW_PAUSE				0x00000002
+#define BGE_SOFTWARE_GENCOMM_NICCFG2	0x00000D38
+#define BGE_SOFTWARE_GENCOMM_NICCFG3	0x00000D3C
+#define BGE_SOFTWARE_GENCOMM_NICCFG4	0x00000D60
+#define    BGE_NICCFG4_GMII_MODE		0x00000002
+#define    BGE_NICCFG4_RGMII_STD_IBND_DISABLE	0x00000004
+#define    BGE_NICCFG4_RGMII_EXT_IBND_RX_EN	0x00000008
+#define    BGE_NICCFG4_RGMII_EXT_IBND_TX_EN	0x00000010
 #define BGE_SOFTWARE_GENCOMM_END	0x00000FFF
 #define BGE_UNMAPPED			0x00001000
 #define BGE_UNMAPPED_END		0x00001FFF
@@ -378,6 +387,7 @@
 #define BGE_PCISTATE_WANT_EXPROM	0x00000020
 #define BGE_PCISTATE_EXPROM_RETRY	0x00000040
 #define BGE_PCISTATE_FLATVIEW_MODE	0x00000100
+#define BGE_PCISTATE_RETRY_SAME_DMA	0x00002000
 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
 
 /*
@@ -614,6 +624,9 @@
 #define BGE_MAX_RX_FRAME_LOWAT		0x0504
 #define BGE_SERDES_CFG			0x0590
 #define BGE_SERDES_STS			0x0594
+#define BGE_PHYCFG1			0x05A0
+#define BGE_PHYCFG2			0x05A4
+#define BGE_EXT_RGMII_MODE		0x05A8
 #define BGE_SGDIG_CFG			0x05B0
 #define BGE_SGDIG_STS			0x05B4
 #define BGE_MAC_STATS			0x0800
@@ -768,6 +781,118 @@
 #define BGE_SERDESSTS_RXSTAT		0x0000000F /* receive status bits */
 #define BGE_SERDESSTS_CDET		0x00000010 /* comma code detected */
 
+/* PHYCFG1 config */
+#define BGE_PHYCFG1_RGMII_INT		0x00000001
+#define BGE_PHYCFG1_RGMII_EXT_RX_DEC	0x02000000
+#define BGE_PHYCFG1_RGMII_SND_STAT_EN	0x04000000
+#define BGE_PHYCFG1_TXC_DRV		0x20000000
+
+/* PHYCFG2 config */
+#define BGE_PHYCFG2_INBAND_ENABLE	0x00000001
+#define BGE_PHYCFG2_EMODE_MASK_MASK	0x000001c0
+#define BGE_PHYCFG2_EMODE_MASK_AC131	0x000000c0
+#define BGE_PHYCFG2_EMODE_MASK_50610	0x00000100
+#define BGE_PHYCFG2_EMODE_MASK_RT8211	0x00000000
+#define BGE_PHYCFG2_EMODE_MASK_RT8201	0x000001c0
+#define BGE_PHYCFG2_EMODE_COMP_MASK	0x00000e00
+#define BGE_PHYCFG2_EMODE_COMP_AC131	0x00000600
+#define BGE_PHYCFG2_EMODE_COMP_50610	0x00000400
+#define BGE_PHYCFG2_EMODE_COMP_RT8211	0x00000800
+#define BGE_PHYCFG2_EMODE_COMP_RT8201	0x00000000
+#define BGE_PHYCFG2_FMODE_MASK_MASK	0x00007000
+#define BGE_PHYCFG2_FMODE_MASK_AC131	0x00006000
+#define BGE_PHYCFG2_FMODE_MASK_50610	0x00004000
+#define BGE_PHYCFG2_FMODE_MASK_RT8211	0x00000000
+#define BGE_PHYCFG2_FMODE_MASK_RT8201	0x00007000
+#define BGE_PHYCFG2_FMODE_COMP_MASK	0x00038000
+#define BGE_PHYCFG2_FMODE_COMP_AC131	0x00030000
+#define BGE_PHYCFG2_FMODE_COMP_50610	0x00008000
+#define BGE_PHYCFG2_FMODE_COMP_RT8211	0x00038000
+#define BGE_PHYCFG2_FMODE_COMP_RT8201	0x00000000
+#define BGE_PHYCFG2_GMODE_MASK_MASK	0x001c0000
+#define BGE_PHYCFG2_GMODE_MASK_AC131	0x001c0000
+#define BGE_PHYCFG2_GMODE_MASK_50610	0x00100000
+#define BGE_PHYCFG2_GMODE_MASK_RT8211	0x00000000
+#define BGE_PHYCFG2_GMODE_MASK_RT8201	0x001c0000
+#define BGE_PHYCFG2_GMODE_COMP_MASK	0x00e00000
+#define BGE_PHYCFG2_GMODE_COMP_AC131	0x00e00000
+#define BGE_PHYCFG2_GMODE_COMP_50610	0x00000000
+#define BGE_PHYCFG2_GMODE_COMP_RT8211	0x00200000
+#define BGE_PHYCFG2_GMODE_COMP_RT8201	0x00000000
+#define BGE_PHYCFG2_ACT_MASK_MASK	0x03000000
+#define BGE_PHYCFG2_ACT_MASK_AC131	0x03000000
+#define BGE_PHYCFG2_ACT_MASK_50610	0x01000000
+#define BGE_PHYCFG2_ACT_MASK_RT8211	0x03000000
+#define BGE_PHYCFG2_ACT_MASK_RT8201	0x01000000
+#define BGE_PHYCFG2_ACT_COMP_MASK	0x0c000000
+#define BGE_PHYCFG2_ACT_COMP_AC131	0x00000000
+#define BGE_PHYCFG2_ACT_COMP_50610	0x00000000
+#define BGE_PHYCFG2_ACT_COMP_RT8211	0x00000000
+#define BGE_PHYCFG2_ACT_COMP_RT8201	0x08000000
+#define BGE_PHYCFG2_QUAL_MASK_MASK	0x30000000
+#define BGE_PHYCFG2_QUAL_MASK_AC131	0x30000000
+#define BGE_PHYCFG2_QUAL_MASK_50610	0x30000000
+#define BGE_PHYCFG2_QUAL_MASK_RT8211	0x30000000
+#define BGE_PHYCFG2_QUAL_MASK_RT8201	0x30000000
+#define BGE_PHYCFG2_QUAL_COMP_MASK	0xc0000000
+#define BGE_PHYCFG2_QUAL_COMP_AC131	0x00000000
+#define BGE_PHYCFG2_QUAL_COMP_50610	0x00000000
+#define BGE_PHYCFG2_QUAL_COMP_RT8211	0x00000000
+#define BGE_PHYCFG2_QUAL_COMP_RT8201	0x00000000
+#define BGE_PHYCFG2_50610_LED_MODES \
+        (BGE_PHYCFG2_EMODE_MASK_50610 | \
+         BGE_PHYCFG2_EMODE_COMP_50610 | \
+         BGE_PHYCFG2_FMODE_MASK_50610 | \
+         BGE_PHYCFG2_FMODE_COMP_50610 | \
+         BGE_PHYCFG2_GMODE_MASK_50610 | \
+         BGE_PHYCFG2_GMODE_COMP_50610 | \
+         BGE_PHYCFG2_ACT_MASK_50610 | \
+         BGE_PHYCFG2_ACT_COMP_50610 | \
+         BGE_PHYCFG2_QUAL_MASK_50610 | \
+         BGE_PHYCFG2_QUAL_COMP_50610)
+#define BGE_PHYCFG2_AC131_LED_MODES \
+        (BGE_PHYCFG2_EMODE_MASK_AC131 | \
+         BGE_PHYCFG2_EMODE_COMP_AC131 | \
+         BGE_PHYCFG2_FMODE_MASK_AC131 | \
+         BGE_PHYCFG2_FMODE_COMP_AC131 | \
+         BGE_PHYCFG2_GMODE_MASK_AC131 | \
+         BGE_PHYCFG2_GMODE_COMP_AC131 | \
+         BGE_PHYCFG2_ACT_MASK_AC131 | \
+         BGE_PHYCFG2_ACT_COMP_AC131 | \
+         BGE_PHYCFG2_QUAL_MASK_AC131 | \
+         BGE_PHYCFG2_QUAL_COMP_AC131)
+#define BGE_PHYCFG2_RTL8211C_LED_MODES \
+        (BGE_PHYCFG2_EMODE_MASK_RT8211 | \
+         BGE_PHYCFG2_EMODE_COMP_RT8211 | \
+         BGE_PHYCFG2_FMODE_MASK_RT8211 | \
+         BGE_PHYCFG2_FMODE_COMP_RT8211 | \
+         BGE_PHYCFG2_GMODE_MASK_RT8211 | \
+         BGE_PHYCFG2_GMODE_COMP_RT8211 | \
+         BGE_PHYCFG2_ACT_MASK_RT8211 | \
+         BGE_PHYCFG2_ACT_COMP_RT8211 | \
+         BGE_PHYCFG2_QUAL_MASK_RT8211 | \
+         BGE_PHYCFG2_QUAL_COMP_RT8211)
+#define BGE_PHYCFG2_RTL8201E_LED_MODES \
+        (BGE_PHYCFG2_EMODE_MASK_RT8201 | \
+         BGE_PHYCFG2_EMODE_COMP_RT8201 | \
+         BGE_PHYCFG2_FMODE_MASK_RT8201 | \
+         BGE_PHYCFG2_FMODE_COMP_RT8201 | \
+         BGE_PHYCFG2_GMODE_MASK_RT8201 | \
+         BGE_PHYCFG2_GMODE_COMP_RT8201 | \
+         BGE_PHYCFG2_ACT_MASK_RT8201 | \
+         BGE_PHYCFG2_ACT_COMP_RT8201 | \
+         BGE_PHYCFG2_QUAL_MASK_RT8201 | \
+         BGE_PHYCFG2_QUAL_COMP_RT8201)
+
+/* EXT_RGMII_MODE config */
+#define BGE_RGMII_MODE_TX_ENABLE	0x00000001
+#define BGE_RGMII_MODE_TX_LOWPWR	0x00000002
+#define BGE_RGMII_MODE_TX_RESET		0x00000004
+#define BGE_RGMII_MODE_RX_INT_B		0x00000100
+#define BGE_RGMII_MODE_RX_QUALITY	0x00000200
+#define BGE_RGMII_MODE_RX_ACTIVITY	0x00000400
+#define BGE_RGMII_MODE_RX_ENG_DET	0x00000800
+
 /* SGDIG config (not documented) */
 #define BGE_SGDIGCFG_PAUSE_CAP		0x00000800
 #define BGE_SGDIGCFG_ASYM_PAUSE		0x00001000
@@ -1917,7 +2042,7 @@
  * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
  * driver to synchronize with the firmware.
  */
-#define BGE_MAGIC_NUMBER                0x4B657654
+#define BGE_MAGIC_NUMBER		0x4B657654
 
 typedef struct {
 	u_int32_t		bge_addr_hi;