make use of udelay to reduce the diff to linux

7 files changed, 77 insertions, 77 deletions

diff --git a/sys/dev/pci/drm/i915/dvo_ivch.c b/sys/dev/pci/drm/i915/dvo_ivch.c
index f079240ab27..e5d1bd07039 100644
--- a/sys/dev/pci/drm/i915/dvo_ivch.c
+++ b/sys/dev/pci/drm/i915/dvo_ivch.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dvo_ivch.c,v 1.2 2013/03/30 12:36:50 kettenis Exp $	*/
+/*	$OpenBSD: dvo_ivch.c,v 1.3 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  * Copyright © 2006 Intel Corporation
  *
@@ -333,10 +333,10 @@ ivch_dpms(struct intel_dvo_device *dvo, bool enable)
 
 		if (((vr30 & VR30_PANEL_ON) != 0) == enable)
 			break;
-		delay(1000);
+		udelay(1000);
 	}
 	/* wait some more; vch may fail to resync sometimes without this */
-	delay(16 * 1000);
+	udelay(16 * 1000);
 }
 
 bool
diff --git a/sys/dev/pci/drm/i915/i915_suspend.c b/sys/dev/pci/drm/i915/i915_suspend.c
index 68ad2972288..7da8cf98c00 100644
--- a/sys/dev/pci/drm/i915/i915_suspend.c
+++ b/sys/dev/pci/drm/i915/i915_suspend.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: i915_suspend.c,v 1.2 2013/07/05 07:20:27 jsg Exp $	*/
+/*	$OpenBSD: i915_suspend.c,v 1.3 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  *
  * Copyright 2008 (c) Intel Corporation
@@ -496,19 +496,19 @@ i915_restore_modeset_reg(struct drm_device *dev)
 		I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A &
 			   ~DPLL_VCO_ENABLE);
 		POSTING_READ(dpll_a_reg);
-		DRM_UDELAY(150);
+		udelay(150);
 	}
 	I915_WRITE(fpa0_reg, dev_priv->regfile.saveFPA0);
 	I915_WRITE(fpa1_reg, dev_priv->regfile.saveFPA1);
 	/* Actually enable it */
 	I915_WRITE(dpll_a_reg, dev_priv->regfile.saveDPLL_A);
 	POSTING_READ(dpll_a_reg);
-	DRM_UDELAY(150);
+	udelay(150);
 	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 		I915_WRITE(_DPLL_A_MD, dev_priv->regfile.saveDPLL_A_MD);
 		POSTING_READ(_DPLL_A_MD);
 	}
-	DRM_UDELAY(150);
+	udelay(150);
 
 	/* Restore mode */
 	I915_WRITE(_HTOTAL_A, dev_priv->regfile.saveHTOTAL_A);
@@ -565,19 +565,19 @@ i915_restore_modeset_reg(struct drm_device *dev)
 		I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B &
 			   ~DPLL_VCO_ENABLE);
 		POSTING_READ(dpll_b_reg);
-		DRM_UDELAY(150);
+		udelay(150);
 	}
 	I915_WRITE(fpb0_reg, dev_priv->regfile.saveFPB0);
 	I915_WRITE(fpb1_reg, dev_priv->regfile.saveFPB1);
 	/* Actually enable it */
 	I915_WRITE(dpll_b_reg, dev_priv->regfile.saveDPLL_B);
 	POSTING_READ(dpll_b_reg);
-	DRM_UDELAY(150);
+	udelay(150);
 	if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
 		I915_WRITE(_DPLL_B_MD, dev_priv->regfile.saveDPLL_B_MD);
 		POSTING_READ(_DPLL_B_MD);
 	}
-	DRM_UDELAY(150);
+	udelay(150);
 
 	/* Restore mode */
 	I915_WRITE(_HTOTAL_B, dev_priv->regfile.saveHTOTAL_B);
@@ -832,7 +832,7 @@ i915_restore_display(struct drm_device *dev)
 	I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
 	I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
 	POSTING_READ(VGA_PD);
-	DRM_UDELAY(150);
+	udelay(150);
 
 	i915_restore_vga(dev);
 }
diff --git a/sys/dev/pci/drm/i915/intel_ddi.c b/sys/dev/pci/drm/i915/intel_ddi.c
index 8682b1d9415..15399503913 100644
--- a/sys/dev/pci/drm/i915/intel_ddi.c
+++ b/sys/dev/pci/drm/i915/intel_ddi.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intel_ddi.c,v 1.3 2013/07/05 07:20:27 jsg Exp $	*/
+/*	$OpenBSD: intel_ddi.c,v 1.4 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  * Copyright © 2012 Intel Corporation
  *
@@ -168,7 +168,7 @@ intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 	int i;
 
 	for (i = 0; i < 8; i++) {
-		DELAY(1);
+		udelay(1);
 		if (I915_READ(reg) & DDI_BUF_IS_IDLE)
 			return;
 	}
@@ -206,7 +206,7 @@ hsw_fdi_link_train(struct drm_crtc *crtc)
 		     FDI_RX_PLL_ENABLE | ((intel_crtc->fdi_lanes - 1) << 19);
 	I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
 	POSTING_READ(_FDI_RXA_CTL);
-	DELAY(220);
+	udelay(220);
 
 	/* Switch from Rawclk to PCDclk */
 	rx_ctl_val |= FDI_PCDCLK;
@@ -235,7 +235,7 @@ hsw_fdi_link_train(struct drm_crtc *crtc)
 			   hsw_ddi_buf_ctl_values[i / 2]);
 		POSTING_READ(DDI_BUF_CTL(PORT_E));
 
-		DELAY(600);
+		udelay(600);
 
 		/* Program PCH FDI Receiver TU */
 		I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
@@ -246,7 +246,7 @@ hsw_fdi_link_train(struct drm_crtc *crtc)
 		POSTING_READ(_FDI_RXA_CTL);
 
 		/* Wait for FDI receiver lane calibration */
-		DELAY(30);
+		udelay(30);
 
 		/* Unset FDI_RX_MISC pwrdn lanes */
 		temp = I915_READ(_FDI_RXA_MISC);
@@ -255,7 +255,7 @@ hsw_fdi_link_train(struct drm_crtc *crtc)
 		POSTING_READ(_FDI_RXA_MISC);
 
 		/* Wait for FDI auto training time */
-		DELAY(5);
+		udelay(5);
 
 		temp = I915_READ(DP_TP_STATUS(PORT_E));
 		if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
@@ -940,7 +940,7 @@ intel_ddi_pll_mode_set(struct drm_crtc *crtc, int clock)
 	}
 
 	I915_WRITE(reg, val);
-	DELAY(20);
+	udelay(20);
 
 	return true;
 }
@@ -1444,7 +1444,7 @@ intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
 	I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
 	POSTING_READ(DDI_BUF_CTL(port));
 
-	DELAY(600);
+	udelay(600);
 }
 
 void
diff --git a/sys/dev/pci/drm/i915/intel_display.c b/sys/dev/pci/drm/i915/intel_display.c
index 6d9aa322117..b5a0a9afe35 100644
--- a/sys/dev/pci/drm/i915/intel_display.c
+++ b/sys/dev/pci/drm/i915/intel_display.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intel_display.c,v 1.8 2013/07/05 07:20:27 jsg Exp $	*/
+/*	$OpenBSD: intel_display.c,v 1.9 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  * Copyright © 2006-2007 Intel Corporation
  *
@@ -1875,13 +1875,13 @@ intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
 	/* We do this three times for luck */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
-	DELAY(150); /* wait for warmup */
+	udelay(150); /* wait for warmup */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
-	DELAY(150); /* wait for warmup */
+	udelay(150); /* wait for warmup */
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
-	DELAY(150); /* wait for warmup */
+	udelay(150); /* wait for warmup */
 }
 
 /**
@@ -2042,7 +2042,7 @@ ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
 	val |= DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
-	DELAY(200);
+	udelay(200);
 
 	pll->on = true;
 }
@@ -2087,7 +2087,7 @@ intel_disable_pch_pll(struct intel_crtc *intel_crtc)
 	val &= ~DPLL_VCO_ENABLE;
 	I915_WRITE(reg, val);
 	POSTING_READ(reg);
-	DELAY(200);
+	udelay(200);
 
 	pll->on = false;
 }
@@ -2875,7 +2875,7 @@ ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 	I915_WRITE(DP_A, dpa_ctl);
 
 	POSTING_READ(DP_A);
-	DELAY(500);
+	udelay(500);
 }
 
 void
@@ -2912,7 +2912,7 @@ intel_fdi_normal_train(struct drm_crtc *crtc)
 
 	/* wait one idle pattern time */
 	POSTING_READ(reg);
-	DELAY(1000);
+	udelay(1000);
 
 	/* IVB wants error correction enabled */
 	if (IS_IVYBRIDGE(dev))
@@ -2967,7 +2967,7 @@ ironlake_fdi_link_train(struct drm_crtc *crtc)
 	temp &= ~FDI_RX_BIT_LOCK;
 	I915_WRITE(reg, temp);
 	I915_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	/* enable CPU FDI TX and PCH FDI RX */
 	reg = FDI_TX_CTL(pipe);
@@ -2985,7 +2985,7 @@ ironlake_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	/* Ironlake workaround, enable clock pointer after FDI enable*/
 	I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
@@ -3020,7 +3020,7 @@ ironlake_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	reg = FDI_RX_IIR(pipe);
 	for (tries = 0; tries < 5; tries++) {
@@ -3066,7 +3066,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	/* enable CPU FDI TX and PCH FDI RX */
 	reg = FDI_TX_CTL(pipe);
@@ -3095,7 +3095,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
@@ -3105,7 +3105,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(reg, temp);
 
 		POSTING_READ(reg);
-		DELAY(500);
+		udelay(500);
 
 		for (retry = 0; retry < 5; retry++) {
 			reg = FDI_RX_IIR(pipe);
@@ -3116,7 +3116,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 				DRM_DEBUG_KMS("FDI train 1 done.\n");
 				break;
 			}
-			DELAY(50);
+			udelay(50);
 		}
 		if (retry < 5)
 			break;
@@ -3148,7 +3148,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
@@ -3158,7 +3158,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(reg, temp);
 
 		POSTING_READ(reg);
-		DELAY(500);
+		udelay(500);
 
 		for (retry = 0; retry < 5; retry++) {
 			reg = FDI_RX_IIR(pipe);
@@ -3169,7 +3169,7 @@ gen6_fdi_link_train(struct drm_crtc *crtc)
 				DRM_DEBUG_KMS("FDI train 2 done.\n");
 				break;
 			}
-			DELAY(50);
+			udelay(50);
 		}
 		if (retry < 5)
 			break;
@@ -3199,7 +3199,7 @@ ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
 		      I915_READ(FDI_RX_IIR(pipe)));
@@ -3228,7 +3228,7 @@ ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp | FDI_RX_ENABLE);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
@@ -3238,7 +3238,7 @@ ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(reg, temp);
 
 		POSTING_READ(reg);
-		DELAY(500);
+		udelay(500);
 
 		reg = FDI_RX_IIR(pipe);
 		temp = I915_READ(reg);
@@ -3270,7 +3270,7 @@ ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp);
 
 	POSTING_READ(reg);
-	DELAY(150);
+	udelay(150);
 
 	for (i = 0; i < 4; i++) {
 		reg = FDI_TX_CTL(pipe);
@@ -3280,7 +3280,7 @@ ivb_manual_fdi_link_train(struct drm_crtc *crtc)
 		I915_WRITE(reg, temp);
 
 		POSTING_READ(reg);
-		DELAY(500);
+		udelay(500);
 
 		reg = FDI_RX_IIR(pipe);
 		temp = I915_READ(reg);
@@ -3316,14 +3316,14 @@ ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
 	I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
 
 	POSTING_READ(reg);
-	DELAY(200);
+	udelay(200);
 
 	/* Switch from Rawclk to PCDclk */
 	temp = I915_READ(reg);
 	I915_WRITE(reg, temp | FDI_PCDCLK);
 
 	POSTING_READ(reg);
-	DELAY(200);
+	udelay(200);
 
 	/* On Haswell, the PLL configuration for ports and pipes is handled
 	 * separately, as part of DDI setup */
@@ -3335,7 +3335,7 @@ ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
 			I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
 
 			POSTING_READ(reg);
-			DELAY(100);
+			udelay(100);
 		}
 	}
 }
@@ -3359,7 +3359,7 @@ ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
 	I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
 
 	POSTING_READ(reg);
-	DELAY(100);
+	udelay(100);
 
 	reg = FDI_RX_CTL(pipe);
 	temp = I915_READ(reg);
@@ -3367,7 +3367,7 @@ ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
 
 	/* Wait for the clocks to turn off. */
 	POSTING_READ(reg);
-	DELAY(100);
+	udelay(100);
 }
 
 void
@@ -3392,7 +3392,7 @@ ironlake_fdi_disable(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
 
 	POSTING_READ(reg);
-	DELAY(100);
+	udelay(100);
 
 	/* Ironlake workaround, disable clock pointer after downing FDI */
 	if (HAS_PCH_IBX(dev)) {
@@ -3421,7 +3421,7 @@ ironlake_fdi_disable(struct drm_crtc *crtc)
 	I915_WRITE(reg, temp);
 
 	POSTING_READ(reg);
-	DELAY(100);
+	udelay(100);
 }
 
 bool
@@ -3566,7 +3566,7 @@ lpt_program_iclkip(struct drm_crtc *crtc)
 	intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
 
 	/* Wait for initialization time */
-	DELAY(24);
+	udelay(24);
 
 	I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
 }
@@ -3792,7 +3792,7 @@ prepare: /* separate function? */
 	/* Wait for the clocks to stabilize before rewriting the regs */
 	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(pll->pll_reg);
-	DELAY(150);
+	udelay(150);
 
 	I915_WRITE(pll->fp0_reg, fp);
 	I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
@@ -3809,7 +3809,7 @@ intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
 	int retries;
 
 	temp = I915_READ(dslreg);
-	DELAY(500);
+	udelay(500);
 	for (retries = 10; retries > 0; retries--) {
 		if (I915_READ(dslreg) != temp)
 			break;
@@ -4964,7 +4964,7 @@ vlv_update_pll(struct drm_crtc *crtc,
 
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(DPLL(pipe));
-	DELAY(150);
+	udelay(150);
 
 	temp = 0;
 	if (is_sdvo) {
@@ -5071,7 +5071,7 @@ i9xx_update_pll(struct drm_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
-	DELAY(150);
+	udelay(150);
 
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
@@ -5087,7 +5087,7 @@ i9xx_update_pll(struct drm_crtc *crtc,
 
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(DPLL(pipe));
-	DELAY(150);
+	udelay(150);
 
 	if (INTEL_INFO(dev)->gen >= 4) {
 		u32 temp = 0;
@@ -5149,7 +5149,7 @@ i8xx_update_pll(struct drm_crtc *crtc,
 	dpll |= DPLL_VCO_ENABLE;
 	I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
 	POSTING_READ(DPLL(pipe));
-	DELAY(150);
+	udelay(150);
 
 	/* The LVDS pin pair needs to be on before the DPLLs are enabled.
 	 * This is an exception to the general rule that mode_set doesn't turn
@@ -5162,7 +5162,7 @@ i8xx_update_pll(struct drm_crtc *crtc,
 
 	/* Wait for the clocks to stabilize. */
 	POSTING_READ(DPLL(pipe));
-	DELAY(150);
+	udelay(150);
 
 	/* The pixel multiplier can only be updated once the
 	 * DPLL is enabled and the clocks are stable.
@@ -5483,7 +5483,7 @@ ironlake_init_pch_refclk(struct drm_device *dev)
 		/* Get SSC going before enabling the outputs */
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
-		DELAY(200);
+		udelay(200);
 
 		temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
 
@@ -5500,7 +5500,7 @@ ironlake_init_pch_refclk(struct drm_device *dev)
 
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
-		DELAY(200);
+		udelay(200);
 	} else {
 		DRM_DEBUG_KMS("Disabling SSC entirely\n");
 
@@ -5511,7 +5511,7 @@ ironlake_init_pch_refclk(struct drm_device *dev)
 
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
-		DELAY(200);
+		udelay(200);
 
 		/* Turn off the SSC source */
 		temp &= ~DREF_SSC_SOURCE_MASK;
@@ -5522,7 +5522,7 @@ ironlake_init_pch_refclk(struct drm_device *dev)
 
 		I915_WRITE(PCH_DREF_CONTROL, temp);
 		POSTING_READ(PCH_DREF_CONTROL);
-		DELAY(200);
+		udelay(200);
 	}
 }
 
@@ -5558,7 +5558,7 @@ lpt_init_pch_refclk(struct drm_device *dev)
 	tmp |= SBI_SSCCTL_PATHALT;
 	intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
 
-	DELAY(24);
+	udelay(24);
 
 	tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
 	tmp &= ~SBI_SSCCTL_PATHALT;
@@ -6285,7 +6285,7 @@ ironlake_crtc_mode_set(struct drm_crtc *crtc,
 
 		/* Wait for the clocks to stabilize. */
 		POSTING_READ(intel_crtc->pch_pll->pll_reg);
-		DELAY(150);
+		udelay(150);
 
 		/* The pixel multiplier can only be updated once the
 		 * DPLL is enabled and the clocks are stable.
@@ -6501,7 +6501,7 @@ haswell_crtc_mode_set(struct drm_crtc *crtc,
 
 			/* Wait for the clocks to stabilize. */
 			POSTING_READ(intel_crtc->pch_pll->pll_reg);
-			DELAY(150);
+			udelay(150);
 
 			/* The pixel multiplier can only be updated once the
 			 * DPLL is enabled and the clocks are stable.
@@ -9573,7 +9573,7 @@ i915_disable_vga(struct drm_device *dev)
 #if 0
 	vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 #endif
-	DELAY(300);
+	udelay(300);
 
 	I915_WRITE(vga_reg, VGA_DISP_DISABLE);
 	POSTING_READ(vga_reg);
diff --git a/sys/dev/pci/drm/i915/intel_dp.c b/sys/dev/pci/drm/i915/intel_dp.c
index 60e6306aea2..fe5587bd96f 100644
--- a/sys/dev/pci/drm/i915/intel_dp.c
+++ b/sys/dev/pci/drm/i915/intel_dp.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intel_dp.c,v 1.6 2013/07/05 07:20:27 jsg Exp $	*/
+/*	$OpenBSD: intel_dp.c,v 1.7 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  * Copyright © 2008 Intel Corporation
  *
@@ -558,7 +558,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
 			status = I915_READ(ch_ctl);
 			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 				break;
-			DELAY(100);
+			udelay(100);
 		}
 
 		/* Clear done status and any errors */
@@ -634,7 +634,7 @@ intel_dp_aux_native_write(struct intel_dp *intel_dp,
 		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 			break;
 		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
-			DELAY(100);
+			udelay(100);
 		else
 			return -EIO;
 	}
@@ -683,7 +683,7 @@ intel_dp_aux_native_read(struct intel_dp *intel_dp,
 			return ret - 1;
 		}
 		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
-			DELAY(100);
+			udelay(100);
 		else
 			return -EIO;
 	}
@@ -755,7 +755,7 @@ intel_dp_i2c_aux_ch(struct i2c_controller *adapter, int mode,
 			DRM_DEBUG_KMS("aux_ch native nack\n");
 			return -EIO;
 		case AUX_NATIVE_REPLY_DEFER:
-			DELAY(100);
+			udelay(100);
 			continue;
 		default:
 			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
@@ -774,7 +774,7 @@ intel_dp_i2c_aux_ch(struct i2c_controller *adapter, int mode,
 			return -EIO;
 		case AUX_I2C_REPLY_DEFER:
 			DRM_DEBUG_KMS("aux_i2c defer\n");
-			DELAY(100);
+			udelay(100);
 			break;
 		default:
 			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
@@ -1401,7 +1401,7 @@ ironlake_edp_pll_on(struct intel_dp *intel_dp)
 	intel_dp->DP |= DP_PLL_ENABLE;
 	I915_WRITE(DP_A, intel_dp->DP);
 	POSTING_READ(DP_A);
-	DELAY(200);
+	udelay(200);
 }
 
 void
@@ -1427,7 +1427,7 @@ ironlake_edp_pll_off(struct intel_dp *intel_dp)
 	dpa_ctl &= ~DP_PLL_ENABLE;
 	I915_WRITE(DP_A, dpa_ctl);
 	POSTING_READ(DP_A);
-	DELAY(200);
+	udelay(200);
 }
 
 /* If the sink supports it, try to set the power state appropriately */
diff --git a/sys/dev/pci/drm/i915/intel_pm.c b/sys/dev/pci/drm/i915/intel_pm.c
index cd454eee93d..22ab2ca4d6b 100644
--- a/sys/dev/pci/drm/i915/intel_pm.c
+++ b/sys/dev/pci/drm/i915/intel_pm.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intel_pm.c,v 1.8 2013/07/05 07:20:27 jsg Exp $	*/
+/*	$OpenBSD: intel_pm.c,v 1.9 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  * Copyright © 2012 Intel Corporation
  *
@@ -4613,7 +4613,7 @@ __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
 		int loop = 500;
 		u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 		while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
-			DELAY(10);
+			udelay(10);
 			fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
 		}
 		if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
diff --git a/sys/dev/pci/drm/i915/intel_sdvo.c b/sys/dev/pci/drm/i915/intel_sdvo.c
index a8431aaa3e7..39e4d7fd30d 100644
--- a/sys/dev/pci/drm/i915/intel_sdvo.c
+++ b/sys/dev/pci/drm/i915/intel_sdvo.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intel_sdvo.c,v 1.9 2013/07/05 07:20:27 jsg Exp $	*/
+/*	$OpenBSD: intel_sdvo.c,v 1.10 2013/07/08 09:47:45 jsg Exp $	*/
 /*
  * Copyright 2006 Dave Airlie <airlied@linux.ie>
  * Copyright © 2006-2007 Intel Corporation
@@ -675,7 +675,7 @@ intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
 		if (retry < 10)
 			drm_msleep(15, "915srr");
 		else
-			DELAY(15);
+			udelay(15);
 
 		if (!intel_sdvo_read_byte(intel_sdvo,
 					  SDVO_I2C_CMD_STATUS,