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author | 2020-10-26 22:05:01 +0000 | |
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committer | 2020-10-26 22:05:01 +0000 | |
commit | 2c3ebbac5f6f3cd3a2ab5b778455a04feae2fabc (patch) | |
tree | 01a593e250fa5c21eff4d205fdd327ef894f2fe0 | |
parent | Define ws_get/set_param for macppc using ofw brightness and backlight (diff) | |
download | wireguard-openbsd-2c3ebbac5f6f3cd3a2ab5b778455a04feae2fabc.tar.xz wireguard-openbsd-2c3ebbac5f6f3cd3a2ab5b778455a04feae2fabc.zip |
Make mapping the "I/O Space" BAR optional. POWER9 systems don't support
"I/O Space" on their PCIe host bridges and for most (all) Radeon variants
there is an alternative method to access the relevant registers.
ok jsg@
-rw-r--r-- | sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c | 21 |
1 files changed, 7 insertions, 14 deletions
diff --git a/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c b/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c index f706d5e8409..a77a6c97ff9 100644 --- a/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c +++ b/sys/dev/pci/drm/amd/amdgpu/amdgpu_kms.c @@ -1609,22 +1609,15 @@ amdgpu_attach(struct device *parent, struct device *self, void *aux) adev->fb_aper_offset = base; } - for (i = PCI_MAPREG_START; i < PCI_MAPREG_END ;) { + for (i = PCI_MAPREG_START; i < PCI_MAPREG_END; i += 4) { type = pci_mapreg_type(pa->pa_pc, pa->pa_tag, i); - if (PCI_MAPREG_TYPE(type) != PCI_MAPREG_TYPE_IO) { - if (type & PCI_MAPREG_MEM_TYPE_64BIT) - i += 8; - else - i += 4; - continue; - } - if (pci_mapreg_map(pa, i, type, 0, - &adev->rio_mem_bst, &adev->rio_mem_bsh, NULL, - &adev->rio_mem_size, 0)) { - printf(": can't map rio space\n"); - return; + if (type == PCI_MAPREG_TYPE_IO) { + pci_mapreg_map(pa, i, type, 0, &adev->rio_mem_bst, + &adev->rio_mem_bsh, NULL, &adev->rio_mem_size, 0); + break; } - break; + if (type == PCI_MAPREG_MEM_TYPE_64BIT) + i += 4; } if (adev->family >= CHIP_BONAIRE) { |