diff options
| author |   visa <visa@openbsd.org> | 2016-10-09 03:29:53 +0000 |
|---|---|---|
| committer | visa <visa@openbsd.org> | 2016-10-09 03:29:53 +0000 |
| commit | 313bdb8503318cfd738cc4cf9bebb20cdab4e36c (patch) | |
| tree | 2b12809f1b75449db98456466ddbfa67f005cdec | |
| parent | Pass `prid' properly to pmon_init(). (diff) | |
| download | wireguard-openbsd-313bdb8503318cfd738cc4cf9bebb20cdab4e36c.tar.xz wireguard-openbsd-313bdb8503318cfd738cc4cf9bebb20cdab4e36c.zip | |
Do not use MIPS64r2 instructions on Loongson 2. Now, a generic loongson
kernel has to learn a new trick in order to use TLB RI/XI on 3A2000.
| -rw-r--r-- | sys/arch/mips64/include/pte.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/arch/mips64/include/pte.h b/sys/arch/mips64/include/pte.h index eb385fa7d40..d982b221c8b 100644 --- a/sys/arch/mips64/include/pte.h +++ b/sys/arch/mips64/include/pte.h @@ -1,4 +1,4 @@ -/* $OpenBSD: pte.h,v 1.20 2016/09/06 13:41:29 visa Exp $ */ +/* $OpenBSD: pte.h,v 1.21 2016/10/09 03:29:53 visa Exp $ */ /* * Copyright (c) 1988 University of Utah. @@ -76,7 +76,7 @@ typedef u_int32_t pt_entry_t; #define PTE_OFFS 4 #endif -#ifdef CPU_MIPS64R2 +#if defined(CPU_MIPS64R2) && !defined(CPU_LOONGSON2) #define PTE_CLEAR_SWBITS(reg) \ .set push; \ .set mips64r2; \ |