Remove the qli driver for QLogic 4010 & 4022 iSCSI.

It was never enabled and is apparently unfinished.

ok deraadt@ krw@ claudio@ kettenis@

4 files changed, 2 insertions, 1823 deletions

diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC
index 7002ce796b7..ec307466322 100644
--- a/sys/arch/i386/conf/GENERIC
+++ b/sys/arch/i386/conf/GENERIC
@@ -1,4 +1,4 @@
-#	$OpenBSD: GENERIC,v 1.778 2014/07/11 21:58:09 tedu Exp $
+#	$OpenBSD: GENERIC,v 1.779 2014/07/12 11:33:13 jsg Exp $
 #
 # For further information on compiling OpenBSD kernels, see the config(8)
 # man page.
@@ -452,7 +452,6 @@ ips*	at pci?			# IBM ServeRAID controllers
 qlw*	at pci?			# QLogic ISP SCSI
 qla*	at pci?			# QLogic ISP 2[123]xx FibreChannel
 qle*	at pci?			# QLogic ISP 2[45]xx FibreChannel
-#qli*	at pci?			# QLogic 4010 & 4022 iSCSI
 aic0	at isa? port 0x340 irq 11 # Adaptec 152[02] SCSI controllers
 aic*	at pcmcia?		# PCMCIA based aic SCSI controllers
 aic*	at isapnp?		# isapnp configured aic SCSI controllers
diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci
index e42e489fefe..f0676268757 100644
--- a/sys/dev/pci/files.pci
+++ b/sys/dev/pci/files.pci
@@ -1,4 +1,4 @@
-#	$OpenBSD: files.pci,v 1.306 2014/04/12 05:06:58 dlg Exp $
+#	$OpenBSD: files.pci,v 1.307 2014/07/12 11:33:13 jsg Exp $
 #	$NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $
 #
 # Config file and device description for machine-independent PCI code.
@@ -247,11 +247,6 @@ file	dev/pci/sli_pci.c		sli_pci
 attach	sili at pci with sili_pci
 file	dev/pci/sili_pci.c		sili_pci
 
-# QLogic iSCSI HBAs
-device	qli: scsi
-attach	qli at pci with qli_pci
-file	dev/pci/qli_pci.c		qli_pci
-
 # Ethernet driver for DC21040-based boards
 device	de: ether, ifnet, ifmedia
 attach	de at pci
diff --git a/sys/dev/pci/qli_pci.c b/sys/dev/pci/qli_pci.c
deleted file mode 100644
index 159838b50e1..00000000000
--- a/sys/dev/pci/qli_pci.c
+++ /dev/null
@@ -1,1168 +0,0 @@
-/* $OpenBSD: qli_pci.c,v 1.21 2014/02/21 18:47:35 deraadt Exp $ */
-/*
- * Copyright (c) 2007 Marco Peereboom <marco@peereboom.us>
- * Copyright (c) 2007 David Collins <dave@davec.name>
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include "bio.h"
-
-#include <sys/param.h>
-#include <sys/systm.h>
-#include <sys/buf.h>
-#include <sys/ioctl.h>
-#include <sys/device.h>
-#include <sys/kernel.h>
-#include <sys/malloc.h>
-#include <sys/proc.h>
-#include <sys/rwlock.h>
-
-#include <dev/pci/pcidevs.h>
-#include <dev/pci/pcivar.h>
-
-#include <machine/bus.h>
-
-#include <scsi/scsi_all.h>
-#include <scsi/scsi_disk.h>
-#include <scsi/scsiconf.h>
-
-#include <dev/pci/qlireg.h>
-
-#if NBIO > 0
-#include <dev/biovar.h>
-#include <sys/sensors.h>
-#endif /* NBIO > 0 */
-
-#define DEVNAME(_s)     ((_s)->sc_dev.dv_xname)
-
-struct qli_softc {
-	struct device		sc_dev;
-
-	void			*sc_ih;
-	bus_space_tag_t		sc_memt;
-	bus_space_handle_t	sc_memh;
-	bus_size_t		sc_memsize;
-	bus_dma_tag_t		sc_dmat;
-
-	volatile struct qli_reg	*sc_reg;	/* pointer to registers */
-
-	/* scsi ioctl from sd device */
-	int			(*sc_ioctl)(struct device *, u_long, caddr_t);
-
-	int			sc_ql4010;	/* if set we are a QL4010 HBA */
-	u_int32_t		sc_resource;	/* nr for semaphores */
-
-	struct rwlock		sc_lock;
-
-	/* mailbox members */
-	struct rwlock		sc_mbox_lock;
-	u_int32_t		sc_mbox[QLI_MBOX_SIZE];
-	int			sc_mbox_flags;
-#define QLI_MBOX_F_INVALID	(0x00)
-#define QLI_MBOX_F_PENDING	(0x01)
-#define QLI_MBOX_F_WAKEUP	(0x02)
-#define QLI_MBOX_F_POLL		(0x04)
-
-	/* firmware control block */
-	struct qli_mem		*sc_fw_cb;
-
-	/* queues */
-	unsigned int		sc_queues_len;
-	struct qli_mem		*sc_queues;
-	bus_addr_t		sc_request_dva;
-	struct qli_queue_entry	*sc_request_ring;
-};
-
-/* #define QLI_DEBUG */
-#ifdef QLI_DEBUG
-#define DPRINTF(x...)		do { if (qli_debug) printf(x); } while(0)
-#define DNPRINTF(n,x...)	do { if (qli_debug & n) printf(x); } while(0)
-#define	QLI_D_CMD		0x0001
-#define	QLI_D_INTR		0x0002
-#define	QLI_D_MISC		0x0004
-#define	QLI_D_DMA		0x0008
-#define	QLI_D_IOCTL		0x0010
-#define	QLI_D_RW		0x0020
-#define	QLI_D_MEM		0x0040
-#define	QLI_D_CCB		0x0080
-#define	QLI_D_SEM		0x0100
-#define	QLI_D_MBOX		0x0200
-
-u_int32_t	qli_debug = 0
-		    | QLI_D_CMD
-		    | QLI_D_INTR
-		    | QLI_D_MISC
-		    | QLI_D_DMA
-		    | QLI_D_IOCTL
-		    | QLI_D_RW
-		    | QLI_D_MEM
-		    | QLI_D_CCB
-		    | QLI_D_SEM
-		    | QLI_D_MBOX
-		;
-
-void		qli_dump_mbox(struct qli_softc *, u_int32_t *);
-#else
-#define DPRINTF(x...)
-#define DNPRINTF(n,x...)
-#define qli_dump_mbox(x, y)
-#endif /* QLI_DEBUG */
-
-struct qli_mem {
-	bus_dmamap_t		am_map;
-	bus_dma_segment_t	am_seg;
-	size_t			am_size;
-	caddr_t			am_kva;
-};
-
-#define QLIMEM_MAP(_am)		((_am)->am_map)
-#define QLIMEM_DVA(_am)		((_am)->am_map->dm_segs[0].ds_addr)
-#define QLIMEM_KVA(_am)		((void *)(_am)->am_kva)
-#define QLIMEM_ALIGN		(MAX(QLI_REQUESTQ_DEPTH, QLI_RESPONSEQ_DEPTH) *\
-				    sizeof(struct qli_queue_entry))
-
-struct qli_mem	*qli_allocmem(struct qli_softc *, size_t);
-void		qli_freemem(struct qli_softc *, struct qli_mem *);
-void		qli_scsi_cmd(struct scsi_xfer *);
-int		qli_scsi_ioctl(struct scsi_link *, u_long, caddr_t, int,
-		    struct proc *);
-void		qliminphys(struct buf *bp, struct scsi_link *sl);
-void		qli_disable_interrupts(struct qli_softc *);
-void		qli_enable_interrupts(struct qli_softc *);
-int		qli_pci_find_device(void *);
-int		qli_pci_match(struct device *, void *, void *);
-void		qli_pci_attach(struct device *, struct device *, void *);
-int		qli_ioctl(struct device *, u_long, caddr_t);
-int		qli_lock_sem(struct qli_softc *, u_int32_t, u_int32_t);
-void		qli_unlock_sem(struct qli_softc *, u_int32_t);
-void		qli_eeprom_out(struct qli_softc *, u_int32_t);
-u_int16_t	qli_read_nvram(struct qli_softc *, u_int32_t);
-int		qli_validate_nvram(struct qli_softc *);
-int		qli_lock_driver(struct qli_softc *);
-void		qli_write(struct qli_softc *, volatile u_int32_t *, u_int32_t);
-u_int32_t	qli_read(struct qli_softc *, volatile u_int32_t *);
-void		qli_hw_reset(struct qli_softc *);
-int		qli_soft_reset(struct qli_softc *);
-int		qli_get_fw_state(struct qli_softc *, u_int32_t *);
-int		qli_start_firmware(struct qli_softc *);
-int		qli_mgmt(struct qli_softc *, int, u_int32_t *);
-int		qli_intr(void *);
-int		qli_attach(struct qli_softc *);
-#ifndef SMALL_KERNEL
-int		qli_create_sensors(struct qli_softc *);
-#endif /* SMALL_KERNEL */
-
-struct scsi_adapter qli_switch = {
-	qli_scsi_cmd, qliminphys, 0, 0, qli_scsi_ioctl
-};
-
-struct cfdriver qli_cd = {
-	NULL, "qli", DV_DULL
-};
-
-struct cfattach qli_pci_ca = {
-	sizeof(struct qli_softc), qli_pci_match, qli_pci_attach
-};
-
-struct	qli_pci_device {
-	pcireg_t	qpd_vendor;
-	pcireg_t	qpd_product;
-	pcireg_t	qpd_subvendor;
-	pcireg_t	qpd_subproduct;
-	char		*qpd_model;
-	uint32_t	qpd_flags;
-} qli_pci_devices[] = {
-	{ PCI_VENDOR_QLOGIC,	PCI_PRODUCT_QLOGIC_ISP4022_HBA,
-	  0,			0,		"",			0 },
-	{ PCI_VENDOR_QLOGIC,	PCI_PRODUCT_QLOGIC_ISP4010_HBA,
-	  0,			0,		"",			0 },
-	{ 0 }
-};
-
-int
-qli_pci_find_device(void *aux) {
-	struct pci_attach_args	*pa = aux;
-	int			i;
-
-	for (i = 0; qli_pci_devices[i].qpd_vendor; i++) {
-		if (qli_pci_devices[i].qpd_vendor == PCI_VENDOR(pa->pa_id) &&
-		    qli_pci_devices[i].qpd_product == PCI_PRODUCT(pa->pa_id)) {
-			DNPRINTF(QLI_D_MISC, "qli_pci_find_device: %i\n", i);
-			return (i);
-		}
-	}
-
-	return (-1);
-}
-
-int
-qli_pci_match(struct device *parent, void *match, void *aux)
-{
-	int			i;
-
-	if ((i = qli_pci_find_device(aux)) != -1) {
-		DNPRINTF(QLI_D_MISC,
-		    "qli_pci_match: vendor: %04x  product: %04x\n",
-		    qli_pci_devices[i].qpd_vendor,
-		    qli_pci_devices[i].qpd_product);
-
-		return (1);
-	}
-	return (0);
-}
-
-void
-qli_pci_attach(struct device *parent, struct device *self, void *aux)
-{
-	struct qli_softc	*sc = (struct qli_softc *)self;
-	struct pci_attach_args	*pa = aux;
-	const char		*intrstr;
-	pci_intr_handle_t	ih;
-	pcireg_t		memtype;
-	int			r;
-
-	/* find the appropriate memory base */
-	for (r = PCI_MAPREG_START; r < PCI_MAPREG_END; r += sizeof(memtype)) {
-		memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, r);
-		if ((memtype & PCI_MAPREG_TYPE_MASK) == PCI_MAPREG_TYPE_MEM)
-			break;
-	}
-	if (r >= PCI_MAPREG_END) {
-		printf(": unable to locate system interface registers\n");
-		return;
-	}
-	if (pci_mapreg_map(pa, r, memtype, BUS_SPACE_MAP_LINEAR, &sc->sc_memt,
-	    &sc->sc_memh, NULL, &sc->sc_memsize, 0)) {
-		printf(": can't map controller pci space\n");
-		return;
-	}
-	sc->sc_dmat = pa->pa_dmat;
-
-	/* establish interrupt */
-	if (pci_intr_map(pa, &ih)) {
-		printf(": can't map interrupt\n");
-		goto unmap;
-	}
-	intrstr = pci_intr_string(pa->pa_pc, ih);
-	sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO, qli_intr, sc,
-	    DEVNAME(sc));
-	if (!sc->sc_ih) {
-		printf(": can't establish interrupt");
-		if (intrstr)
-			printf(" at %s", intrstr);
-		printf("\n");
-		goto unmap;
-	}
-
-	/* retrieve kva for register access */
-	sc->sc_reg = bus_space_vaddr(sc->sc_memt, sc->sc_memh);
-	if (sc->sc_reg == NULL) {
-		printf(": can't map registers into kernel\n");
-		goto intrdis;
-	}
-	printf(": %s\n", intrstr);
-
-	sc->sc_ql4010 =
-	    PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_QLOGIC_ISP4010_HBA;
-
-	if (qli_attach(sc)) {
-		printf("%s: can't attach\n", DEVNAME(sc));
-		goto intrdis;
-	}
-
-	return;
-intrdis:
-	pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
-unmap:
-	sc->sc_ih = NULL;
-	bus_space_unmap(sc->sc_memt, sc->sc_memh, sc->sc_memsize);
-}
-
-struct qli_mem *
-qli_allocmem(struct qli_softc *sc, size_t size)
-{
-	struct qli_mem		*mm;
-	int			nsegs;
-
-	DNPRINTF(QLI_D_MEM, "%s: qli_allocmem: %d\n", DEVNAME(sc),
-	    size);
-
-	mm = malloc(sizeof(*mm), M_DEVBUF, M_NOWAIT | M_ZERO);
-	if (mm == NULL)
-		return (NULL);
-
-	mm->am_size = size;
-
-	if (bus_dmamap_create(sc->sc_dmat, size, 1, size, 0,
-	    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &mm->am_map) != 0)
-		goto amfree;
-
-	if (bus_dmamem_alloc(sc->sc_dmat, size, PAGE_SIZE, 0, &mm->am_seg, 1,
-	    &nsegs, BUS_DMA_NOWAIT | BUS_DMA_ZERO) != 0)
-		goto destroy;
-
-	if (bus_dmamem_map(sc->sc_dmat, &mm->am_seg, nsegs, size, &mm->am_kva,
-	    BUS_DMA_NOWAIT) != 0)
-		goto free;
-
-	if (bus_dmamap_load(sc->sc_dmat, mm->am_map, mm->am_kva, size, NULL,
-	    BUS_DMA_NOWAIT) != 0)
-		goto unmap;
-
-	DNPRINTF(QLI_D_MEM, "  kva: %p  dva: %p  map: %p\n",
-	    mm->am_kva, mm->am_map->dm_segs[0].ds_addr, mm->am_map);
-
-	return (mm);
-
-unmap:
-	bus_dmamem_unmap(sc->sc_dmat, mm->am_kva, size);
-free:
-	bus_dmamem_free(sc->sc_dmat, &mm->am_seg, 1);
-destroy:
-	bus_dmamap_destroy(sc->sc_dmat, mm->am_map);
-amfree:
-	free(mm, M_DEVBUF);
-
-	return (NULL);
-}
-
-void
-qli_freemem(struct qli_softc *sc, struct qli_mem *mm)
-{
-	DNPRINTF(QLI_D_MEM, "%s: qli_freemem: %p\n", DEVNAME(sc), mm);
-
-	bus_dmamap_unload(sc->sc_dmat, mm->am_map);
-	bus_dmamem_unmap(sc->sc_dmat, mm->am_kva, mm->am_size);
-	bus_dmamem_free(sc->sc_dmat, &mm->am_seg, 1);
-	bus_dmamap_destroy(sc->sc_dmat, mm->am_map);
-	free(mm, M_DEVBUF);
-}
-
-void
-qliminphys(struct buf *bp, struct scsi_link *sl)
-{
-	DNPRINTF(QLI_D_MISC, "qliminphys: %d\n", bp->b_bcount);
-
-	if (bp->b_bcount > QLI_MAXFER)
-		bp->b_bcount = QLI_MAXFER;
-	minphys(bp);
-}
-
-void
-qli_disable_interrupts(struct qli_softc *sc)
-{
-	DNPRINTF(QLI_D_INTR, "%s: qli_disable_interrupts\n", DEVNAME(sc));
-
-	if (sc->sc_ql4010)
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-		    QLI_CLR_MASK(QLI_REG_CTRLSTAT_SCSI_INTR_ENABLE));
-	else
-		qli_write(sc, &sc->sc_reg->u1.isp4022.q22_intr_mask,
-		    QLI_CLR_MASK(QLI_REG_CTRLSTAT_SCSI_INTR_ENABLE_4022));
-}
-
-void
-qli_enable_interrupts(struct qli_softc *sc)
-{
-	DNPRINTF(QLI_D_INTR, "%s: qli_enable_interrupts\n", DEVNAME(sc));
-
-	if (sc->sc_ql4010)
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-		    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_INTR_ENABLE));
-	else
-		qli_write(sc, &sc->sc_reg->u1.isp4022.q22_intr_mask,
-		    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_INTR_ENABLE_4022));
-}
-
-void
-qli_write(struct qli_softc *sc, volatile u_int32_t *p, u_int32_t v)
-{
-	DNPRINTF(QLI_D_RW, "%s: qw 0x%x 0x%08x\n", DEVNAME(sc),
-	    (u_int8_t *)p - (u_int8_t *)sc->sc_reg, v);
-
-	*p = letoh32(v);
-	bus_space_barrier(sc->sc_memt, sc->sc_memh,
-	    (u_int8_t *)p - (u_int8_t *)sc->sc_reg, 4, BUS_SPACE_BARRIER_WRITE);
-}
-
-u_int32_t
-qli_read(struct qli_softc *sc, volatile u_int32_t *p)
-{
-	u_int32_t		v;
-
-	bus_space_barrier(sc->sc_memt, sc->sc_memh,
-	    (u_int8_t *)p - (u_int8_t *)sc->sc_reg, 4, BUS_SPACE_BARRIER_READ);
-	v = letoh32(*p);
-
-	DNPRINTF(QLI_D_RW, "%s: qr 0x%x 0x%08x\n", DEVNAME(sc),
-	    (u_int8_t *)p - (u_int8_t *)sc->sc_reg, v);
-	return (v);
-}
-
-void
-qli_hw_reset(struct qli_softc *sc)
-{
-	u_int32_t		s;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_hw_reset\n", DEVNAME(sc));
-
-	/* clear scsi reset interrupt bit or soft reset won't work */
-	s = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-	if (s & QLI_REG_CTRLSTAT_SCSI_RESET_INTR)
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status, QLI_SET_MASK(s));
-
-	/* issue soft reset */
-	qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-	    QLI_SET_MASK(QLI_REG_CTRLSTAT_SOFT_RESET));
-}
-
-int
-qli_soft_reset(struct qli_softc *sc)
-{
-	int			rv = 1, i, failed;
-	u_int32_t		s;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_soft_reset\n", DEVNAME(sc));
-
-	qli_hw_reset(sc);
-
-	/* wait until net reset bit is cleared */
-	for (i = 0; i < QLI_SOFT_RESET_RETRIES; i++) {
-		s = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-		if ((s & QLI_REG_CTRLSTAT_NET_RESET_INTR) == 0)
-			break;
-		delay(1000000); /* 1s */
-	}
-	s = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-	if (s & QLI_REG_CTRLSTAT_NET_RESET_INTR) {
-		printf("%s: qli_soft_reset: net reset intr bit not cleared\n",
-		    DEVNAME(sc));
-		/* XXX set the same bit per the linux driver */
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-		    QLI_SET_MASK(QLI_REG_CTRLSTAT_NET_RESET_INTR));
-	}
-
-	/* wait for soft reset to complete */
-	for (i = 0, failed = 1; i < QLI_SOFT_RESET_RETRIES; i++) {
-		s = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-		if ((s & QLI_REG_CTRLSTAT_SOFT_RESET) == 0) {
-			failed = 0;
-			break;
-		}
-		delay(1000000); /* 1s */
-	}
-
-	/* check if scsi reset interrupt is cleared */
-	s = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-	if (s & QLI_REG_CTRLSTAT_SCSI_RESET_INTR) {
-		printf("%s: qli_soft_reset: scsi reset intr bit not cleared\n",
-		    DEVNAME(sc));
-		/* XXX set the same bit per the linux driver */
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-		    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_RESET_INTR));
-	}
-
-	if (failed) {
-		/* force the soft reset */
-		printf("%s: qli_soft_reset: soft reset failed\n", DEVNAME(sc));
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-		    QLI_SET_MASK(QLI_REG_CTRLSTAT_FORCE_SOFT_RESET));
-		for (i = 0; i < QLI_SOFT_RESET_RETRIES; i++) {
-			s = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-			if ((s & QLI_REG_CTRLSTAT_FORCE_SOFT_RESET) == 0) {
-				rv = 0;
-				break;
-			}
-			delay(1000000); /* 1s */
-		}
-	} else
-		rv = 0;
-
-	return (rv);
-}
-
-int
-qli_get_fw_state(struct qli_softc *sc, u_int32_t *mbox)
-{
-	int			rv = 1;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_get_fw_state\n", DEVNAME(sc));
-
-	mbox[0] = QLI_MBOX_OPC_GET_FW_STATE;
-	if (qli_mgmt(sc, 1, mbox))
-		goto done;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_get_fw_state: state: 0x%08x\n",
-	    DEVNAME(sc), mbox[1]);
-	rv = 0;
-done:
-	return (rv);
-}
-
-int
-qli_lock_driver(struct qli_softc *sc)
-{
-	int			i, rv = 1;
-
-	DNPRINTF(QLI_D_SEM, "%s: qli_lock_driver\n", DEVNAME(sc));
-
-	for (i = 0; i < QLI_SEM_MAX_RETRIES; i++) {
-		if (qli_lock_sem(sc, QLI_SEM_DRIVER(sc),
-		    QLI_SEM_DRIVER_MASK(sc))) {
-			DNPRINTF(QLI_D_SEM, "%s: qli_lock_driver: semaphore"
-			    " not acquired, retry %d\n", DEVNAME(sc), i);
-			if (cold)
-				delay(1000000); /* 1s */
-			else
-				while (tsleep(sc, PRIBIO + 1, "qlisem", hz) !=
-				    EWOULDBLOCK)
-					;
-		} else {
-			DNPRINTF(QLI_D_SEM, "%s: qli_lock_driver: semaphore"
-			    " acquired\n", DEVNAME(sc));
-			rv = 0;
-			break;
-		}
-	}
-	return (rv);
-}
-
-void
-qli_unlock_sem(struct qli_softc *sc, u_int32_t mask)
-{
-	DNPRINTF(QLI_D_SEM, "%s: qli_unlock_sem: 0x%08x released\n",
-	    DEVNAME(sc), mask);
-
-	qli_write(sc, QLI_SEMAPHORE(sc), mask);
-}
-
-int
-qli_lock_sem(struct qli_softc *sc, u_int32_t shift, u_int32_t mask)
-{
-	int			rv = 1;
-	u_int32_t		v, s;
-
-	s = sc->sc_resource << shift;
-	qli_write(sc, QLI_SEMAPHORE(sc), s | mask);
-	v = qli_read(sc, QLI_SEMAPHORE(sc));
-
-	if ((v & (mask >> 16)) == s)
-		rv = 0;
-
-	DNPRINTF(QLI_D_SEM, "%s: qli_lock_sem: mask: 0x%08x shift: 0x%08x "
-	    "s: 0x%08x v: 0x%08x did %sacquire semaphore \n", DEVNAME(sc),
-	    mask, shift, s, v, rv ? "not " : "");
-
-	return (rv);
-}
-
-void
-qli_eeprom_out(struct qli_softc *sc, u_int32_t data)
-{
-	qli_write(sc, QLI_NVRAM(sc), data);
-	delay(1);
-}
-
-u_int16_t
-qli_read_nvram(struct qli_softc *sc, u_int32_t offset)
-{
-	int			i;
-	u_int32_t		s, mask, data;
-	u_int16_t		val = 0;
-#ifdef QLI_DEBUG
-	u_int32_t		qli_debug_save = qli_debug;
-
-	qli_debug = 0;
-#endif /* QLI_DEBUG */
-
-	/* select chip */
-	s = QLI_NVRAM_MASK | QLI_NVRAM_SELECT;
-	qli_eeprom_out(sc, s);
-
-	/* start bit */
-	qli_eeprom_out(sc, s | QLI_NVRAM_DATA_OUT);
-	qli_eeprom_out(sc, s | QLI_NVRAM_DATA_OUT | QLI_NVRAM_CLOCK);
-	qli_eeprom_out(sc, s | QLI_NVRAM_DATA_OUT); /* clock low */
-
-	/* send read command */
-	mask = 1 << (QLI_NVRAM_NUM_CMD_BITS - 1);
-	for (i = 0; i < QLI_NVRAM_NUM_CMD_BITS; i++) {
-		data = ((QLI_NVRAM_CMD_READ << i) & mask) ?
-		    QLI_NVRAM_DATA_OUT : 0;
-
-		qli_eeprom_out(sc, s | data);
-		qli_eeprom_out(sc, s | data | QLI_NVRAM_CLOCK);
-		qli_eeprom_out(sc, s | data);
-	}
-
-	/* send read address */
-	mask = 1 << (QLI_NVRAM_NUM_ADDR_BITS(sc) - 1);
-	for (i = 0; i < QLI_NVRAM_NUM_ADDR_BITS(sc); i++) {
-		data = ((offset << i) & mask) ? QLI_NVRAM_DATA_OUT : 0;
-		qli_eeprom_out(sc, s | data);
-		qli_eeprom_out(sc, s | data | QLI_NVRAM_CLOCK);
-		qli_eeprom_out(sc, s | data);
-	}
-
-	/* read data */
-	for (i = 0; i < QLI_NVRAM_NUM_DATA_BITS; i++) {
-		qli_eeprom_out(sc, s | QLI_NVRAM_CLOCK);
-		qli_eeprom_out(sc, s);
-		data = (qli_read(sc, QLI_NVRAM(sc)) & QLI_NVRAM_DATA_IN) ?
-		    1 : 0;
-		val = (val << 1) | data;
-	}
-
-	/* deselect chip */
-	s = QLI_NVRAM_MASK;
-	qli_write(sc, QLI_NVRAM(sc), s);
-
-#ifdef QLI_DEBUG
-	qli_debug = qli_debug_save;
-#endif /* QLI_DEBUG */
-
-	DNPRINTF(QLI_D_RW, "%s: qli_read_nvram 0x%x 0x%04x\n", DEVNAME(sc),
-	    offset, letoh16(val));
-
-	return (letoh16(val));
-}
-
-int
-qli_validate_nvram(struct qli_softc *sc)
-{
-	int			i, rv = 1;
-	u_int16_t		nvram_checksum = 0;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_validate_nvram\n", DEVNAME(sc));
-
-	for (i = 0; i < QLI_NVRAM_SIZE(sc); i++)
-		nvram_checksum += qli_read_nvram(sc, i);
-
-	DNPRINTF(QLI_D_MISC, "%s: nvram checksum 0x%04x\n", DEVNAME(sc),
-	    nvram_checksum);
-
-	if (nvram_checksum == 0)
-		rv = 0;
-
-	return (rv);
-}
-
-int
-qli_start_firmware(struct qli_softc *sc) {
-	int			rv = 1, reset_required = 1, config_required = 0;
-	int			boot_required = 0, i;
-	u_int32_t		mbox[QLI_MBOX_SIZE], r;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware\n", DEVNAME(sc));
-
-	if (qli_lock_driver(sc)) {
-		printf("%s: could not acquire global driver semaphore, "
-		    "aborting firmware bring-up\n", DEVNAME(sc));
-		goto done;
-	}
-
-	if (qli_read(sc, QLI_PORT_CTRL(sc)) & QLI_PORT_CTRL_INITIALIZED) {
-		/* Hardware has been initialized */
-		DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: hardware has "
-		    "been initialized\n", DEVNAME(sc));
-
-		if (qli_read(sc, &sc->sc_reg->qlr_mbox[0]) == 0) {
-			/* firmware is not running */
-			DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: fw "
-			    "not running\n", DEVNAME(sc));
-			reset_required = 0;
-			config_required = 1;
-		} else {
-			qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-			    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_RESET_INTR));
-
-			/* issue command to fw to find out if we are up */
-			bzero(mbox, sizeof(mbox));
-			if (qli_get_fw_state(sc, mbox)) {
-				/* command failed, reset chip */
-				DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: "
-				    "firmware in unknown state, reseting "
-				    "chip\n", DEVNAME(sc));
-			} else {
-				if (mbox[1] & QLI_MBOX_STATE_CONFIG_WAIT) {
-					config_required = 1;
-					reset_required = 0;
-				}
-			}
-		}
-	}
-
-	if (reset_required) {
-		if (qli_soft_reset(sc)) {
-			printf("%s: soft reset failed, aborting firmware "
-			    "bring-up\n", DEVNAME(sc));
-			goto done;
-		}
-		config_required = 1;
-
-		if (qli_lock_driver(sc)) {
-			printf("%s: could not acquire global driver semaphore "
-			    "after reseting chip, aborting firmware bring-up\n",
-			    DEVNAME(sc));
-			goto done;
-		}
-	}
-
-	if (config_required) {
-		DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: configuring "
-		    "firmware\n", DEVNAME(sc));
-
-		if (qli_lock_sem(sc, QLI_SEM_FLASH(sc),
-		    QLI_SEM_FLASH_MASK(sc))) {
-			printf("%s: could not lock flash during firmware "
-			    "bring-up\n", DEVNAME(sc));
-			goto unlock_driver;
-		}
-
-		if (qli_lock_sem(sc, QLI_SEM_NVRAM(sc),
-		    QLI_SEM_NVRAM_MASK(sc))) {
-			printf("%s: could not lock nvram during firmware "
-			    "bring-up\n", DEVNAME(sc));
-			qli_unlock_sem(sc, QLI_SEM_FLASH_MASK(sc));
-			goto unlock_driver;
-		}
-
-		if (qli_validate_nvram(sc)) {
-			printf("%s: invalid NVRAM checksum.  Flash your "
-			    "controller", DEVNAME(sc));
-
-			if (sc->sc_ql4010)
-				r = QLI_EXT_HW_CFG_DEFAULT_QL4010;
-			else
-				r = QLI_EXT_HW_CFG_DEFAULT_QL4022;
-		} else
-			r = (u_int32_t)qli_read_nvram(sc,
-			    QLI_NVRAM_EXT_HW_CFG(sc));
-
-		/* upper 16 bits are write mask; enable everything */
-		qli_write(sc, QLI_EXT_HW_CFG(sc), (0xffff << 16 ) | r);
-
-		qli_unlock_sem(sc, QLI_SEM_NVRAM_MASK(sc));
-		qli_unlock_sem(sc, QLI_SEM_FLASH_MASK(sc));
-
-		boot_required = 1;
-	}
-
-	if (boot_required) {
-		/* boot firmware */
-		DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: booting "
-		    "firmware\n", DEVNAME(sc));
-
-		/* stuff random value in mbox[7] to randomize source ports */
-		/* XXX use random ne instead of 1234  */
-		qli_write(sc, &sc->sc_reg->qlr_mbox[7], 1234);
-
-		/* XXX linux driver sets ACB v2 into mbox[6] */
-
-		qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-			QLI_SET_MASK(QLI_REG_CTRLSTAT_BOOT_ENABLE));
-
-		/* wait for firmware to come up */
-		for (i = 0; i < 60 * 4 /* up to 60 seconds */; i ++) {
-			if (qli_read(sc, &sc->sc_reg->qlr_ctrl_status) &
-			    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_PROC_INTR))
-				break;
-			if (qli_read(sc, &sc->sc_reg->qlr_mbox[0]) ==
-			    QLI_MBOX_STATUS_COMMAND_COMPLETE)
-				break;
-			DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: waiting "
-			    "for firmware, retry = %d\n", DEVNAME(sc), i);
-
-			delay(250000); /* 250ms */
-		}
-		if (qli_read(sc, &sc->sc_reg->qlr_mbox[0]) ==
-		    QLI_MBOX_STATUS_COMMAND_COMPLETE) {
-			/* firmware is done booting */
-			qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-			    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_PROC_INTR));
-
-			DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: firmware "
-			    "booting complete\n", DEVNAME(sc));
-
-			rv = 0;
-		}
-		else {
-			DNPRINTF(QLI_D_MISC, "%s: qli_start_firmware: firmware "
-			    "booting failed\n", DEVNAME(sc));
-			rv = 1;
-		}
-	}
-
-unlock_driver:
-	qli_unlock_sem(sc, QLI_SEM_DRIVER_MASK(sc));
-done:
-	return (rv);
-}
-
-int
-qli_mgmt(struct qli_softc *sc, int len, u_int32_t *mbox)
-{
-	int			rv = 1, s, i;
-	u_int32_t		x;
-
-	DNPRINTF(QLI_D_MBOX, "%s: qli_mgmt: cold: %d\n", DEVNAME(sc), cold);
-
-	if (!mbox)
-		goto done;
-
-	s = splbio();
-	rw_enter_write(&sc->sc_mbox_lock);
-
-	if (qli_read(sc, &sc->sc_reg->qlr_ctrl_status) &
-	    QLI_REG_CTRLSTAT_SCSI_PROC_INTR) {
-		/* this should not happen */
-		printf("%s: qli_mgmt called while interrupt is pending\n",
-		    DEVNAME(sc));
-		qli_intr(sc);
-	}
-
-	qli_dump_mbox(sc, mbox);
-
-	/* mbox[0] needs to be written last so write backwards */
-	for (i = QLI_MBOX_SIZE - 1; i >= 0; i--)
-		qli_write(sc, &sc->sc_reg->qlr_mbox[i], i < len ? mbox[i] : 0);
-
-	/* notify chip it has to deal with mailbox */
-	qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-	    QLI_SET_MASK(QLI_REG_CTRLSTAT_EP_INTR));
-
-	/* wait for completion */
-	if (cold) {
-		sc->sc_mbox_flags = QLI_MBOX_F_POLL;
-		for (i = 0; i < 6000000 /* up to a minute */; i++) {
-			delay(10);
-			if ((qli_read(sc, &sc->sc_reg->qlr_ctrl_status) &
-			    (QLI_REG_CTRLSTAT_SCSI_RESET_INTR |
-			    QLI_REG_CTRLSTAT_SCSI_COMPL_INTR |
-			    QLI_REG_CTRLSTAT_SCSI_PROC_INTR))) {
-				qli_intr(sc);
-				break;
-			}
-		}
-	} else {
-		sc->sc_mbox_flags = QLI_MBOX_F_PENDING;
-		while ((sc->sc_mbox_flags & QLI_MBOX_F_WAKEUP) == 0)
-			tsleep(sc->sc_mbox, PRIBIO, "qli_mgmt", 0);
-	}
-
-	x = sc->sc_mbox[0];
-	switch (x) {
-	case QLI_MBOX_STATUS_COMMAND_COMPLETE:
-		for (i = 0; i < QLI_MBOX_SIZE; i++)
-			mbox[i] = sc->sc_mbox[i];
-		sc->sc_mbox_flags = QLI_MBOX_F_INVALID;
-		rv = 0;
-
-		qli_dump_mbox(sc, mbox);
-		break;
-	default:
-		printf("%s: qli_mgmt: mailbox failed opcode 0x%08x failed "
-		    "with error code 0x%08x\n", DEVNAME(sc), mbox[0], x);
-	}
-
-	rw_exit_write(&sc->sc_mbox_lock);
-	splx(s);
-done:
-	return (rv);
-}
-
-int
-qli_attach(struct qli_softc *sc)
-{
-	/* struct scsibus_attach_args saa; */
-	int			rv = 1;
-	u_int32_t		f, mbox[QLI_MBOX_SIZE];
-	unsigned int		align;
-
-	DNPRINTF(QLI_D_MISC, "%s: qli_attach\n", DEVNAME(sc));
-
-	rw_init(&sc->sc_lock, "qli_lock");
-	rw_init(&sc->sc_mbox_lock, "qli_mbox_lock");
-
-	if (sc->sc_ql4010)
-		sc->sc_resource = QLI_SEM_4010_SCSI;
-	else {
-		f = qli_read(sc, &sc->sc_reg->qlr_ctrl_status) &
-		    QLI_REG_CTRLSTAT_FUNC_MASK;
-		sc->sc_resource = f >> 8;
-	}
-	DNPRINTF(QLI_D_MISC, "%s: qli_attach resource: %d\n", DEVNAME(sc),
-	    sc->sc_resource);
-
-	if (qli_start_firmware(sc)) {
-		printf("%s: could not start firmware\n", DEVNAME(sc));
-		goto done;
-	}
-
-	bzero(mbox, sizeof(mbox));
-	mbox[0] = QLI_MBOX_OPC_ABOUT_FIRMWARE;
-	if (qli_mgmt(sc, 4, mbox)) {
-		printf("%s: about firmware command failed\n", DEVNAME(sc));
-		goto done;
-	}
-	printf("%s: version %d.%d.%d.%d\n", DEVNAME(sc), mbox[1], mbox[2],
-	    mbox[3], mbox[4]);
-
-	/* get state */
-	bzero(mbox, sizeof(mbox));
-	if (qli_get_fw_state(sc, mbox)) {
-		printf("%s: get firmware state command failed\n", DEVNAME(sc));
-		goto done;
-	}
-
-	/* initialize firmware */
-	sc->sc_fw_cb = qli_allocmem(sc, QLI_FW_CTRL_BLK_SIZE);
-	if (sc->sc_fw_cb == NULL) {
-		printf("%s: unable to allocate firmware control block memory\n",
-		    DEVNAME(sc));
-		goto done;
-	}
-	bzero(mbox, sizeof(mbox));
-	mbox[0] = QLI_MBOX_OPC_GET_INITIAL_FW_CB;
-	mbox[2] = (u_int32_t)QLIMEM_DVA(sc->sc_fw_cb);
-	mbox[3] = (u_int32_t)((u_int64_t)QLIMEM_DVA(sc->sc_fw_cb) >> 32);
-	if (qli_mgmt(sc, 4, mbox)) {
-		printf("%s: get initial firmware control block failed\n",
-		    DEVNAME(sc));
-		goto nofwcb;
-	}
-
-	/* setup queues & shadow registers */
-	sc->sc_queues_len = (QLI_REQUESTQ_DEPTH * QLI_QUEUE_SIZE) +
-	    (QLI_RESPONSEQ_DEPTH * QLI_QUEUE_SIZE) +
-	    sizeof(struct qli_shadow_regs) +
-	    QLIMEM_ALIGN + PAGE_SIZE - 1;
-	sc->sc_queues_len &= ~(PAGE_SIZE - 1);
-
-	sc->sc_queues = qli_allocmem(sc, sc->sc_queues_len);
-	if (sc->sc_queues == NULL) {
-		printf("%s: unable to allocate firmware control block memory\n",
-		    DEVNAME(sc));
-		goto nofwcb;
-	}
-
-	if (QLIMEM_DVA(sc->sc_queues) & (QLIMEM_ALIGN - 1))
-		align = QLIMEM_ALIGN -
-		    (QLIMEM_DVA(sc->sc_queues) & (QLIMEM_ALIGN - 1));
-	else
-		align = 0;
-
-	sc->sc_request_dva = QLIMEM_DVA(sc->sc_queues) + align;
-	sc->sc_request_ring = QLIMEM_KVA(sc->sc_queues) + align;
-
-#if 0
-	/* enable interrupts */
-	qli_enable_interrupts(sc);
-#endif
-
-#if NBIO > 0
-	if (bio_register(&sc->sc_dev, qli_ioctl) != 0)
-		panic("%s: controller registration failed", DEVNAME(sc));
-	else
-		sc->sc_ioctl = qli_ioctl;
-
-#ifndef SMALL_KERNEL
-	if (qli_create_sensors(sc) != 0)
-		printf("%s: unable to create sensors\n", DEVNAME(sc));
-#endif /* SMALL_KERNEL */
-#endif /* NBIO > 0 */
-
-done:
-	return (rv);
-/* noqueues: */
-	qli_freemem(sc, sc->sc_queues);
-nofwcb:
-	qli_freemem(sc, sc->sc_fw_cb);
-	return (rv);
-}
-
-void
-qli_scsi_cmd(struct scsi_xfer *xs)
-{
-	int s;
-#ifdef QLI_DEBUG
-	struct scsi_link	*link = xs->sc_link;
-	struct qli_softc	*sc = link->adapter_softc;
-
-	DNPRINTF(QLI_D_CMD, "%s: qli_scsi_cmd opcode: %#x\n",
-	    DEVNAME(sc), xs->cmd->opcode);
-#endif
-
-	goto stuffup;
-	return;
-
-stuffup:
-	xs->error = XS_DRIVER_STUFFUP;
-	scsi_done(xs);
-}
-
-int
-qli_intr(void *arg)
-{
-	struct qli_softc	*sc = arg;
-	int			claimed = 0, i;
-	u_int32_t		intr, mbox_status;
-
-	intr = qli_read(sc, &sc->sc_reg->qlr_ctrl_status);
-	if ((intr & (QLI_REG_CTRLSTAT_SCSI_RESET_INTR |
-	    QLI_REG_CTRLSTAT_SCSI_COMPL_INTR |
-	    QLI_REG_CTRLSTAT_SCSI_PROC_INTR |
-	    QLI_REG_CTRLSTAT_FATAL_ERROR)) == 0)
-		goto done;
-
-	DNPRINTF(QLI_D_INTR, "%s: qli_intr %#x cs: 0x%08x\n", DEVNAME(sc), sc,
-	    intr);
-
-	if (intr & QLI_REG_CTRLSTAT_SCSI_RESET_INTR) {
-		/* chip requests soft reset */
-		/* XXX */
-		panic("%s: qli_intr chip reset not implemented", DEVNAME(sc));
-	}
-
-	if (intr & QLI_REG_CTRLSTAT_FATAL_ERROR) {
-		/* reset firmware */
-		/* XXX */
-		panic("%s: qli_intr chip hang recovery not implemented",
-		    DEVNAME(sc));
-	}
-
-	if (intr & QLI_REG_CTRLSTAT_SCSI_COMPL_INTR) {
-		/* io completion */
-		/* XXX */
-		panic("%s: qli_intr io completion not implemented",
-		    DEVNAME(sc));
-	}
-
-	if (intr & QLI_REG_CTRLSTAT_SCSI_PROC_INTR) {
-		/* mailbox completion */
-		mbox_status = qli_read(sc, &sc->sc_reg->qlr_mbox[0]);
-		switch (mbox_status >> QLI_MBOX_TYPE_SHIFT) {
-		case QLI_MBOX_COMPLETION_STATUS:
-			for (i = 0; i < QLI_MBOX_SIZE; i++)
-				sc->sc_mbox[i] = qli_read(sc,
-				    &sc->sc_reg->qlr_mbox[i]);
-			qli_write(sc, &sc->sc_reg->qlr_ctrl_status,
-			    QLI_SET_MASK(QLI_REG_CTRLSTAT_SCSI_PROC_INTR));
-			if (sc->sc_mbox_flags & QLI_MBOX_F_PENDING) {
-				sc->sc_mbox_flags |= QLI_MBOX_F_WAKEUP;
-				wakeup(sc->sc_mbox);
-			}
-			claimed = 1;
-			break;
-		case QLI_MBOX_ASYNC_EVENT_STATUS:
-			printf("%s: unhandled async event 0x%08x\n",
-			    DEVNAME(sc),
-			    qli_read(sc, &sc->sc_reg->qlr_mbox[0]));
-			break;
-		default:
-			printf("%s: invalid mailbox return 0x%08x\n",
-			    DEVNAME(sc),
-			    qli_read(sc, &sc->sc_reg->qlr_mbox[0]));
-			break;
-		}
-	}
-
-done:
-	return (claimed);
-}
-
-int
-qli_scsi_ioctl(struct scsi_link *link, u_long cmd, caddr_t addr, int flag,
-    struct proc *p)
-{
-	struct qli_softc	*sc = (struct qli_softc *)link->adapter_softc;
-
-	DNPRINTF(QLI_D_IOCTL, "%s: qli_scsi_ioctl\n", DEVNAME(sc));
-
-	if (sc->sc_ioctl)
-		return (sc->sc_ioctl(link->adapter_softc, cmd, addr));
-	else
-		return (ENOTTY);
-}
-
-#if NBIO > 0
-int
-qli_ioctl(struct device *dev, u_long cmd, caddr_t addr)
-{
-	struct qli_softc	*sc = (struct qli_softc *)dev;
-	int			error = EINVAL;
-
-	DNPRINTF(QLI_D_IOCTL, "%s: qli_ioctl ", DEVNAME(sc));
-
-	rw_enter_write(&sc->sc_lock);
-
-	switch (cmd) {
-	case BIOCINQ:
-		DNPRINTF(QLI_D_IOCTL, "inq\n");
-		break;
-
-	case BIOCVOL:
-		DNPRINTF(QLI_D_IOCTL, "vol\n");
-		break;
-
-	case BIOCDISK:
-		DNPRINTF(QLI_D_IOCTL, "disk\n");
-		break;
-
-	case BIOCALARM:
-		DNPRINTF(QLI_D_IOCTL, "alarm\n");
-		break;
-
-	case BIOCBLINK:
-		DNPRINTF(QLI_D_IOCTL, "blink\n");
-		break;
-
-	case BIOCSETSTATE:
-		DNPRINTF(QLI_D_IOCTL, "setstate\n");
-		break;
-
-	default:
-		DNPRINTF(QLI_D_IOCTL, " invalid ioctl\n");
-		error = EINVAL;
-	}
-
-	rw_exit_write(&sc->sc_lock);
-
-	return (error);
-}
-#endif /* NBIO > 0 */
-
-#ifndef SMALL_KERNEL
-int
-qli_create_sensors(struct qli_softc *sc)
-{
-	return (1);
-}
-#endif /* SMALL_KERNEL */
-
-#ifdef QLI_DEBUG
-void
-qli_dump_mbox(struct qli_softc *sc, u_int32_t *mbox)
-{
-	int			i;
-
-	if ((qli_debug & QLI_D_MBOX) == 0)
-		return;
-
-	printf("%s: qli_dump_mbox: ", DEVNAME(sc));
-	for (i = 0; i < QLI_MBOX_SIZE; i++)
-		printf("mbox[%d] = 0x%08x ", i, mbox[i]);
-	printf("\n");
-}
-#endif /* QLI_DEBUG */
diff --git a/sys/dev/pci/qlireg.h b/sys/dev/pci/qlireg.h
deleted file mode 100644
index 29d7b0f7c9e..00000000000
--- a/sys/dev/pci/qlireg.h
+++ /dev/null
@@ -1,647 +0,0 @@
-/* $OpenBSD: qlireg.h,v 1.9 2010/10/27 20:48:27 deraadt Exp $ */
-/*
- * Copyright (c) 2007 Marco Peereboom <marco@peereboom.us>
- * Copyright (c) 2007 David Collins <dave@davec.name>
- *
- * Permission to use, copy, modify, and distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
- * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
- * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
- * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#define QLI_MAXFER				(MAXPHYS)
-#define QLI_SOFT_RESET_RETRIES			(3)
-
-struct qli_port_regs {
-	u_int32_t		qpr_ext_hw_conf;
-	u_int32_t		qpr_chip_config;
-	u_int32_t		qpr_port_ctrl;
-	u_int32_t		qpr_port_status;
-	u_int32_t		qpr_host_prim_mac_hi;
-	u_int32_t		qpr_host_prim_mac_lo;
-	u_int32_t		qpr_sec_host_mac_hi;
-	u_int32_t		qpr_sec_host_mac_lo;
-	u_int32_t		qpr_ep_prim_mac_hi;
-	u_int32_t		qpr_ep_prim_mac_lo;
-	u_int32_t		qpr_ep_sec_mac_hi;
-	u_int32_t		qpr_ep_sec_mac_lo;
-	u_int32_t		qpr_host_prim_ip_hi;
-	u_int32_t		qpr_host_prim_ip_mid_hi;
-	u_int32_t		qpr_host_prim_ip_mid_lo;
-	u_int32_t		qpr_host_prim_ip_lo;
-	u_int32_t		qpr_host_sec_ip_hi;
-	u_int32_t		qpr_host_sec_ip_mid_hi;
-	u_int32_t		qpr_host_sec_ip_mid_lo;
-	u_int32_t		qpr_host_sec_ip_lo;
-	u_int32_t		qpr_ep_prim_ip_hi;
-	u_int32_t		qpr_epprimipmidhi;
-	u_int32_t		qpr_ep_prim_ip_mid_lo;
-	u_int32_t		qpr_ep_prim_ip_lo;
-	u_int32_t		qpr_eps_ec_ip_hi;
-	u_int32_t		qpr_ep_sec_ip_mid_hi;
-	u_int32_t		qpr_ep_sec_ip_mid_lo;
-	u_int32_t		qpr_ep_sec_ip_lo;
-	u_int32_t		qpr_ip_reassembly_timeout;
-	u_int32_t		qpr_eth_max_frame_payload;
-	u_int32_t		qpr_tcp_max_window_size;
-	u_int32_t		qpr_tcp_current_timestamp_hi;
-	u_int32_t		qpr_tcp_current_timestamp_lo;
-	u_int32_t		qpr_local_ram_address;
-	u_int32_t		qpr_local_ram_data;
-	u_int32_t		qpr_res1;
-	u_int32_t		qpr_gp_out;
-	u_int32_t		qpr_gp_in;
-	u_int32_t		qpr_probe_mux_addr;
-	u_int32_t		qpr_probe_mux_data;
-	u_int32_t		qpr_stats_index;
-	u_int32_t		qpr_stats_read_data_inc;
-	u_int32_t		qpr_stats_read_data_noinc;
-	u_int32_t		qpr_port_err_status;
-} __packed;
-
-struct qli_mem_regs {
-	u_int32_t		qmr_net_request_queue_out;
-	u_int32_t		qmr_net_request_queue_out_addr_hi;
-	u_int32_t		qmr_net_request_queue_out_addr_lo;
-	u_int32_t		qmr_net_request_queue_base_addr_hi;
-	u_int32_t		qmr_net_request_queue_base_addr_lo;
-	u_int32_t		qmr_net_request_queue_length;
-	u_int32_t		qmr_net_response_queue_in;
-	u_int32_t		qmr_net_response_queue_in_addr_hi;
-	u_int32_t		qmr_net_response_queue_in_addr_low;
-	u_int32_t		qmr_net_response_queue_base_addr_hi;
-	u_int32_t		qmr_net_response_queue_base_addr_lo;
-	u_int32_t		qmr_net_response_queue_length;
-	u_int32_t		qmr_req_q_out;
-	u_int32_t		qmr_request_queue_out_addr_hi;
-	u_int32_t		qmr_request_queue_out__addr_lo;
-	u_int32_t		qmr_request_queue_base_addr_hi;
-	u_int32_t		qmr_request_queue_base_addr_lo;
-	u_int32_t		qmr_request_queue_length;
-	u_int32_t		qmr_response_queue_in;
-	u_int32_t		qmr_response_queue_in_addr_hi;
-	u_int32_t		qmr_response_queue_in_addr_lo;
-	u_int32_t		qmr_response_queue_base_addr_hi;
-	u_int32_t		qmr_response_queue_base_addr_lo;
-	u_int32_t		qmr_response_queue_length;
-	u_int32_t		qmr_net_rx_large_buffer_queue_out;
-	u_int32_t		qmr_net_rx_large_buffer_queue_base_addr_hi;
-	u_int32_t		qmr_net_rx_large_buffer_queue_base_addr_lo;
-	u_int32_t		qmr_net_rx_large_buffer_queue_length;
-	u_int32_t		qmr_net_rx_large_buffer_length;
-	u_int32_t		qmr_net_rx_small_buffer_queue_out;
-	u_int32_t		qmr_net_rx_small_buffer_queue_base_addr_hi;
-	u_int32_t		qmr_net_rx_small_buffer_queue_base_addr_lo;
-	u_int32_t		qmr_net_rx_small_buffer_queue_length;
-	u_int32_t		qmr_net_rx_small_buffer_length;
-	u_int32_t		qmr_res[10];
-} __packed;
-
-struct qli_ram_regs {
-	u_int32_t		qrr_buflet_size;
-	u_int32_t		qrr_buflet_max_count;
-	u_int32_t		qrr_buflet_curr_count;
-	u_int32_t		qrr_buflet_pause_threshold_count;
-	u_int32_t		qrr_buflet_tcp_win_threshold_hi;
-	u_int32_t		qrr_buflet_tcp_win_threshold_lo;
-	u_int32_t		qrr_ip_hash_table_base_addr;
-	u_int32_t		qrr_ip_hash_table_size;
-	u_int32_t		qrr_tcp_hash_table_base_addr;
-	u_int32_t		qrr_tcp_hash_table_size;
-	u_int32_t		qrr_ncb_area_base_addr;
-	u_int32_t		qrr_ncb_max_count;
-	u_int32_t		qrr_ncb_curr_count;
-	u_int32_t		qrr_drb_area_base_addr;
-	u_int32_t		qrr_drb_max_count;
-	u_int32_t		qrr_drb_curr_count;
-	u_int32_t		qrr_res[28];
-} __packed;
-
-struct qli_stat_regs{
-	u_int32_t		qsr_mac_tx_frame_count;
-	u_int32_t		qsr_mac_tx_byte_count;
-	u_int32_t		qsr_mac_rx_frame_count;
-	u_int32_t		qsr_mac_rx_byte_count;
-	u_int32_t		qsr_mac_crc_err_count;
-	u_int32_t		qsr_mac_enc_err_count;
-	u_int32_t		qsr_mac_rx_length_err_count;
-	u_int32_t		qsr_ip_tx_packet_count;
-	u_int32_t		qsr_ip_tx_byte_count;
-	u_int32_t		qsr_ip_tx_fragment_count;
-	u_int32_t		qsr_ip_rx_packet_count;
-	u_int32_t		qsr_ip_rx_byte_count;
-	u_int32_t		qsr_ip_rx_fragment_count;
-	u_int32_t		qsr_ip_datagram_reassembly_count;
-	u_int32_t		qsr_ip_v6_rx_packet_count;
-	u_int32_t		qsr_ip_err_packet_count;
-	u_int32_t		qsr_ip_reassembly_err_count;
-	u_int32_t		qsr_tcp_tx_segment_count;
-	u_int32_t		qsr_tcp_tx_byte_count;
-	u_int32_t		qsr_tcp_rx_segment_count;
-	u_int32_t		qsr_tcp_rx_byte_count;
-	u_int32_t		qsr_tcp_timer_exp_count;
-	u_int32_t		qsr_tcp_rx_ack_count;
-	u_int32_t		qsr_tcp_tx_ack_count;
-	u_int32_t		qsr_tcp_rx_errOOO_count;
-	u_int32_t		qsr_res0;
-	u_int32_t		qsr_tcp_rx_window_probe_update_count;
-	u_int32_t		qsr_ecc_err_correction_count;
-	u_int32_t		qsr_res1[16];
-} __packed;
-
-#define QLI_MBOX_SIZE				8
-struct qli_reg {
-	u_int32_t		qlr_mbox[QLI_MBOX_SIZE];
-
-	u_int32_t		qlr_flash_addr;
-	u_int32_t		qlr_flash_data;
-	u_int32_t		qlr_ctrl_status;
-#define QLI_REG_CTRLSTAT_SCSI_INTR_ENABLE	(0x1<<2) /* 4010 */
-#define QLI_REG_CTRLSTAT_SCSI_RESET_INTR	(0x1<<3)
-#define QLI_REG_CTRLSTAT_SCSI_COMPL_INTR	(0x1<<4)
-#define QLI_REG_CTRLSTAT_SCSI_PROC_INTR		(0x1<<5)
-#define QLI_REG_CTRLSTAT_EP_INTR		(0x1<<6)
-#define QLI_REG_CTRLSTAT_BOOT_ENABLE		(0x1<<7)
-#define QLI_REG_CTRLSTAT_FUNC_MASK		(0x0700) /* 4022 */
-#define QLI_REG_CTRLSTAT_NET_INTR_ENABLE	(0x1<<10) /* 4010 */
-#define QLI_REG_CTRLSTAT_NET_RESET_INTR		(0x1<<11) /* 4010 */
-#define QLI_REG_CTRLSTAT_NET_COMPL_INTR		(0x1<<12) /* 4010 */
-#define QLI_REG_CTRLSTAT_FORCE_SOFT_RESET	(0x1<<13) /* 4022 */
-#define QLI_REG_CTRLSTAT_FATAL_ERROR		(0x1<<14)
-#define QLI_REG_CTRLSTAT_SOFT_RESET		(0x1<<15)
-
-	union {
-		struct {
-			u_int32_t	q10_nvram;
-			u_int32_t 	q10_res[2];
-		} __packed isp4010;
-		struct {
-			u_int32_t	q22_intr_mask;
-#define QLI_REG_CTRLSTAT_SCSI_INTR_ENABLE_4022	(0x1<<2) /* 4022 */
-			u_int32_t	q22_nvram;
-			u_int32_t	q22_sem;
-		} __packed isp4022;
-	} u1;
-
-	
-	u_int32_t		qlr_producer;
-	u_int32_t		qlr_consumer;
-
-	u_int32_t		qlr_res[2];
-	u_int32_t		qlr_amc;
-	u_int32_t		qlr_amd;
-
-	union {
-		struct {
-			u_int32_t	q10_ext_hw_conf;
-			u_int32_t	q10_flow_ctrl;
-			u_int32_t	q10_port_ctrl;
-			u_int32_t	q10_port_status;
-			u_int32_t	q10_res1[8];
-			u_int32_t	q10_req_q_out;
-			u_int32_t	q10_res2[23];
-			u_int32_t	q10_gp_out;
-			u_int32_t	q10_gp_in;
-			u_int32_t	q10_probe_mux_addr;
-			u_int32_t	q10_probe_mux_data;
-			u_int32_t	q10_res3[3];
-			u_int32_t	q10_port_err_stat;
-		} __packed isp4010;
-		struct {
-			union {
-				struct qli_port_regs	q22_pr;
-				struct qli_mem_regs	q22_mr;
-				struct qli_ram_regs	q22_rr;
-				struct qli_stat_regs	q22_sr;
-				u_int32_t		q22_union[44];
-			};
-
-		} __packed isp4022;
-	} u2;
-} __packed;
-
-#define QLI_PORT_CTRL_INITIALIZED		(0x1<<15) /* hw init done */
-#define QLI_PORT_CTRL(s) (s->sc_ql4010 ? \
-	&s->sc_reg->u2.isp4010.q10_port_ctrl : \
-	&s->sc_reg->u2.isp4022.q22_pr.qpr_port_ctrl)
-
-#define QLI_PORT_STATUS_RESET_INTR		(0x1<<3) /* reset interrupt */
-#define QLI_PORT_STATUS(sc) (sc->sc_ql4010 ? \
-	&sc->sc_reg->u2.isp4010.q10_port_status : \
-	&sc->sc_reg->u2.isp4022.q22_pr.qpr_port_status)
-
-#define QLI_SET_MASK(v)	((v & 0xffff) | (v << 16))
-#define QLI_CLR_MASK(v) (0 | (v << 16))
-
-/* semaphores */
-#define QLI_SEM_MAX_RETRIES				(3)
-#define QLI_SEM_4010_SCSI				(0x2) /* 4010 */
-
-#define QLI_SEMAPHORE(s) (s->sc_ql4010 ? \
-	&s->sc_reg->u1.isp4010.q10_nvram : \
-	&s->sc_reg->u1.isp4022.q22_sem)
-
-/* nvram sempahore */
-#define QLI_SEM_4010_NVRAM_SHIFT			(12)
-#define QLI_SEM_4022_NVRAM_SHIFT			(10)
-#define QLI_SEM_4010_NVRAM_MASK				(0x30000000)
-#define QLI_SEM_4022_NVRAM_MASK				(0x1c000000)
-#define QLI_SEM_NVRAM(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_NVRAM_SHIFT: \
-	QLI_SEM_4022_NVRAM_SHIFT)
-#define QLI_SEM_NVRAM_MASK(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_NVRAM_MASK: \
-	QLI_SEM_4022_NVRAM_MASK)
-
-/* flash memory sempahore */
-#define QLI_SEM_4010_FLASH_SHIFT			(14)
-#define QLI_SEM_4022_FLASH_SHIFT			(13)
-#define QLI_SEM_4010_FLASH_MASK				(0xc0000000)
-#define QLI_SEM_4022_FLASH_MASK				(0xe0000000)
-#define QLI_SEM_FLASH(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_FLASH_SHIFT: \
-	QLI_SEM_4022_FLASH_SHIFT)
-#define QLI_SEM_FLASH_MASK(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_FLASH_MASK: \
-	QLI_SEM_4022_FLASH_MASK)
-
-/* memory semaphore */
-#define QLI_SEM_4010_MEM_SHIFT				(8)
-#define QLI_SEM_4022_MEM_SHIFT				(4)
-#define QLI_SEM_4010_MEM_MASK				(0x03000000)
-#define QLI_SEM_4022_MEM_MASK				(0x00700000)
-#define QLI_SEM_MEM(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_MEM_SHIFT: \
-	QLI_SEM_4022_MEM_SHIFT)
-#define QLI_SEM_MEM_MASK(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_MEM_MASK: \
-	QLI_SEM_4022_MEM_MASK)
-
-/* gpio & phy semaphore are the same on the 4022 */
-#define QLI_SEM_4010_PHY_SHIFT				(10)
-#define QLI_SEM_4022_PHY_SHIFT				(7)
-#define QLI_SEM_4010_PHY_MASK				(0x0c000000)
-#define QLI_SEM_4022_PHY_MASK				(0x03800000)
-#define QLI_SEM_PHY(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_PHY_SHIFT: \
-	QLI_SEM_4022_PHY_SHIFT)
-#define QLI_SEM_PHY_MASK(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_PHY_MASK: \
-	QLI_SEM_4022_PHY_MASK)
-
-#define QLI_SEM_4010_GPIO_SHIFT				(6)
-#define QLI_SEM_4022_GPIO_SHIFT				QLI_SEM_4022_PHY_SHIFT
-#define QLI_SEM_4010_GPIO_MASK				(0x00c00000)
-#define QLI_SEM_4022_GPIO_MASK				QLI_SEM_4022_PHY_MASK
-#define QLI_SEM_GPIO(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_GPIO_SHIFT: \
-	QLI_SEM_4022_GPIO_SHIFT)
-#define QLI_SEM_GPIO_MASK(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_GPIO_MASK: \
-	QLI_SEM_4022_GPIO_MASK)
-
-/* global driver semaphore */
-#define QLI_SEM_4010_DRIVER_SHIFT			(4)
-#define QLI_SEM_4022_DRIVER_SHIFT			(1)
-#define QLI_SEM_4010_DRIVER_MASK			(0x00300000)
-#define QLI_SEM_4022_DRIVER_MASK			(0x000e0000)
-#define QLI_SEM_DRIVER(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_DRIVER_SHIFT: \
-	QLI_SEM_4022_DRIVER_SHIFT)
-#define QLI_SEM_DRIVER_MASK(s) (s->sc_ql4010 ? \
-	QLI_SEM_4010_DRIVER_MASK: \
-	QLI_SEM_4022_DRIVER_MASK)
-
-/* mailbox commands */
-#define QLI_MBOX_OPC_ABOUT_FIRMWARE			(0x09)
-#define QLI_MBOX_OPC_GET_FW_STATUS			(0x1f)
-#define QLI_MBOX_OPC_GET_INITIAL_FW_CB			(0x61)
-#define QLI_MBOX_OPC_GET_FW_STATE			(0x69)
-		/* mbox 1 firmware state */
-#define		QLI_MBOX_STATE_READY			(0x0<<0)
-#define		QLI_MBOX_STATE_CONFIG_WAIT		(0x1<<0)
-#define		QLI_MBOX_STATE_WAIT_AUTOCONNECT		(0x1<<1)
-#define		QLI_MBOX_STATE_ERROR			(0x1<<2)
-#define		QLI_MBOX_STATE_CONFIGURING_IP		(0x1<<3)
-#define		QLI_MBOX_STATE_WAIT_ACTIVATE_PRI_ACB	(0x1<<4)
-#define		QLI_MBOX_STATE_WAIT_ACTIVATE_SEC_ACB	(0x1<<5)
-		/* mbox 2 chip version */
-		/* mbox 3 additional state flags */
-#define		QLI_MBOX_ASTATE_COPPER_MEDIA		(0x0<<0)
-#define		QLI_MBOX_ASTATE_OPTICAL_MEDIA		(0x1<<0)
-#define		QLI_MBOX_ASTATE_DHCPv4_ENABLED		(0x1<<1)
-#define		QLI_MBOX_ASTATE_DHCPv4_LEASE_ACQUIRED	(0x1<<2)
-#define		QLI_MBOX_ASTATE_DHCPv4_LEASE_EXPIRED	(0x1<<3)
-#define		QLI_MBOX_ASTATE_LINK_UP			(0x1<<4)
-#define		QLI_MBOX_ASTATE_ISNSv4_SVC_ENABLED	(0x1<<5)
-#define		QLI_MBOX_ASTATE_LINK_SPEED_10MBPS	(0x1<<8)
-#define		QLI_MBOX_ASTATE_LINK_SPEED_100MBPS	(0x1<<9)
-#define		QLI_MBOX_ASTATE_LINK_SPEED_1000MBPS	(0x1<<10)
-#define		QLI_MBOX_ASTATE_HALF_DUPLEX		(0x1<<12)
-#define		QLI_MBOX_ASTATE_FULL_DUPLEX		(0x1<<13)
-#define		QLI_MBOX_ASTATE_FLOW_CTRL_ENABLED	(0x1<<14)
-#define		QLI_MBOX_ASTATE_AUTONEG_ENABLED		(0x1<<15)
-#define		QLI_MBOX_ASTATE_FW_CTRLS_PORT_LINK	(0x1<<16)
-#define		QLI_MBOX_ASTATE_PAUSE_TX_ENABLED	(0x1<<17)
-#define		QLI_MBOX_ASTATE_PAUSE_RX_ENABLED	(0x1<<18)
-#define		QLI_MBOX_ASTATE_IPV4_PRI_ENABLED	(0x1<<19)
-#define		QLI_MBOX_ASTATE_IPV4_SEC_ENABLED	(0x1<<20)
-#define		QLI_MBOX_ASTATE_IPV6_PRI_ENABLED	(0x1<<21)
-#define		QLI_MBOX_ASTATE_IPV6_SEC_ENABLED	(0x1<<22)
-#define		QLI_MBOX_ASTATE_DHCPV6_ENABLED		(0x1<<23)
-#define		QLI_MBOX_ASTATE_IPV6_AUTOCONFIG_ENABLED	(0x1<<24)
-#define		QLI_MBOX_ASTATE_IPV6_ADDR0_STATE	(0x1<<25)
-#define		QLI_MBOX_ASTATE_IPV6_ADDR0_EXPIRED	(0x1<<26)
-#define		QLI_MBOX_ASTATE_IPV6_ADDR1_STATE	(0x1<<27)
-#define		QLI_MBOX_ASTATE_IPV6_ADDR1_EXPIRED	(0x1<<28)
-#define QLI_MBOX_OPC_NOOP				(0xFF)
-
-/* mailbox status */
-#define QLI_MBOX_TYPE_SHIFT				(12)
-#define QLI_MBOX_COMPLETION_STATUS			(4)
-#define QLI_MBOX_STATUS_BUSY				(0x0007)
-#define QLI_MBOX_STATUS_INTERMEDIATE_COMPLETION		(0x1000)
-#define QLI_MBOX_STATUS_COMMAND_COMPLETE		(0x4000)
-#define QLI_MBOX_STATUS_INVALID_COMMAND			(0x4001)
-#define QLI_MBOX_STATUS_HOST_INTERFACE_ERROR		(0x4002)
-#define QLI_MBOX_STATUS_TEST_FAILED			(0x4003)
-#define QLI_MBOX_STATUS_COMMAND_ERROR			(0x4005)
-#define QLI_MBOX_STATUS_COMMAND_PARAMETER_ERROR		(0x4006)
-#define QLI_MBOX_STATUS_TARGET_MODE_INIT_FAIL		(0x4007)
-#define QLI_MBOX_STATUS_INITIATOR_MODE_INIT_FAIL	(0x4008)
-
-/* async events */
-#define QLI_MBOX_ASYNC_EVENT_STATUS			(8)
-#define QLI_MBOX_AES_SYSTEM_ERROR			(0x8002)
-#define QLI_MBOX_AES_REQUEST_TRANSFER_ERROR		(0x8003)
-#define QLI_MBOX_AES_RESPONSE_TRANSFER_ERROR		(0x8004)
-#define QLI_MBOX_AES_PROTOCOL_STATISTIC_ALARM		(0x8005)
-#define QLI_MBOX_AES_SCSI_COMMAND_PDU_REJECTED		(0x8006)
-#define QLI_MBOX_AES_LINK_UP				(0x8010)
-#define QLI_MBOX_AES_LINK_DOWN				(0x8011)
-#define QLI_MBOX_AES_DATABASE_CHANGED			(0x8014)
-
-/* external hardware config */
-#define QLI_EXT_HW_CFG(s) (s->sc_ql4010 ? \
-	&s->sc_reg->u2.isp4010.q10_ext_hw_conf : \
-	&s->sc_reg->u2.isp4022.q22_pr.qpr_ext_hw_conf)
-
-#define QLI_EXT_HW_CFG_DEFAULT_QL4010			(0x1912)
-#define QLI_EXT_HW_CFG_DEFAULT_QL4022			(0x0023)
-
-#define		QLI_EXT_HW_CFG_IGNORE_SHRINK_TCP_WINDOW	(0x1<<0)
-#define		QLI_EXT_HW_CFG_SDRAM_PROTECTION_NONE	(0x00)
-#define		QLI_EXT_HW_CFG_SDRAM_PROTECTION_BYTE	(0x02)
-#define		QLI_EXT_HW_CFG_SDRAM_PROTECTION_ECC	(0x04)
-#define		QLI_EXT_HW_CFG_SDRAM_PROTECTION_ECC2	(0x06)
-#define		QLI_EXT_HW_CFG_BANKS			(0x1<<3)
-#define		QLI_EXT_HW_CFG_CHIP_WIDTH		(0x1<<4)
-#define		QLI_EXT_HW_CFG_CHIP_SIZE_64M		(0x00)
-#define		QLI_EXT_HW_CFG_CHIP_SIZE_256M		(0x20)
-#define		QLI_EXT_HW_CFG_CHIP_SIZE_512M		(0x40)
-#define		QLI_EXT_HW_CFG_CHIP_SIZE_1G		(0x60)
-#define		QLI_EXT_HW_CFG_PARITY_DISABLE		(0x1<<7)
-#define		QLI_EXT_HW_CFG_EXTERNAL_MEM_TYPE	(0x1<<8)
-#define		QLI_EXT_HW_CFG_FLASH_BIOS_WRT_ENABLE	(0x1<<9)
-#define		QLI_EXT_HW_CFG_FLASH_UPPER_BANK_SELECT	(0x1<<10)
-#define		QLI_EXT_HW_CFG_WRITE_BURST_9MA		(0x0000)
-#define		QLI_EXT_HW_CFG_WRITE_BURST_15MA		(0x0800)
-#define		QLI_EXT_HW_CFG_WRITE_BURST_18MA		(0x1000)
-#define		QLI_EXT_HW_CFG_WRITE_BURST_24MA		(0x1800)
-#define		QLI_EXT_HW_CFG_DDR_DRIVE_STRENGTH_9MA	(0x0000)
-#define		QLI_EXT_HW_CFG_DDR_DRIVE_STRENGTH_15MA	(0x2000)
-#define		QLI_EXT_HW_CFG_DDR_DRIVE_STRENGTH_18MA	(0x4000)
-#define		QLI_EXT_HW_CFG_DDR_DRIVE_STRENGTH_24MA	(0x6000)
-
-/* nvram */
-#define QLI_NVRAM_MASK					(0xf<<16)
-#define QLI_NVRAM(s) (s->sc_ql4010 ? \
-	&s->sc_reg->u1.isp4010.q10_nvram : \
-	&s->sc_reg->u1.isp4022.q22_nvram)
-
-#define QLI_NVRAM_CLOCK					(0x1<<0)
-#define QLI_NVRAM_SELECT				(0x1<<1)
-#define QLI_NVRAM_DATA_OUT				(0x1<<2)
-#define QLI_NVRAM_DATA_IN				(0x1<<3)
-
-#define QLI_NVRAM_SIZE_4010				(0x100)
-#define QLI_NVRAM_SIZE_4022				(0x400)
-#define QLI_NVRAM_SIZE(s) (s->sc_ql4010 ? \
-	QLI_NVRAM_SIZE_4010 : QLI_NVRAM_SIZE_4022)
-
-#define QLI_NVRAM_NUM_CMD_BITS				(0x2)
-#define QLI_NVRAM_CMD_READ				(0x2)
-
-#define QLI_NVRAM_NUM_ADDR_BITS_4010			(0x8)
-#define QLI_NVRAM_NUM_ADDR_BITS_4022			(0xa)
-#define QLI_NVRAM_NUM_ADDR_BITS(s) (s->sc_ql4010 ? \
-	QLI_NVRAM_NUM_ADDR_BITS_4010 : \
-	QLI_NVRAM_NUM_ADDR_BITS_4022)
-
-#define QLI_NVRAM_NUM_DATA_BITS				(0x10)
-
-#define QLI_NVRAM_EXT_HW_CFG_4010			(0xc)
-#define QLI_NVRAM_EXT_HW_CFG_4022			(0x14)
-#define QLI_NVRAM_EXT_HW_CFG(s) (s->sc_ql4010 ? \
-	QLI_NVRAM_EXT_HW_CFG_4010 : \
-	QLI_NVRAM_EXT_HW_CFG_4022)
-
-/* firmware control block */
-#define QLI_FW_CTRL_BLK_SIZE				(0x400) /* 1k */
-struct qli_cb {
-	u_int8_t		qcb_version;
-#define QLI_QCB_VER_NO_ADDTIIONAL_INFO			(0x00)
-#define QLI_QCB_VER_MIN					(0x01)
-#define QLI_QCB_VER_MAX					(0x02)
-	u_int8_t		qcb_ctrl;
-#define QLI_QCB_CTRL_NEW_CONN_DISABLE			(0x02)
-#define QLI_QCB_CTRL_SECONDARY_ACB			(0x01)
-	u_int16_t		qcb_fw_options;
-#define QLI_QCB_FWOPT_HEARTBEAT_ENABLE			(0x1000)
-#define QLI_QCB_FWOPT_MARKER_DISABLE			(0x0400)
-#define QLI_QCB_FWOPT_PROT_STAT_ALARM_DISABLE		(0x0200)
-#define QLI_QCB_FWOPT_TARGET_ACCEPT_AEN_ENABLE		(0x0100)
-#define QLI_QCB_FWOPT_ACCESS_CTRL_ENABLE		(0x0080)
-#define QLI_QCB_FWOPT_SESSION_MODE			(0x0040)
-#define QLI_QCB_FWOPT_INITIATOR_MODE			(0x0020)
-#define QLI_QCB_FWOPT_TARGET_MODE			(0x0010)
-#define QLI_QCB_FWOPT_FAST_POSTING			(0x0008)
-#define QLI_QCB_FWOPT_AUTO_TARGET_INFO_DISABLE		(0x0004)
-#define QLI_QCB_FWOPT_SENSE_BUFFER_DATA_ENABLE		(0x0002)
-	u_int16_t		qcb_exec_throttle;
-	u_int8_t		qcb_zio_count;
-	u_int8_t		qcb_res0;
-	u_int16_t		qcb_max_eth_payload;
-	u_int16_t		qcb_add_fw_options;
-#define QLI_QCB_ADDFWOPT_AUTOCONNECT_DISABLE		(0x0002)
-#define QLI_QCB_ADDFWOPT_SUSPEND_ON_FW_ERROR		(0x0001)
-	u_int8_t		qcb_heartbeat_intr;
-	u_int8_t		qcb_instance_nr;
-	u_int16_t		qcb_res1;
-	u_int16_t		qcb_req_q_cons_idx;  /* 4010 */
-	u_int16_t		qcb_comp_q_prod_idx; /* 4010 */
-	u_int16_t		qcb_req_q_len;
-	u_int16_t		qcb_comp_q_len;
-	u_int32_t		qcb_req_q_addr_lo;
-	u_int32_t		qcb_req_q_addr_hi;
-	u_int32_t		qcb_comp_q_addr_lo;
-	u_int32_t		qcb_comp_q_addr_hi;
-	u_int32_t		qcb_shadow_reg_addr_lo;
-	u_int32_t		qcb_shadow_reg_addr_hi;
-	u_int16_t		qcb_iscsi_options;
-#define QLI_QCB_ISCSIOPTS_RECV_MARKER_ENABLE		(0x8000)
-#define QLI_QCB_ISCSIOPTS_SEND_MARKER_ENABLE		(0x4000)
-#define QLI_QCB_ISCSIOPTS_HDR_DIGEST_ENABLE		(0x2000)
-#define QLI_QCB_ISCSIOPTS_DATA_DIGEST_ENABLE		(0x1000)
-#define QLI_QCB_ISCSIOPTS_IMMEDIATE_DATA_ENABLE		(0x0800)
-#define QLI_QCB_ISCSIOPTS_INITIAL_R2T_ENABLE		(0x0400)
-#define QLI_QCB_ISCSIOPTS_DATA_SEQ_IN_ORDER		(0x0200)
-#define QLI_QCB_ISCSIOPTS_DATA_PDU_IN_ORDER		(0x0100)
-#define QLI_QCB_ISCSIOPTS_CHAP_AUTH_ENABLE		(0x0080)
-#define QLI_QCB_ISCSIOPTS_SNACK_REQ_ENABLE		(0x0040)
-#define QLI_QCB_ISCSIOPTS_DISCOVERY_LOGOUT_ENABLE	(0x0020)
-#define QLI_QCB_ISCSIOPTS_BIDIR_CHAP_ENABLE		(0x0010)
-	u_int16_t		qcb_tcp_options;
-#define QLI_QCB_TCPOPTS_ISNS_ENABLE			(0x4000)
-#define QLI_QCB_TCPOPTS_SLP_USE_DA_ENABLE		(0x2000)
-#define QLI_QCB_TCPOPTS_AUTO_DISCOVERY_ENABLE		(0x1000)
-#define QLI_QCB_TCPOPTS_SLP_UA_ENABLE			(0x0800)
-#define QLI_QCB_TCPOPTS_SLP_SA_ENABLE			(0x0400)
-#define QLI_QCB_TCPOPTS_DHCP_ENABLE			(0x0200)
-#define QLI_QCB_TCPOPTS_GET_DNS_VIA_DHCP_ENABLE		(0x0100)
-#define QLI_QCB_TCPOPTS_GET_SLP_VIA_DHCP_ENABLE		(0x0080)
-#define QLI_QCB_TCPOPTS_LEARN_ISNS_IPADDR_ENABLE	(0x0040)
-#define QLI_QCB_TCPOPTS_NAGLE_DISABLE			(0x0020)
-#define QLI_QCB_TCPOPTS_TIMER_SCALE_MASK		(0x000e)
-#define QLI_QCB_TCPOPTS_TIME_STAMP_ENABLE		(0x0001)
-	u_int16_t		qcb_ip_options;
-#define QLI_QCB_IPOPTS_IPV4_ENABLE			(0x8000)
-#define QLI_QCB_IPOPTS_IPV4_TOS_ENABLE			(0x4000)
-#define QLI_QCB_IPOPTS_VLAN_TAGGING_ENABLE		(0x2000)
-#define QLI_QCB_IPOPTS_GRAT_ARP_ENABLE			(0x1000)
-#define QLI_QCB_IPOPTS_DHCP_USE_ALT_CLIENT_ID		(0x0800)
-#define QLI_QCB_IPOPTS_DHCP_REQUIRE_VENDOR_ID		(0x0400)
-#define QLI_QCB_IPOPTS_DHCP_USE_VENDOR_ID		(0x0200)
-#define QLI_QCB_IPOPTS_LEARN_IQN			(0x0100)
-#define QLI_QCB_IPOPTS_FRAG_DISABLE			(0x0010)
-#define QLI_QCB_IPOPTS_INCOMMING_FORWARDING_ENABLE	(0x0008)
-#define QLI_QCB_IPOPTS_ARP_REDIRECT_ENABLE		(0x0004)
-#define QLI_QCB_IPOPTS_PAUSE_FRAME_ENABLE		(0x0002)
-#define QLI_QCB_IPOPTS_IPADDR_VALID			(0x0001)
-	u_int16_t		qcb_max_pdu_size;
-	u_int8_t		qcb_tos;
-	u_int8_t		qcb_ttl;
-	u_int8_t		qcb_acb_version;
-#define QLI_QCB_ACBVER_NOT_SUPPORTED			(0x00)
-#define QLI_QCB_ACBVER_SUPPORTED			(0x02)
-	u_int8_t		qcb_res2;
-	u_int16_t		qcb_def_timeout;
-	u_int16_t		qcb_first_burst_size;
-	u_int16_t		qcb_def_time_to_wait;
-	u_int16_t		qcb_def_time_to_retain;
-	u_int16_t		qcb_max_out_r2t;
-	u_int16_t		qcb_keep_alive_timeout;
-	u_int16_t		qcb_port;
-	u_int16_t		max_burst_size;
-	u_int32_t		qcb_res3;
-	u_int32_t		qcb_ip_addr;
-	u_int16_t		qcb_vlan_tag_ctrl;
-	u_int8_t		qcb_ip_addr_state;
-	u_int8_t		qcb_ip_cache_id;
-	u_int8_t		qcb_res4[8];
-	u_int32_t		qcb_subnet_mask;
-	u_int8_t		qcb_res5[12];
-	u_int32_t		qcb_gateway_addr;
-	u_int8_t		qcb_res6[12];
-	u_int32_t		qcb_pri_dns_addr;
-	u_int32_t		qcb_sec_dns_addr;
-	u_int16_t		qcb_min_eport;
-	u_int16_t		qcb_max_eport;
-	u_int8_t		qcb_res7[4];
-	u_int8_t		qcb_iscsi_alias[32];
-	u_int8_t		qcb_res8[24];
-	u_int8_t		qcb_abort_timer;
-	u_int8_t		qcb_tcp_win_scale_factor;
-	u_int8_t		qcb_res9[10];
-	u_int8_t		qcb_dhcp_vendor_id_len;
-	u_int8_t		qcb_dhcp_vendor_id[11];
-	u_int32_t		qcb_isns_addr;
-	u_int16_t		qcb_isns_port;
-	u_int8_t		qcb_res10[14];
-	u_int8_t		qcb_dhcp_client_id_len;
-	u_int8_t		qcb_dhcp_client_id[11];
-	u_int8_t		qcb_iscsi_name[224];
-	u_int8_t		qcb_res11[32];
-	u_int32_t		qcb_cookie;
-#define QLI_QCB_COOKIE				(0x11bead5a)
-	/* ip v6 section */
-	u_int16_t		qcb_ipv6_port;
-	u_int16_t		qcb_ipv6_options;
-#define QLI_QCB_IPV6OPTS_IPV6_ENABLE		(0x8000)
-#define QLI_QCB_IPV6OPTS_VLAN_TAGGING_ENABLE	(0x2000)
-#define QLI_QCB_IPV6OPTS_GRAT_NEIGHBOR_ENABLE	(0x1000)
-#define QLI_QCB_IPV6OPTS_INBOUND_FORW_ENABLE	(0x0008)
-	u_int16_t		qcb_ipv6_add_options;
-#define QLI_QCB_IPV6AOPTS_NEIGHB_DISC_ENABLE	(0x0002)
-#define QLI_QCB_IPV6AOPTS_AUTOCFG_LINK_ENABLE	(0x0001)
-	u_int16_t		qcb_ipv6_tcp_options;
-#define QLI_QCB_IPV6TCPOPTS_DELAYED_ACK_DISABLE	(0x8000)
-#define QLI_QCB_IPV6TCPOPTS_ISNS_ENABLE		(0x4000)
-#define QLI_QCB_IPV6TCPOPTS_TCP_WINDOW_SCALE	(0x0400)
-#define QLI_QCB_IPV6TCPOPTS_NAGLE_DISABLE	(0x0020)
-#define QLI_QCB_IPV6TCPOPTS_TCP_WIN_SCALE_DISA	(0x0010)
-#define QLI_QCB_IPV6TCPOPTS_TIMER_SCALE_MASK	(0x000e)
-#define QLI_QCB_IPV6TCPOPTS_TIME_STAMP_ENABLE	(0x0001)
-	u_int8_t		qcb_ipv6_tcp_recv_scale;
-	u_int8_t		qcb_ipv6_flow_label[3];
-	u_int8_t		qcb_ipv6_def_router_addr[16];
-	u_int8_t		qcb_ipv6_vlan_tci[2];
-	u_int8_t		qcb_ipv6_link_local_addr_state;
-#define QLI_QCB_IPV6_LLAS_UNCONFIGURED		(0x00)
-#define QLI_QCB_IPV6_LLAS_INVALID		(0x01)
-#define QLI_QCB_IPV6_LLAS_ACQUIRING		(0x02)
-#define QLI_QCB_IPV6_LLAS_TENTATIVE		(0x03)
-#define QLI_QCB_IPV6_LLAS_DEPRECATED		(0x04)
-#define QLI_QCB_IPV6_LLAS_PREFERRED		(0x05)
-#define QLI_QCB_IPV6_LLAS_DISABLING		(0x06)
-	u_int8_t		qcb_ipv6_addr0_state;
-	u_int8_t		qcb_ipv6_addr1_state;
-	u_int8_t		qcb_ipv6_def_router_state;
-	u_int8_t		qcb_ipv6_traf_class;
-	u_int8_t		qcb_ipv6_hop_limit;
-	u_int8_t		qcb_ipv6_iface_id[8];
-	u_int8_t		qcb_ipv6_addr0[16];
-	u_int8_t		qcb_ipv6_addr1[16];
-	u_int32_t		qcb_ipv6_nd_reachable_time;
-	u_int32_t		qcb_ipv6_nd_retransmit_timer;
-	u_int32_t		qcb_ipv6_nd_stale_timeout;
-	u_int8_t		qcb_ipv6_dup_addr_count;
-	u_int8_t		qcb_ipv6_cache_id;
-	u_int8_t		qcb_ipv6_res0[2];
-	u_int8_t		qcb_ipv6_isns_addr1[16];
-	u_int8_t		qcb_ipv6_router_ad_lnk_mtu[4];
-	u_int8_t		qcb_ipv6_res1[140];
-} __packed;
-
-/* queues */
-#define QLI_REQUESTQ_DEPTH			(1024)
-#define QLI_QUEUE_SIZE				(64)
-#define QLI_RESPONSEQ_DEPTH			(64)
-
-struct qli_queue_entry {
-	u_int8_t		qqe_data[60];
-	u_int32_t		qqe_signature;
-} __packed;
-
-/* shadow regs */
-struct qli_shadow_regs {
-	u_int32_t		qsr_req_q;
-	u_int32_t		qsr_resp_q;
-} __packed;