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author | 2018-04-03 09:31:00 +0000 | |
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committer | 2018-04-03 09:31:00 +0000 | |
commit | 370f045f0fe0db10deed37990658f5598ebb3c58 (patch) | |
tree | 8f634545063af20fd2c242bb1af07612a34d8103 | |
parent | Move FREF()s just after fd_getfile() in sys_kevent(), sys_lseek() and (diff) | |
download | wireguard-openbsd-370f045f0fe0db10deed37990658f5598ebb3c58.tar.xz wireguard-openbsd-370f045f0fe0db10deed37990658f5598ebb3c58.zip |
Match on the more specific "marvell,armada8k-pcie" instead of the generic
"snps,dw-pcie" for now. There are considerable variations between
implementations of the Synapsys Designware PCIe core and glue logic and
the current code isn't flexible enough to deal with that yet.
-rw-r--r-- | sys/dev/fdt/dwpcie.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/dev/fdt/dwpcie.c b/sys/dev/fdt/dwpcie.c index a7808d829a7..29e35de5fa3 100644 --- a/sys/dev/fdt/dwpcie.c +++ b/sys/dev/fdt/dwpcie.c @@ -1,4 +1,4 @@ -/* $OpenBSD: dwpcie.c,v 1.1 2018/04/02 15:25:27 kettenis Exp $ */ +/* $OpenBSD: dwpcie.c,v 1.2 2018/04/03 09:31:00 kettenis Exp $ */ /* * Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org> * @@ -87,7 +87,7 @@ dwpcie_match(struct device *parent, void *match, void *aux) { struct fdt_attach_args *faa = aux; - return OF_is_compatible(faa->fa_node, "snps,dw-pcie"); + return OF_is_compatible(faa->fa_node, "marvell,armada8k-pcie"); } void dwpcie_atr_init(struct dwpcie_softc *); |