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authorkettenis <kettenis@openbsd.org>2020-04-08 21:32:27 +0000
committerkettenis <kettenis@openbsd.org>2020-04-08 21:32:27 +0000
commit4d55a1025304b0d9d50bce2473be87bc046aef61 (patch)
tree9ed81acc1519657e13fca5121dfe2b10a6fe69d4
parentPrevent multiple ibuf leaks. Clean up on proccess shutdown. (diff)
downloadwireguard-openbsd-4d55a1025304b0d9d50bce2473be87bc046aef61.tar.xz
wireguard-openbsd-4d55a1025304b0d9d50bce2473be87bc046aef61.zip
Add RK3328 Crypto/RNG clocks.
-rw-r--r--sys/dev/fdt/rkclock.c10
-rw-r--r--sys/dev/fdt/rkclock_clocks.h2
2 files changed, 11 insertions, 1 deletions
diff --git a/sys/dev/fdt/rkclock.c b/sys/dev/fdt/rkclock.c
index 1d72db6b7f3..ffd18eda634 100644
--- a/sys/dev/fdt/rkclock.c
+++ b/sys/dev/fdt/rkclock.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: rkclock.c,v 1.51 2020/03/01 17:57:33 kettenis Exp $ */
+/* $OpenBSD: rkclock.c,v 1.52 2020/04/08 21:32:27 kettenis Exp $ */
/*
* Copyright (c) 2017, 2018 Mark Kettenis <kettenis@openbsd.org>
*
@@ -883,6 +883,11 @@ struct rkclock rk3328_clocks[] = {
{ RK3328_PLL_CPLL, RK3328_PLL_GPLL }
},
{
+ RK3328_CLK_CRYPTO, RK3328_CRU_CLKSEL_CON(20),
+ SEL(7, 7), DIV(4, 0),
+ { RK3328_PLL_CPLL, RK3328_PLL_GPLL }
+ },
+ {
RK3328_CLK_PDM, RK3328_CRU_CLKSEL_CON(20),
SEL(15, 14), DIV(12, 8),
{ RK3328_PLL_CPLL, RK3328_PLL_GPLL, RK3328_PLL_APLL },
@@ -1422,6 +1427,9 @@ rk3328_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)
RK3328_CRU_VOP_DCLK_SRC_SEL_SHIFT;
idx = (mux == 0) ? RK3328_HDMIPHY : RK3328_DCLK_LCDC_SRC;
return rk3328_set_frequency(sc, &idx, freq);
+ case RK3328_HCLK_CRYPTO_SLV:
+ idx = RK3328_HCLK_BUS_PRE;
+ return rk3328_set_frequency(sc, &idx, freq);
default:
break;
}
diff --git a/sys/dev/fdt/rkclock_clocks.h b/sys/dev/fdt/rkclock_clocks.h
index 7c249cb2ebe..575988058f8 100644
--- a/sys/dev/fdt/rkclock_clocks.h
+++ b/sys/dev/fdt/rkclock_clocks.h
@@ -63,6 +63,7 @@
#define RK3328_CLK_I2C1 56
#define RK3328_CLK_I2C2 57
#define RK3328_CLK_I2C3 58
+#define RK3328_CLK_CRYPTO 59
#define RK3328_CLK_PDM 61
#define RK3328_CLK_VDEC_CABAC 65
#define RK3328_CLK_VDEC_CORE 66
@@ -92,6 +93,7 @@
#define RK3328_HCLK_PERI 308
#define RK3328_HCLK_BUS_PRE 328
+#define RK3328_HCLK_CRYPTO_SLV 337
#define RK3328_XIN24M 1023
#define RK3328_CLK_24M 1022