rename some defines as well

16 files changed, 406 insertions, 406 deletions

diff --git a/sys/arch/armv7/sunxi/a1xintc.c b/sys/arch/armv7/sunxi/a1xintc.c
index cf19c394aed..c080a0a8dd6 100644
--- a/sys/arch/armv7/sunxi/a1xintc.c
+++ b/sys/arch/armv7/sunxi/a1xintc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: a1xintc.c,v 1.1 2013/10/23 17:08:47 jasper Exp $	*/
+/*	$OpenBSD: a1xintc.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -318,9 +318,9 @@ intc_irq_handler(void *frame)
 	if (irq == 0)
 		return;
 	if (irq == 1)
-		sxipio_togglepin(AWPIO_LED_BLUE);
+		sxipio_togglepin(SXIPIO_LED_BLUE);
 
-	sxipio_setpin(AWPIO_LED_GREEN);
+	sxipio_setpin(SXIPIO_LED_GREEN);
 
 	prio = intc_handler[irq].iq_irq;
 	s = intc_splraise(prio);
@@ -356,7 +356,7 @@ intc_irq_handler(void *frame)
 	}
 	intc_splx(s);
 
-	sxipio_clrpin(AWPIO_LED_GREEN);
+	sxipio_clrpin(SXIPIO_LED_GREEN);
 }
 
 void *
diff --git a/sys/arch/armv7/sunxi/sun4i.c b/sys/arch/armv7/sunxi/sun4i.c
index 418514cf619..207bd1ffbec 100644
--- a/sys/arch/armv7/sunxi/sun4i.c
+++ b/sys/arch/armv7/sunxi/sun4i.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sun4i.c,v 1.1 2013/10/23 17:08:47 jasper Exp $	*/
+/*	$OpenBSD: sun4i.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2011 Uwe Stuehler <uwe@openbsd.org>
  *
@@ -122,7 +122,7 @@ struct sxi_dev sxia1x_devs[] = {
 	{ .name = "sxie",
 	  .unit = 0,
 	  .mem = {	{ EMAC_ADDR, EMAC_SIZE },
-			{ AWESRAM_ADDR, AWESRAM_SIZE } },
+			{ SXIESRAM_ADDR, SXIESRAM_SIZE } },
 	  .irq = { EMAC_IRQ}
 	},
 
diff --git a/sys/arch/armv7/sunxi/sun7i.c b/sys/arch/armv7/sunxi/sun7i.c
index ef32ea810f5..ed099690ebc 100644
--- a/sys/arch/armv7/sunxi/sun7i.c
+++ b/sys/arch/armv7/sunxi/sun7i.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sun7i.c,v 1.1 2013/10/23 17:08:47 jasper Exp $ */
+/* $OpenBSD: sun7i.c,v 1.2 2013/10/23 18:01:52 jasper Exp $ */
 
 /*
  * Copyright (c) 2011 Uwe Stuehler <uwe@openbsd.org>
@@ -117,7 +117,7 @@ struct sxi_dev sxia20_devs[] = {
 	{ .name = "sxie",
 	  .unit = 0,
 	  .mem = {	{ EMAC_ADDR, EMAC_SIZE },
-			{ AWESRAM_ADDR, AWESRAM_SIZE } },
+			{ SXIESRAM_ADDR, SXIESRAM_SIZE } },
 	  .irq = { EMAC_IRQ}
 	},
 
diff --git a/sys/arch/armv7/sunxi/sunxi.c b/sys/arch/armv7/sunxi/sunxi.c
index 1e8a147c092..2d157fe02f9 100644
--- a/sys/arch/armv7/sunxi/sunxi.c
+++ b/sys/arch/armv7/sunxi/sunxi.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sunxi.c,v 1.1 2013/10/23 17:08:48 jasper Exp $ */
+/* $OpenBSD: sunxi.c,v 1.2 2013/10/23 18:01:52 jasper Exp $ */
 /*
  * Copyright (c) 2005,2008 Dale Rahn <drahn@openbsd.com>
  *
@@ -169,7 +169,7 @@ sunxi_attach(struct device *parent, struct device *self, void *aux)
 	    &sc->sc_ioh))
 		panic("sunxi_attach: bus_space_map failed!");
 	/* map the part of SRAM dedicated to EMAC to EMAC */
-	AWSET4(sc, 4, 5 << 2);
+	SXISET4(sc, 4, 5 << 2);
 #endif
 
 	/* Directly configure on-board devices (dev* in config file). */
diff --git a/sys/arch/armv7/sunxi/sunxireg.h b/sys/arch/armv7/sunxi/sunxireg.h
index a157837b9c7..c86d8a7e31f 100644
--- a/sys/arch/armv7/sunxi/sunxireg.h
+++ b/sys/arch/armv7/sunxi/sunxireg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sunxireg.h,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sunxireg.h,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2013 Artturi Alm
  *
@@ -88,8 +88,8 @@
 #define	EMAC_ADDR		0x01c0b000
 #define	EMAC_SIZE		0x1000
 #define	EMAC_IRQ		55
-#define	AWESRAM_ADDR		0x00008000 /* combined area for EMAC fifos */
-#define	AWESRAM_SIZE		0x4000
+#define	SXIESRAM_ADDR		0x00008000 /* combined area for EMAC fifos */
+#define	SXIESRAM_SIZE		0x4000
 
 /* Security System */
 #define	SS_ADDR			0x01c15000 /* not in use */
diff --git a/sys/arch/armv7/sunxi/sunxivar.h b/sys/arch/armv7/sunxi/sunxivar.h
index 84f9c9b9fe6..1e3fe09cff1 100644
--- a/sys/arch/armv7/sunxi/sunxivar.h
+++ b/sys/arch/armv7/sunxi/sunxivar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sunxivar.h,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sunxivar.h,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2005,2008 Dale Rahn <drahn@drahn.com>
  *
@@ -18,27 +18,27 @@
 #include <machine/bus.h>
 
 
-#define AWREAD1(sc, reg)						\
+#define SXIREAD1(sc, reg)						\
 	(bus_space_read_1((sc)->sc_iot, (sc)->sc_ioh, (reg)))
-#define AWWRITE1(sc, reg, val)						\
+#define SXIWRITE1(sc, reg, val)						\
 	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
-#define AWSET1(sc, reg, bits)						\
-	AWWRITE1((sc), (reg), AWREAD1((sc), (reg)) | (bits))
-#define AWCLR1(sc, reg, bits)						\
-	AWWRITE1((sc), (reg), AWREAD1((sc), (reg)) & ~(bits))
-#define	AWCMS1(sc, reg, mask, bits)					\
-	AWWRITE1((sc), (reg), (AWREAD1((sc), (reg)) & ~(mask)) | (bits))
+#define SXISET1(sc, reg, bits)						\
+	SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) | (bits))
+#define SXICLR1(sc, reg, bits)						\
+	SXIWRITE1((sc), (reg), SXIREAD1((sc), (reg)) & ~(bits))
+#define	SXICMS1(sc, reg, mask, bits)					\
+	SXIWRITE1((sc), (reg), (SXIREAD1((sc), (reg)) & ~(mask)) | (bits))
 
-#define AWREAD4(sc, reg)						\
+#define SXIREAD4(sc, reg)						\
 	(bus_space_read_4((sc)->sc_iot, (sc)->sc_ioh, (reg)))
-#define AWWRITE4(sc, reg, val)						\
+#define SXIWRITE4(sc, reg, val)						\
 	bus_space_write_4((sc)->sc_iot, (sc)->sc_ioh, (reg), (val))
-#define AWSET4(sc, reg, bits)						\
-	AWWRITE4((sc), (reg), AWREAD4((sc), (reg)) | (bits))
-#define AWCLR4(sc, reg, bits)						\
-	AWWRITE4((sc), (reg), AWREAD4((sc), (reg)) & ~(bits))
-#define	AWCMS4(sc, reg, mask, bits)					\
-	AWWRITE4((sc), (reg), (AWREAD4((sc), (reg)) & ~(mask)) | (bits))
+#define SXISET4(sc, reg, bits)						\
+	SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) | (bits))
+#define SXICLR4(sc, reg, bits)						\
+	SXIWRITE4((sc), (reg), SXIREAD4((sc), (reg)) & ~(bits))
+#define	SXICMS4(sc, reg, mask, bits)					\
+	SXIWRITE4((sc), (reg), (SXIREAD4((sc), (reg)) & ~(mask)) | (bits))
 
 
 /* Physical memory range for on-chip devices. */
@@ -47,15 +47,15 @@ struct sxi_mem {
 	bus_size_t size;		/* size of range in bytes */
 };
 
-#define AW_DEV_NMEM 4			/* max number of memory ranges */
-#define AW_DEV_NIRQ 4			/* max number of IRQs per device */
+#define SXI_DEV_NMEM 4			/* max number of memory ranges */
+#define SXI_DEV_NIRQ 4			/* max number of IRQs per device */
 
 /* Descriptor for all on-chip devices. */
 struct sxi_dev {
 	char *name;			/* driver name or made up name */
 	int unit;			/* driver instance number or -1 */
-	struct sxi_mem mem[AW_DEV_NMEM]; /* memory ranges */
-	int irq[AW_DEV_NIRQ];		/* IRQ number(s) */
+	struct sxi_mem mem[SXI_DEV_NMEM]; /* memory ranges */
+	int irq[SXI_DEV_NIRQ];		/* IRQ number(s) */
 };
 
 /* Passed as third arg to attach functions. */
diff --git a/sys/arch/armv7/sunxi/sxiahci.c b/sys/arch/armv7/sunxi/sxiahci.c
index d3d484ed8ff..1f5146e9d29 100644
--- a/sys/arch/armv7/sunxi/sxiahci.c
+++ b/sys/arch/armv7/sunxi/sxiahci.c
@@ -32,16 +32,16 @@
 #include <armv7/sunxi/sxiccmuvar.h>
 #include <armv7/sunxi/sxipiovar.h>
 
-#define	AWAHCI_CAP	0x0000
-#define	AWAHCI_GHC	0x0004
-#define	AWAHCI_PI	0x000c
-#define	AWAHCI_PHYCS0	0x00c0
-#define	AWAHCI_PHYCS1	0x00c4
-#define	AWAHCI_PHYCS2	0x00c8
-#define	AWAHCI_TIMER1MS	0x00e0
-#define	AWAHCI_RWC	0x00fc
-#define	AWAHCI_TIMEOUT	0x100000
-#define AWAHCI_PWRPIN	40
+#define	SXIAHCI_CAP	0x0000
+#define	SXIAHCI_GHC	0x0004
+#define	SXIAHCI_PI	0x000c
+#define	SXIAHCI_PHYCS0	0x00c0
+#define	SXIAHCI_PHYCS1	0x00c4
+#define	SXIAHCI_PHYCS2	0x00c8
+#define	SXIAHCI_TIMER1MS	0x00e0
+#define	SXIAHCI_RWC	0x00fc
+#define	SXIAHCI_TIMEOUT	0x100000
+#define SXIAHCI_PWRPIN	40
 
 void	sxiahci_attach(struct device *, struct device *, void *);
 int	sxiahci_detach(struct device *, int);
@@ -92,57 +92,57 @@ sxiahci_attach(struct device *parent, struct device *self, void *args)
 	delay(5000);
 
 	/* XXX setup magix */
-	AWWRITE4(sc, AWAHCI_RWC, 0);
+	SXIWRITE4(sc, SXIAHCI_RWC, 0);
 	delay(10);
 
-	AWSET4(sc, AWAHCI_PHYCS1, 1 << 19);
+	SXISET4(sc, SXIAHCI_PHYCS1, 1 << 19);
 	delay(10);
 
-	AWCMS4(sc, AWAHCI_PHYCS0, 1 << 25,
+	SXICMS4(sc, SXIAHCI_PHYCS0, 1 << 25,
 	    1 << 23 | 1 << 24 | 1 << 18 | 1 << 26);
 	delay(10);
 
-	AWCMS4(sc, AWAHCI_PHYCS1,
+	SXICMS4(sc, SXIAHCI_PHYCS1,
 	    1 << 16 | 1 << 12 | 1 << 11 | 1 << 8 | 1 << 6,
 	    1 << 17 | 1 << 10 | 1 << 9 | 1 << 7);
 	delay(10);
 
-	AWSET4(sc, AWAHCI_PHYCS1, 1 << 28 | 1 << 15); 
+	SXISET4(sc, SXIAHCI_PHYCS1, 1 << 28 | 1 << 15); 
 	delay(10);
 
-	AWCLR4(sc, AWAHCI_PHYCS1, 1 << 19); 
+	SXICLR4(sc, SXIAHCI_PHYCS1, 1 << 19); 
 	delay(10);
 
-	AWCMS4(sc, AWAHCI_PHYCS0, 1 << 21 | 1 << 20, 1 << 22);
+	SXICMS4(sc, SXIAHCI_PHYCS0, 1 << 21 | 1 << 20, 1 << 22);
 	delay(10);
 
-	AWCMS4(sc, AWAHCI_PHYCS2, 1 << 7 | 1 << 6,
+	SXICMS4(sc, SXIAHCI_PHYCS2, 1 << 7 | 1 << 6,
 	    1 << 9 | 1 << 8 | 1 << 5);
 	delay(5000);
 
-	AWSET4(sc, AWAHCI_PHYCS0, 1 << 19);
+	SXISET4(sc, SXIAHCI_PHYCS0, 1 << 19);
 	delay(20);
 
-	timo = AWAHCI_TIMEOUT;
-	while ((AWREAD4(sc, AWAHCI_PHYCS0) >> 28 & 3) != 2 && --timo)
+	timo = SXIAHCI_TIMEOUT;
+	while ((SXIREAD4(sc, SXIAHCI_PHYCS0) >> 28 & 3) != 2 && --timo)
 		delay(10);
 	if (!timo)
 		printf("sxiahci_attach: AHCI phy power up failed.\n");
 
-	AWSET4(sc, AWAHCI_PHYCS2, 1 << 24);
+	SXISET4(sc, SXIAHCI_PHYCS2, 1 << 24);
 
-	timo = AWAHCI_TIMEOUT;
-	while ((AWREAD4(sc, AWAHCI_PHYCS2) & (1 << 24)) && --timo)
+	timo = SXIAHCI_TIMEOUT;
+	while ((SXIREAD4(sc, SXIAHCI_PHYCS2) & (1 << 24)) && --timo)
 		delay(10);
 	if (!timo)
 		printf("sxiahci_attach: AHCI phy calibration failed.\n");
 
 	delay(15000);
-	AWWRITE4(sc, AWAHCI_RWC, 7);
+	SXIWRITE4(sc, SXIAHCI_RWC, 7);
 
 	/* power up phy */
-	sxipio_setcfg(AWAHCI_PWRPIN, AWPIO_OUTPUT);
-	sxipio_setpin(AWAHCI_PWRPIN);
+	sxipio_setcfg(SXIAHCI_PWRPIN, SXIPIO_OUTPUT);
+	sxipio_setpin(SXIAHCI_PWRPIN);
 
 	sc->sc_ih = arm_intr_establish(sxi->sxi_dev->irq[0], IPL_BIO,
 	    ahci_intr, sc, sc->sc_dev.dv_xname);
@@ -151,8 +151,8 @@ sxiahci_attach(struct device *parent, struct device *self, void *args)
 		goto unmap;
 	}
 
-	AWWRITE4(sc, AWAHCI_PI, 1);
-	AWCLR4(sc, AWAHCI_CAP, AHCI_REG_CAP_SPM);
+	SXIWRITE4(sc, SXIAHCI_PI, 1);
+	SXICLR4(sc, SXIAHCI_CAP, AHCI_REG_CAP_SPM);
 	sc->sc_flags |= AHCI_F_NO_PMP; /* XXX enough? */
 	if (ahci_attach(sc) != 0) {
 		/* error printed by ahci_attach */
diff --git a/sys/arch/armv7/sunxi/sxiccmu.c b/sys/arch/armv7/sunxi/sxiccmu.c
index 22cae699c27..7b44f412c06 100644
--- a/sys/arch/armv7/sunxi/sxiccmu.c
+++ b/sys/arch/armv7/sunxi/sxiccmu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiccmu.c,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sxiccmu.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -132,35 +132,35 @@ sxiccmu_enablemodule(int mod)
 
 	switch (mod) {
 	case CCMU_EHCI0:
-		AWSET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI0);
-		AWSET4(sc, CCMU_USB_CLK, CCMU_USB1_RESET | CCMU_USB_PHY);
+		SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI0);
+		SXISET4(sc, CCMU_USB_CLK, CCMU_USB1_RESET | CCMU_USB_PHY);
 		break;
 	case CCMU_EHCI1:
-		AWSET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI1);
-		AWSET4(sc, CCMU_USB_CLK, CCMU_USB2_RESET | CCMU_USB_PHY);
+		SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EHCI1);
+		SXISET4(sc, CCMU_USB_CLK, CCMU_USB2_RESET | CCMU_USB_PHY);
 		break;
 	case CCMU_OHCI:
 		panic("sxiccmu_enablemodule: XXX OHCI!");
 		break;
 	case CCMU_AHCI:
-		reg = AWREAD4(sc, CCMU_PLL6_CFG);
+		reg = SXIREAD4(sc, CCMU_PLL6_CFG);
 		reg &= ~(CCMU_PLL6_BYPASS_EN | CCMU_PLL6_FACTOR_M |
 		    CCMU_PLL6_FACTOR_N);
 		reg |= CCMU_PLL6_EN | CCMU_PLL6_SATA_CLK_EN;
 		reg |= 25 << 8;
 		reg |= (reg >> 4 & 3);
-		AWWRITE4(sc, CCMU_PLL6_CFG, reg);
+		SXIWRITE4(sc, CCMU_PLL6_CFG, reg);
 
-		AWSET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_SATA);
+		SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_SATA);
 		delay(1000);
 
-		AWWRITE4(sc, CCMU_SATA_CLK, CCMU_SCLK_GATING);
+		SXIWRITE4(sc, CCMU_SATA_CLK, CCMU_SCLK_GATING);
 		break;
 	case CCMU_EMAC:
-		AWSET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EMAC);
+		SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_EMAC);
 		break;
 	case CCMU_DMA:
-		AWSET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_DMA);
+		SXISET4(sc, CCMU_AHB_GATING0, CCMU_AHB_GATING_DMA);
 		break;
 	case CCMU_UART0:
 	case CCMU_UART1:
@@ -170,7 +170,7 @@ sxiccmu_enablemodule(int mod)
 	case CCMU_UART5:
 	case CCMU_UART6:
 	case CCMU_UART7:
-		AWSET4(sc, CCMU_APB_GATING1, CCMU_APB_GATING_UARTx(mod - CCMU_UART0));
+		SXISET4(sc, CCMU_APB_GATING1, CCMU_APB_GATING_UARTx(mod - CCMU_UART0));
 		break;
 	default:
 		break;
diff --git a/sys/arch/armv7/sunxi/sxidog.c b/sys/arch/armv7/sunxi/sxidog.c
index 136865a974e..f791c875caa 100644
--- a/sys/arch/armv7/sunxi/sxidog.c
+++ b/sys/arch/armv7/sunxi/sxidog.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: sxidog.c,v 1.1 2013/10/23 17:08:48 jasper Exp $ */
+/* $OpenBSD: sxidog.c,v 1.2 2013/10/23 18:01:52 jasper Exp $ */
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  *
@@ -91,8 +91,8 @@ sxidog_attach(struct device *parent, struct device *self, void *args)
 		panic("sxidog_attach: bus_space_subregion failed!");
 
 #ifdef DEBUG
-	printf(": ctrl %x mode %x\n", AWREAD4(sc, WDOG_CR),
-	    AWREAD4(sc, WDOG_MR));
+	printf(": ctrl %x mode %x\n", SXIREAD4(sc, WDOG_CR),
+	    SXIREAD4(sc, WDOG_MR));
 #endif
 #if 0
 	(void)intc_intr_establish(sxi->sxi_dev->irq[0], IPL_HIGH, /* XXX */
@@ -119,10 +119,10 @@ sxidog_callback(void *arg, int period)
 	 * to the user manual, so just set new timeout and enable it.
 	 * XXX 
 	 */
-	AWWRITE4(sc, WDOG_MR, WDOG_EN | WDOG_RST_EN |
+	SXIWRITE4(sc, WDOG_MR, WDOG_EN | WDOG_RST_EN |
 	    WDOG_INTV_VALUE(period));
 	/* reset */
-	AWWRITE4(sc, WDOG_CR, WDOG_CTRL_KEY | WDOG_RESTART);
+	SXIWRITE4(sc, WDOG_CR, WDOG_CTRL_KEY | WDOG_RESTART);
 	
 	return period;
 }
@@ -134,7 +134,7 @@ sxidog_intr(void *arg)
 	struct sxidog_softc *sc = (struct sxidog_softc *)arg;
 
 	/* XXX */
-	AWWRITE4(sc, WDOG_CR, WDOG_CTRL_KEY | WDOG_RESTART);
+	SXIWRITE4(sc, WDOG_CR, WDOG_CTRL_KEY | WDOG_RESTART);
 	return 1;
 }
 #endif
@@ -145,8 +145,8 @@ sxidog_reset(void)
 	if (sxidog_sc == NULL)
 		return;
 
-	AWWRITE4(sxidog_sc, WDOG_MR, WDOG_INTV_VALUE(0x00) |
+	SXIWRITE4(sxidog_sc, WDOG_MR, WDOG_INTV_VALUE(0x00) |
 	    WDOG_RST_EN | WDOG_EN);
-	AWWRITE4(sxidog_sc, WDOG_CR, WDOG_CTRL_KEY | WDOG_RESTART);
+	SXIWRITE4(sxidog_sc, WDOG_CR, WDOG_CTRL_KEY | WDOG_RESTART);
 	delay(900000);
 }
diff --git a/sys/arch/armv7/sunxi/sxie.c b/sys/arch/armv7/sunxi/sxie.c
index a5eeabf4e1c..830e0e17c4f 100644
--- a/sys/arch/armv7/sunxi/sxie.c
+++ b/sys/arch/armv7/sunxi/sxie.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxie.c,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sxie.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  * Copyright (c) 2013 Artturi Alm
@@ -56,102 +56,102 @@
 #include <armv7/sunxi/sxipiovar.h>
 
 /* configuration registers */
-#define	AWE_CR			0x0000
-#define	AWE_TXMODE		0x0004
-#define	AWE_TXFLOW		0x0008
-#define	AWE_TXCR0		0x000c
-#define	AWE_TXCR1		0x0010
-#define	AWE_TXINS		0x0014
-#define	AWE_TXPKTLEN0		0x0018
-#define	AWE_TXPKTLEN1		0x001c
-#define	AWE_TXSR		0x0020
-#define	AWE_TXIO0		0x0024
-#define	AWE_TXIO1		0x0028
-#define	AWE_TXTSVL0		0x002c
-#define	AWE_TXTSVH0		0x0030
-#define	AWE_TXTSVL1		0x0034
-#define	AWE_TXTSVH1		0x0038
-#define	AWE_RXCR		0x003c
-#define	AWE_RXHASH0		0x0040
-#define	AWE_RXHASH1		0x0044
-#define	AWE_RXSR		0x0048
-#define	AWE_RXIO		0x004C
-#define	AWE_RXFBC		0x0050
-#define	AWE_INTCR		0x0054
-#define	AWE_INTSR		0x0058
-#define	AWE_MACCR0		0x005C
-#define	AWE_MACCR1		0x0060
-#define	AWE_MACIPGT		0x0064
-#define	AWE_MACIPGR		0x0068
-#define	AWE_MACCLRT		0x006C
-#define	AWE_MACMFL		0x0070
-#define	AWE_MACSUPP		0x0074
-#define	AWE_MACTEST		0x0078
-#define	AWE_MACMCFG		0x007C
-#define	AWE_MACMCMD		0x0080
-#define	AWE_MACMADR		0x0084
-#define	AWE_MACMWTD		0x0088
-#define	AWE_MACMRDD		0x008C
-#define	AWE_MACMIND		0x0090
-#define	AWE_MACSSRR		0x0094
-#define	AWE_MACA0		0x0098
-#define	AWE_MACA1		0x009c
-#define	AWE_MACA2		0x00a0
+#define	SXIE_CR			0x0000
+#define	SXIE_TXMODE		0x0004
+#define	SXIE_TXFLOW		0x0008
+#define	SXIE_TXCR0		0x000c
+#define	SXIE_TXCR1		0x0010
+#define	SXIE_TXINS		0x0014
+#define	SXIE_TXPKTLEN0		0x0018
+#define	SXIE_TXPKTLEN1		0x001c
+#define	SXIE_TXSR		0x0020
+#define	SXIE_TXIO0		0x0024
+#define	SXIE_TXIO1		0x0028
+#define	SXIE_TXTSVL0		0x002c
+#define	SXIE_TXTSVH0		0x0030
+#define	SXIE_TXTSVL1		0x0034
+#define	SXIE_TXTSVH1		0x0038
+#define	SXIE_RXCR		0x003c
+#define	SXIE_RXHASH0		0x0040
+#define	SXIE_RXHASH1		0x0044
+#define	SXIE_RXSR		0x0048
+#define	SXIE_RXIO		0x004C
+#define	SXIE_RXFBC		0x0050
+#define	SXIE_INTCR		0x0054
+#define	SXIE_INTSR		0x0058
+#define	SXIE_MACCR0		0x005C
+#define	SXIE_MACCR1		0x0060
+#define	SXIE_MACIPGT		0x0064
+#define	SXIE_MACIPGR		0x0068
+#define	SXIE_MACCLRT		0x006C
+#define	SXIE_MACMFL		0x0070
+#define	SXIE_MACSUPP		0x0074
+#define	SXIE_MACTEST		0x0078
+#define	SXIE_MACMCFG		0x007C
+#define	SXIE_MACMCMD		0x0080
+#define	SXIE_MACMADR		0x0084
+#define	SXIE_MACMWTD		0x0088
+#define	SXIE_MACMRDD		0x008C
+#define	SXIE_MACMIND		0x0090
+#define	SXIE_MACSSRR		0x0094
+#define	SXIE_MACA0		0x0098
+#define	SXIE_MACA1		0x009c
+#define	SXIE_MACA2		0x00a0
 
 /* i once spent hours on pretty defines, cvs up ate 'em. these shall do */
-#define AWE_INTR_ENABLE		0x010f
-#define AWE_INTR_DISABLE	0x0000
-#define AWE_INTR_CLEAR		0x0000
-
-#define	AWE_RX_ENABLE		0x0004
-#define	AWE_TX_ENABLE		0x0003
-#define	AWE_RXTX_ENABLE		0x0007
-
-#define	AWE_RXDRQM		0x0002
-#define	AWE_RXTM		0x0004
-#define	AWE_RXFLUSH		0x0008
-#define	AWE_RXPA		0x0010
-#define	AWE_RXPCF		0x0020
-#define	AWE_RXPCRCE		0x0040
-#define	AWE_RXPLE		0x0080
-#define	AWE_RXPOR		0x0100
-#define	AWE_RXUCAD		0x10000
-#define	AWE_RXDAF		0x20000
-#define	AWE_RXMCO		0x100000
-#define	AWE_RXMHF		0x200000
-#define	AWE_RXBCO		0x400000
-#define	AWE_RXSAF		0x1000000
-#define	AWE_RXSAIF		0x2000000
-
-#define	AWE_MACRXFC		0x0004
-#define	AWE_MACTXFC		0x0008
-#define AWE_MACSOFTRESET	0x8000
-
-#define	AWE_MACDUPLEX		0x0001	/* full = 1 */
-#define	AWE_MACFLC		0x0002
-#define	AWE_MACHF		0x0004
-#define	AWE_MACDCRC		0x0008
-#define	AWE_MACCRC		0x0010
-#define	AWE_MACPC		0x0020
-#define	AWE_MACVC		0x0040
-#define	AWE_MACADP		0x0080
-#define	AWE_MACPRE		0x0100
-#define	AWE_MACLPE		0x0200
-#define	AWE_MACNB		0x1000
-#define	AWE_MACBNB		0x2000
-#define	AWE_MACED		0x4000
-
-#define	AWE_RX_ERRLENOOR	0x0040
-#define	AWE_RX_ERRLENCHK	0x0020
-#define	AWE_RX_ERRCRC		0x0010
-#define	AWE_RX_ERRRCV		0x0008 /* XXX receive code violation ? */
-#define	AWE_RX_ERRMASK		0x0070
-
-#define	AWE_MII_TIMEOUT	100
-#define AWE_MAX_RXD		8
-#define AWE_MAX_PKT_SIZE	ETHER_MAX_DIX_LEN
-
-#define AWE_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
+#define SXIE_INTR_ENABLE		0x010f
+#define SXIE_INTR_DISABLE	0x0000
+#define SXIE_INTR_CLEAR		0x0000
+
+#define	SXIE_RX_ENABLE		0x0004
+#define	SXIE_TX_ENABLE		0x0003
+#define	SXIE_RXTX_ENABLE		0x0007
+
+#define	SXIE_RXDRQM		0x0002
+#define	SXIE_RXTM		0x0004
+#define	SXIE_RXFLUSH		0x0008
+#define	SXIE_RXPA		0x0010
+#define	SXIE_RXPCF		0x0020
+#define	SXIE_RXPCRCE		0x0040
+#define	SXIE_RXPLE		0x0080
+#define	SXIE_RXPOR		0x0100
+#define	SXIE_RXUCAD		0x10000
+#define	SXIE_RXDAF		0x20000
+#define	SXIE_RXMCO		0x100000
+#define	SXIE_RXMHF		0x200000
+#define	SXIE_RXBCO		0x400000
+#define	SXIE_RXSAF		0x1000000
+#define	SXIE_RXSAIF		0x2000000
+
+#define	SXIE_MACRXFC		0x0004
+#define	SXIE_MACTXFC		0x0008
+#define SXIE_MACSOFTRESET	0x8000
+
+#define	SXIE_MACDUPLEX		0x0001	/* full = 1 */
+#define	SXIE_MACFLC		0x0002
+#define	SXIE_MACHF		0x0004
+#define	SXIE_MACDCRC		0x0008
+#define	SXIE_MACCRC		0x0010
+#define	SXIE_MACPC		0x0020
+#define	SXIE_MACVC		0x0040
+#define	SXIE_MACADP		0x0080
+#define	SXIE_MACPRE		0x0100
+#define	SXIE_MACLPE		0x0200
+#define	SXIE_MACNB		0x1000
+#define	SXIE_MACBNB		0x2000
+#define	SXIE_MACED		0x4000
+
+#define	SXIE_RX_ERRLENOOR	0x0040
+#define	SXIE_RX_ERRLENCHK	0x0020
+#define	SXIE_RX_ERRCRC		0x0010
+#define	SXIE_RX_ERRRCV		0x0008 /* XXX receive code violation ? */
+#define	SXIE_RX_ERRMASK		0x0070
+
+#define	SXIE_MII_TIMEOUT	100
+#define SXIE_MAX_RXD		8
+#define SXIE_MAX_PKT_SIZE	ETHER_MAX_DIX_LEN
+
+#define SXIE_ROUNDUP(size, unit) (((size) + (unit) - 1) & ~((unit) - 1))
 
 struct sxie_softc {
 	struct device			sc_dev;
@@ -266,23 +266,23 @@ sxie_socware_init(struct sxie_softc *sc)
 	int i;
 	uint32_t reg;
 
-	for (i = 0; i < AWPIO_EMAC_NPINS; i++)
+	for (i = 0; i < SXIPIO_EMAC_NPINS; i++)
 		sxipio_setcfg(i, 2); /* mux pins to EMAC */
 	sxiccmu_enablemodule(CCMU_EMAC);
 
 	/* MII clock cfg */
-	AWCMS4(sc, AWE_MACMCFG, 15 << 2, 13 << 2);
+	SXICMS4(sc, SXIE_MACMCFG, 15 << 2, 13 << 2);
 
-	AWWRITE4(sc, AWE_INTCR, AWE_INTR_DISABLE);
-	AWSET4(sc, AWE_INTSR, AWE_INTR_CLEAR);
+	SXIWRITE4(sc, SXIE_INTCR, SXIE_INTR_DISABLE);
+	SXISET4(sc, SXIE_INTSR, SXIE_INTR_CLEAR);
 
 #if 1
 	/* set lladdr with values set in u-boot */
-	reg = AWREAD4(sc, AWE_MACA0);
+	reg = SXIREAD4(sc, SXIE_MACA0);
 	sc->sc_ac.ac_enaddr[3] = reg >> 16 & 0xff;
 	sc->sc_ac.ac_enaddr[4] = reg >> 8 & 0xff;
 	sc->sc_ac.ac_enaddr[5] = reg & 0xff;
-	reg = AWREAD4(sc, AWE_MACA1);
+	reg = SXIREAD4(sc, SXIE_MACA1);
 	sc->sc_ac.ac_enaddr[0] = reg >> 16 & 0xff;
 	sc->sc_ac.ac_enaddr[1] = reg >> 8 & 0xff;
 	sc->sc_ac.ac_enaddr[2] = reg & 0xff;
@@ -303,40 +303,40 @@ sxie_setup_interface(struct sxie_softc *sc, struct device *dev)
 	uint32_t clr_m, set_m;
 
 	/* configure TX */
-	AWCMS4(sc, AWE_TXMODE, 3, 1);	/* cpu mode */
+	SXICMS4(sc, SXIE_TXMODE, 3, 1);	/* cpu mode */
 
 	/* configure RX */
-	clr_m = AWE_RXDRQM | AWE_RXTM | AWE_RXPA | AWE_RXPCF |
-	    AWE_RXPCRCE | AWE_RXPLE | AWE_RXMHF | AWE_RXSAF |
-	    AWE_RXSAIF;
-	set_m = AWE_RXPOR | AWE_RXUCAD | AWE_RXDAF | AWE_RXBCO;
-	AWCMS4(sc, AWE_RXCR, clr_m, set_m);
+	clr_m = SXIE_RXDRQM | SXIE_RXTM | SXIE_RXPA | SXIE_RXPCF |
+	    SXIE_RXPCRCE | SXIE_RXPLE | SXIE_RXMHF | SXIE_RXSAF |
+	    SXIE_RXSAIF;
+	set_m = SXIE_RXPOR | SXIE_RXUCAD | SXIE_RXDAF | SXIE_RXBCO;
+	SXICMS4(sc, SXIE_RXCR, clr_m, set_m);
 
 	/* configure MAC */
-	AWSET4(sc, AWE_MACCR0, AWE_MACTXFC | AWE_MACRXFC);
-	clr_m =	AWE_MACHF | AWE_MACDCRC | AWE_MACVC | AWE_MACADP |
-	    AWE_MACPRE | AWE_MACLPE | AWE_MACNB | AWE_MACBNB |
-	    AWE_MACED;
-	set_m = AWE_MACFLC | AWE_MACCRC | AWE_MACPC;
+	SXISET4(sc, SXIE_MACCR0, SXIE_MACTXFC | SXIE_MACRXFC);
+	clr_m =	SXIE_MACHF | SXIE_MACDCRC | SXIE_MACVC | SXIE_MACADP |
+	    SXIE_MACPRE | SXIE_MACLPE | SXIE_MACNB | SXIE_MACBNB |
+	    SXIE_MACED;
+	set_m = SXIE_MACFLC | SXIE_MACCRC | SXIE_MACPC;
 	set_m |= sxie_miibus_readreg(dev, sc->sc_phyno, 0) >> 8 & 1;
-	AWCMS4(sc, AWE_MACCR1, clr_m, set_m);
+	SXICMS4(sc, SXIE_MACCR1, clr_m, set_m);
 
 	/* XXX */
-	AWWRITE4(sc, AWE_MACIPGT, 0x0015);
-	AWWRITE4(sc, AWE_MACIPGR, 0x0c12);
+	SXIWRITE4(sc, SXIE_MACIPGT, 0x0015);
+	SXIWRITE4(sc, SXIE_MACIPGR, 0x0c12);
 
 	/* XXX set collision window */
-	AWWRITE4(sc, AWE_MACCLRT, 0x370f);
+	SXIWRITE4(sc, SXIE_MACCLRT, 0x370f);
 
 	/* set max frame length */
-	AWWRITE4(sc, AWE_MACMFL, AWE_MAX_PKT_SIZE);
+	SXIWRITE4(sc, SXIE_MACMFL, SXIE_MAX_PKT_SIZE);
 
 	/* set lladdr */
-	AWWRITE4(sc, AWE_MACA0,
+	SXIWRITE4(sc, SXIE_MACA0,
 	    sc->sc_ac.ac_enaddr[3] << 16 |
 	    sc->sc_ac.ac_enaddr[4] << 8 |
 	    sc->sc_ac.ac_enaddr[5]);
-	AWWRITE4(sc, AWE_MACA1,
+	SXIWRITE4(sc, SXIE_MACA1,
 	    sc->sc_ac.ac_enaddr[0] << 16 |
 	    sc->sc_ac.ac_enaddr[1] << 8 |
 	    sc->sc_ac.ac_enaddr[2]);
@@ -354,17 +354,17 @@ sxie_init(struct sxie_softc *sc)
 	
 	sxie_reset(sc);
 
-	AWWRITE4(sc, AWE_INTCR, AWE_INTR_DISABLE);
+	SXIWRITE4(sc, SXIE_INTCR, SXIE_INTR_DISABLE);
 
-	AWSET4(sc, AWE_INTSR, AWE_INTR_CLEAR);
+	SXISET4(sc, SXIE_INTSR, SXIE_INTR_CLEAR);
 
-	AWSET4(sc, AWE_RXCR, AWE_RXFLUSH);
+	SXISET4(sc, SXIE_RXCR, SXIE_RXFLUSH);
 
 	/* soft reset */
-	AWCLR4(sc, AWE_MACCR0, AWE_MACSOFTRESET);
+	SXICLR4(sc, SXIE_MACCR0, SXIE_MACSOFTRESET);
 
 	/* zero rx counter */
-	AWWRITE4(sc, AWE_RXFBC, 0);
+	SXIWRITE4(sc, SXIE_RXFBC, 0);
 
 	sxie_setup_interface(sc, dev);
 
@@ -375,18 +375,18 @@ sxie_init(struct sxie_softc *sc)
 	phyreg = sxie_miibus_readreg(dev, sc->sc_phyno, 0);
 
 	/* set duplex */
-	AWCMS4(sc, AWE_MACCR1, 1, phyreg >> 8 & 1);
+	SXICMS4(sc, SXIE_MACCR1, 1, phyreg >> 8 & 1);
 
 	/* set speed */
-	AWCMS4(sc, AWE_MACSUPP, 1 << 8, (phyreg >> 13 & 1) << 8);
+	SXICMS4(sc, SXIE_MACSUPP, 1 << 8, (phyreg >> 13 & 1) << 8);
 
-	AWSET4(sc, AWE_CR, AWE_RXTX_ENABLE);
+	SXISET4(sc, SXIE_CR, SXIE_RXTX_ENABLE);
 
 	/* Indicate we are up and running. */
 	ifp->if_flags |= IFF_RUNNING;
 	ifp->if_flags &= ~IFF_OACTIVE;
 
-	AWSET4(sc, AWE_INTCR, AWE_INTR_ENABLE);
+	SXISET4(sc, SXIE_INTCR, SXIE_INTR_ENABLE);
 
 	sxie_start(ifp);
 }
@@ -398,10 +398,10 @@ sxie_intr(void *arg)
 	struct ifnet *ifp = &sc->sc_ac.ac_if;
 	uint32_t pending;
 
-	AWWRITE4(sc, AWE_INTCR, AWE_INTR_DISABLE);
+	SXIWRITE4(sc, SXIE_INTCR, SXIE_INTR_DISABLE);
 
-	pending = AWREAD4(sc, AWE_INTSR);
-	AWWRITE4(sc, AWE_INTSR, pending);
+	pending = SXIREAD4(sc, SXIE_INTSR);
+	SXIWRITE4(sc, SXIE_INTSR, pending);
 
 	/*
 	 * Handle incoming packets.
@@ -430,7 +430,7 @@ sxie_intr(void *arg)
 	if (ifp->if_flags & IFF_RUNNING && !IFQ_IS_EMPTY(&ifp->if_snd))
 		sxie_start(ifp);
 
-	AWSET4(sc, AWE_INTCR, AWE_INTR_ENABLE);
+	SXISET4(sc, SXIE_INTCR, SXIE_INTR_ENABLE);
 
 	return 1;
 }
@@ -446,7 +446,7 @@ sxie_start(struct ifnet *ifp)
 	struct mbuf *head;
 	uint8_t *td;
 	uint32_t fifo;
-	uint32_t txbuf[AWE_MAX_PKT_SIZE / sizeof(uint32_t)]; /* XXX !!! */
+	uint32_t txbuf[SXIE_MAX_PKT_SIZE / sizeof(uint32_t)]; /* XXX !!! */
 
 	if (sc->txf_inuse > 1)
 		ifp->if_flags |= IFF_OACTIVE;
@@ -462,7 +462,7 @@ trynext:
 	if (m == NULL)
 		return;
 
-	if (m->m_pkthdr.len > AWE_MAX_PKT_SIZE) {
+	if (m->m_pkthdr.len > SXIE_MAX_PKT_SIZE) {
 		printf("sxie_start: packet too big\n");
 		m_freem(m);
 		return;
@@ -476,21 +476,21 @@ trynext:
 
 	/* select fifo */
 	fifo = sc->txf_inuse;
-	AWWRITE4(sc, AWE_TXINS, fifo);
+	SXIWRITE4(sc, SXIE_TXINS, fifo);
 
 	sc->txf_inuse++;
 
 	/* set packet length */
-	AWWRITE4(sc, AWE_TXPKTLEN0 + (fifo * 4), m->m_pkthdr.len);
+	SXIWRITE4(sc, SXIE_TXPKTLEN0 + (fifo * 4), m->m_pkthdr.len);
 
 	/* copy the actual packet to fifo XXX through 'align buffer'.. */
 	m_copydata(m, 0, m->m_pkthdr.len, (caddr_t)td);
 	bus_space_write_multi_4(sc->sc_iot, sc->sc_ioh,
-	    AWE_TXIO0 + (fifo * 4),
-	    (uint32_t *)td, AWE_ROUNDUP(m->m_pkthdr.len, 4) >> 2);
+	    SXIE_TXIO0 + (fifo * 4),
+	    (uint32_t *)td, SXIE_ROUNDUP(m->m_pkthdr.len, 4) >> 2);
 
 	/* transmit to PHY from fifo */
-	AWSET4(sc, AWE_TXCR0 + (fifo * 4), 1);
+	SXISET4(sc, SXIE_TXCR0 + (fifo * 4), 1);
 	ifp->if_timer = 5;
 	IFQ_DEQUEUE(&ifp->if_snd, m);
 
@@ -518,9 +518,9 @@ void
 sxie_reset(struct sxie_softc *sc)
 {
 	/* reset the controller */
-	AWWRITE4(sc, AWE_CR, 0);
+	SXIWRITE4(sc, SXIE_CR, 0);
 	delay(200);
-	AWWRITE4(sc, AWE_CR, 1);
+	SXIWRITE4(sc, SXIE_CR, 1);
 	delay(200);
 }
 
@@ -550,9 +550,9 @@ sxie_recv(struct sxie_softc *sc)
 	uint16_t pktstat;
 	int16_t pktlen;
 	int rlen;
-	char rxbuf[AWE_MAX_PKT_SIZE]; /* XXX !!! */
+	char rxbuf[SXIE_MAX_PKT_SIZE]; /* XXX !!! */
 trynext:
-	fbc = AWREAD4(sc, AWE_RXFBC);
+	fbc = SXIREAD4(sc, SXIE_RXFBC);
 	if (!fbc)
 		return;
 
@@ -560,13 +560,13 @@ trynext:
 	 * first bit of MSB is packet valid flag,
 	 * it is 'padded' with 0x43414d = "MAC"
 	 */
-	reg = AWREAD4(sc, AWE_RXIO);
+	reg = SXIREAD4(sc, SXIE_RXIO);
 	if (reg != 0x0143414d) {	/* invalid packet */
 		/* disable, flush, enable */
-		AWCLR4(sc, AWE_CR, AWE_RX_ENABLE);
-		AWSET4(sc, AWE_RXCR, AWE_RXFLUSH);
-		while (AWREAD4(sc, AWE_RXCR) & AWE_RXFLUSH);
-		AWSET4(sc, AWE_CR, AWE_RX_ENABLE);
+		SXICLR4(sc, SXIE_CR, SXIE_RX_ENABLE);
+		SXISET4(sc, SXIE_RXCR, SXIE_RXFLUSH);
+		while (SXIREAD4(sc, SXIE_RXCR) & SXIE_RXFLUSH);
+		SXISET4(sc, SXIE_CR, SXIE_RX_ENABLE);
 
 		goto err_out;
 	}
@@ -575,16 +575,16 @@ trynext:
 	if (m == NULL)
 		goto err_out;
 
-	reg = AWREAD4(sc, AWE_RXIO);
+	reg = SXIREAD4(sc, SXIE_RXIO);
 	pktstat = (uint16_t)reg >> 16;
 	pktlen = (int16_t)reg; /* length of useful data */
 
-	if (pktstat & AWE_RX_ERRMASK || pktlen < ETHER_MIN_LEN) {
+	if (pktstat & SXIE_RX_ERRMASK || pktlen < ETHER_MIN_LEN) {
 		ifp->if_ierrors++;
 		goto trynext;
 	}
-	if (pktlen > AWE_MAX_PKT_SIZE)
-		pktlen = AWE_MAX_PKT_SIZE; /* XXX is truncating ok? */
+	if (pktlen > SXIE_MAX_PKT_SIZE)
+		pktlen = SXIE_MAX_PKT_SIZE; /* XXX is truncating ok? */
 
 	ifp->if_ipackets++;
 	m->m_pkthdr.rcvif = ifp;
@@ -594,11 +594,11 @@ trynext:
 
 	/* read the actual packet from fifo XXX through 'align buffer'.. */
 	if (pktlen & 3)
-		rlen = AWE_ROUNDUP(pktlen, 4);
+		rlen = SXIE_ROUNDUP(pktlen, 4);
 	else
 		rlen = pktlen;
 	bus_space_read_multi_4(sc->sc_iot, sc->sc_ioh,
-	    AWE_RXIO, (uint32_t *)&rxbuf[0], rlen >> 2);
+	    SXIE_RXIO, (uint32_t *)&rxbuf[0], rlen >> 2);
 	memcpy(mtod(m, char *), (char *)&rxbuf[0], pktlen);
 
 	/* push the packet up */
@@ -690,12 +690,12 @@ int
 sxie_miibus_readreg(struct device *dev, int phy, int reg)
 {
 	struct sxie_softc *sc = (struct sxie_softc *)dev;
-	int timo = AWE_MII_TIMEOUT;
+	int timo = SXIE_MII_TIMEOUT;
 
-	AWWRITE4(sc, AWE_MACMADR, phy << 8 | reg);
+	SXIWRITE4(sc, SXIE_MACMADR, phy << 8 | reg);
 
-	AWWRITE4(sc, AWE_MACMCMD, 1);
-	while (AWREAD4(sc, AWE_MACMIND) & 1 && --timo)
+	SXIWRITE4(sc, SXIE_MACMCMD, 1);
+	while (SXIREAD4(sc, SXIE_MACMIND) & 1 && --timo)
 		delay(10);
 #ifdef DIAGNOSTIC
 	if (!timo)
@@ -703,21 +703,21 @@ sxie_miibus_readreg(struct device *dev, int phy, int reg)
 		    sc->sc_dev.dv_xname);
 #endif
 
-	AWWRITE4(sc, AWE_MACMCMD, 0);
+	SXIWRITE4(sc, SXIE_MACMCMD, 0);
 	
-	return AWREAD4(sc, AWE_MACMRDD) & 0xffff;
+	return SXIREAD4(sc, SXIE_MACMRDD) & 0xffff;
 }
 
 void
 sxie_miibus_writereg(struct device *dev, int phy, int reg, int val)
 {
 	struct sxie_softc *sc = (struct sxie_softc *)dev;
-	int timo = AWE_MII_TIMEOUT;
+	int timo = SXIE_MII_TIMEOUT;
 
-	AWWRITE4(sc, AWE_MACMADR, phy << 8 | reg);
+	SXIWRITE4(sc, SXIE_MACMADR, phy << 8 | reg);
 
-	AWWRITE4(sc, AWE_MACMCMD, 1);
-	while (AWREAD4(sc, AWE_MACMIND) & 1 && --timo)
+	SXIWRITE4(sc, SXIE_MACMCMD, 1);
+	while (SXIREAD4(sc, SXIE_MACMIND) & 1 && --timo)
 		delay(10);
 #ifdef DIAGNOSTIC
 	if (!timo)
@@ -725,9 +725,9 @@ sxie_miibus_writereg(struct device *dev, int phy, int reg, int val)
 		    sc->sc_dev.dv_xname);
 #endif
 
-	AWWRITE4(sc, AWE_MACMCMD, 0);
+	SXIWRITE4(sc, SXIE_MACMCMD, 0);
 
-	AWWRITE4(sc, AWE_MACMWTD, val);
+	SXIWRITE4(sc, SXIE_MACMWTD, val);
 }
 
 void
diff --git a/sys/arch/armv7/sunxi/sxiehci.c b/sys/arch/armv7/sunxi/sxiehci.c
index cd8825392de..80052407581 100644
--- a/sys/arch/armv7/sunxi/sxiehci.c
+++ b/sys/arch/armv7/sunxi/sxiehci.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiehci.c,v 1.1 2013/10/23 17:08:48 jasper Exp $ */
+/*	$OpenBSD: sxiehci.c,v 1.2 2013/10/23 18:01:52 jasper Exp $ */
 
 /*
  * Copyright (c) 2005 David Gwynne <dlg@openbsd.org>
@@ -171,11 +171,11 @@ sxiehci_init(struct sxiehci_softc *sc, int unit)
 	if (unit > 1)
 		panic("sxiehci_init: unit >1 %d", unit);
 	else if (unit == 0) {
-		pin = AWPIO_USB1_PWR;
+		pin = SXIPIO_USB1_PWR;
 		r = SDRAM_REG_HPCR_USB1;
 		mod = CCMU_EHCI0;
 	} else {
-		pin = AWPIO_USB2_PWR;
+		pin = SXIPIO_USB2_PWR;
 		r = SDRAM_REG_HPCR_USB2;
 		mod = CCMU_EHCI1;
 	}
@@ -183,7 +183,7 @@ sxiehci_init(struct sxiehci_softc *sc, int unit)
 	sxiccmu_enablemodule(mod);
 
 	/* power up */
-	sxipio_setcfg(pin, AWPIO_OUTPUT);
+	sxipio_setcfg(pin, SXIPIO_OUTPUT);
 	sxipio_setpin(pin);
 
 	val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, USB_PMU_IRQ_ENABLE);
diff --git a/sys/arch/armv7/sunxi/sxipio.c b/sys/arch/armv7/sunxi/sxipio.c
index 672a6b958f5..66c0dc08301 100644
--- a/sys/arch/armv7/sunxi/sxipio.c
+++ b/sys/arch/armv7/sunxi/sxipio.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxipio.c,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sxipio.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2010 Miodrag Vallat.
  * Copyright (c) 2013 Artturi Alm
@@ -30,20 +30,20 @@
 #include <armv7/sunxi/sunxivar.h>
 #include <armv7/sunxi/sxipiovar.h>
 
-#define	AWPIO_NPORT		9
-#define	AWPIO_PA_NPIN		18
-#define	AWPIO_PB_NPIN		24
-#define	AWPIO_PC_NPIN		25
-#define	AWPIO_PD_NPIN		28
-#define	AWPIO_PE_NPIN		12
-#define	AWPIO_PF_NPIN		6
-#define	AWPIO_PG_NPIN		12
-#define	AWPIO_PH_NPIN		28
-#define	AWPIO_PI_NPIN		22
-#define	AWPIO_NPIN	(AWPIO_PA_NPIN + AWPIO_PB_NPIN + AWPIO_PC_NPIN + \
-	AWPIO_PD_NPIN + AWPIO_PE_NPIN + AWPIO_PF_NPIN + AWPIO_PG_NPIN + \
-	AWPIO_PH_NPIN + AWPIO_PI_NPIN)
-#define	AWPIO_PS_NPIN		84 /* for DRAM controller */
+#define	SXIPIO_NPORT		9
+#define	SXIPIO_PA_NPIN		18
+#define	SXIPIO_PB_NPIN		24
+#define	SXIPIO_PC_NPIN		25
+#define	SXIPIO_PD_NPIN		28
+#define	SXIPIO_PE_NPIN		12
+#define	SXIPIO_PF_NPIN		6
+#define	SXIPIO_PG_NPIN		12
+#define	SXIPIO_PH_NPIN		28
+#define	SXIPIO_PI_NPIN		22
+#define	SXIPIO_NPIN	(SXIPIO_PA_NPIN + SXIPIO_PB_NPIN + SXIPIO_PC_NPIN + \
+	SXIPIO_PD_NPIN + SXIPIO_PE_NPIN + SXIPIO_PF_NPIN + SXIPIO_PG_NPIN + \
+	SXIPIO_PH_NPIN + SXIPIO_PI_NPIN)
+#define	SXIPIO_PS_NPIN		84 /* for DRAM controller */
 
 
 struct intrhand {
@@ -66,21 +66,21 @@ struct sxipio_softc {
 	int 			sc_min_il;
 	int			sc_irq;
 
-	struct gpio_chipset_tag	 sc_gpio_tag[AWPIO_NPORT];
-	gpio_pin_t		 sc_gpio_pins[AWPIO_NPORT][32];
+	struct gpio_chipset_tag	 sc_gpio_tag[SXIPIO_NPORT];
+	gpio_pin_t		 sc_gpio_pins[SXIPIO_NPORT][32];
 
 	struct intrhand		*sc_handlers[32];
 };
 
-#define	AWPIO_CFG(port, pin)	0x00 + ((port) * 0x24) + ((pin) << 2)
-#define	AWPIO_DAT(port)		0x10 + ((port) * 0x24)
+#define	SXIPIO_CFG(port, pin)	0x00 + ((port) * 0x24) + ((pin) << 2)
+#define	SXIPIO_DAT(port)		0x10 + ((port) * 0x24)
 /* XXX add support for registers below */
-#define	AWPIO_DRV(port, pin)	0x14 + ((port) * 0x24) + ((pin) << 2)
-#define	AWPIO_PUL(port, pin)	0x1c + ((port) * 0x24) + ((pin) << 2)
-#define	AWPIO_INT_CFG0(port)	0x0200 + ((port) * 0x04)
-#define	AWPIO_INT_CTL		0x0210
-#define	AWPIO_INT_STA		0x0214
-#define	AWPIO_INT_DEB		0x0218 /* debounce register */
+#define	SXIPIO_DRV(port, pin)	0x14 + ((port) * 0x24) + ((pin) << 2)
+#define	SXIPIO_PUL(port, pin)	0x1c + ((port) * 0x24) + ((pin) << 2)
+#define	SXIPIO_INT_CFG0(port)	0x0200 + ((port) * 0x04)
+#define	SXIPIO_INT_CTL		0x0210
+#define	SXIPIO_INT_STA		0x0214
+#define	SXIPIO_INT_DEB		0x0218 /* debounce register */
 
 void sxipio_attach(struct device *, struct device *, void *);
 void sxipio_attach_gpio(struct device *);
@@ -114,10 +114,10 @@ sxipio_attach(struct device *parent, struct device *self, void *args)
 	sxipio_sc = sc;
 
 	sc->sc_irq = sxi->sxi_dev->irq[0];
-	sxipio_setcfg(AWPIO_LED_GREEN, AWPIO_OUTPUT);
-	sxipio_setcfg(AWPIO_LED_BLUE, AWPIO_OUTPUT);
-	sxipio_setpin(AWPIO_LED_GREEN);
-	sxipio_setpin(AWPIO_LED_BLUE);
+	sxipio_setcfg(SXIPIO_LED_GREEN, SXIPIO_OUTPUT);
+	sxipio_setcfg(SXIPIO_LED_BLUE, SXIPIO_OUTPUT);
+	sxipio_setpin(SXIPIO_LED_GREEN);
+	sxipio_setpin(SXIPIO_LED_BLUE);
 
 	config_defer(self, sxipio_attach_gpio);
 
@@ -158,26 +158,26 @@ void
 sxipio_pin_ctl(void *portno, int pin, int flags)
 {
 	if (ISSET(flags, GPIO_PIN_OUTPUT))
-		sxipio_setcfg((*(uint32_t *)portno * 32) + pin, AWPIO_OUTPUT);
+		sxipio_setcfg((*(uint32_t *)portno * 32) + pin, SXIPIO_OUTPUT);
 	else
-		sxipio_setcfg((*(uint32_t *)portno * 32) + pin, AWPIO_INPUT);
+		sxipio_setcfg((*(uint32_t *)portno * 32) + pin, SXIPIO_INPUT);
 }
 
 /* XXX ugly, but cookie has no other purposeful use. */
-static const uint32_t sxipio_ports[AWPIO_NPORT] = {
+static const uint32_t sxipio_ports[SXIPIO_NPORT] = {
 	0, 1, 2, 3, 4, 5, 6, 7, 8
 };
 
-static const int sxipio_last_pin[AWPIO_NPORT] = {
-	AWPIO_PA_NPIN,
-	AWPIO_PB_NPIN,
-	AWPIO_PC_NPIN,
-	AWPIO_PD_NPIN,
-	AWPIO_PE_NPIN,
-	AWPIO_PF_NPIN,
-	AWPIO_PG_NPIN,
-	AWPIO_PH_NPIN,
-	AWPIO_PI_NPIN
+static const int sxipio_last_pin[SXIPIO_NPORT] = {
+	SXIPIO_PA_NPIN,
+	SXIPIO_PB_NPIN,
+	SXIPIO_PC_NPIN,
+	SXIPIO_PD_NPIN,
+	SXIPIO_PE_NPIN,
+	SXIPIO_PF_NPIN,
+	SXIPIO_PG_NPIN,
+	SXIPIO_PH_NPIN,
+	SXIPIO_PI_NPIN
 };
 
 void
@@ -222,7 +222,7 @@ next:
 	config_found(&sc->sc_dev, &gba, gpiobus_print);
 
 	pin = 0;
-	if (++port < AWPIO_NPORT)
+	if (++port < SXIPIO_NPORT)
 		goto next;
 }
 
@@ -239,12 +239,12 @@ sxipio_getcfg(int pin)
 
 	port = pin >> 5;
 	bit = pin - (port << 5);
-	reg = AWPIO_CFG(port, bit >> 3);
+	reg = SXIPIO_CFG(port, bit >> 3);
 	off = (bit & 7) << 2;
 
 	s = splhigh();
 
-	data = AWREAD4(sc, reg);
+	data = SXIREAD4(sc, reg);
 
 	splx(s);
 
@@ -260,14 +260,14 @@ sxipio_setcfg(int pin, int mux)
 
 	port = pin >> 5;
 	bit = pin - (port << 5);
-	reg = AWPIO_CFG(port, bit >> 3);
+	reg = SXIPIO_CFG(port, bit >> 3);
 	off = (bit & 7) << 2;
 	cmask = 7 << off;
 	mask = mux << off;
 
 	s = splhigh();
 
-	AWCMS4(sc, reg, cmask, mask);
+	SXICMS4(sc, reg, cmask, mask);
 
 	splx(s);
 }
@@ -281,12 +281,12 @@ sxipio_getpin(int pin)
 
 	port = pin >> 5;
 	bit = pin - (port << 5);
-	reg = AWPIO_DAT(port);
+	reg = SXIPIO_DAT(port);
 	mask = 1 << (bit & 31);
 
 	s = splhigh();
 
-	data = AWREAD4(sc, reg);
+	data = SXIREAD4(sc, reg);
 
 	splx(s);
 
@@ -302,12 +302,12 @@ sxipio_setpin(int pin)
 
 	port = pin >> 5;
 	bit = pin - (port << 5);
-	reg = AWPIO_DAT(port);
+	reg = SXIPIO_DAT(port);
 	mask = 1 << (bit & 31);
 
 	s = splhigh();
 
-	AWSET4(sc, reg, mask);
+	SXISET4(sc, reg, mask);
 
 	splx(s);
 }
@@ -321,12 +321,12 @@ sxipio_clrpin(int pin)
 
 	port = pin >> 5;
 	bit = pin - (port << 5);
-	reg = AWPIO_DAT(port);
+	reg = SXIPIO_DAT(port);
 	mask = 1 << (bit & 31);
 
 	s = splhigh();
 
-	AWCLR4(sc, reg, mask);
+	SXICLR4(sc, reg, mask);
 
 	splx(s);
 }
@@ -340,13 +340,13 @@ sxipio_togglepin(int pin)
 
 	port = pin >> 5;
 	bit = pin - (port << 5);
-	reg = AWPIO_DAT(port);
+	reg = SXIPIO_DAT(port);
 	mask = 1 << (bit & 31);
 
 	s = splhigh();
 
-	data = AWREAD4(sc, reg);
-	AWWRITE4(sc, reg, data ^ mask);
+	data = SXIREAD4(sc, reg);
+	SXIWRITE4(sc, reg, data ^ mask);
 
 	splx(s);
 
diff --git a/sys/arch/armv7/sunxi/sxipiovar.h b/sys/arch/armv7/sunxi/sxipiovar.h
index 46072dd0100..4b44bced029 100644
--- a/sys/arch/armv7/sunxi/sxipiovar.h
+++ b/sys/arch/armv7/sunxi/sxipiovar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxipiovar.h,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sxipiovar.h,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2013 Artturi Alm
  *
@@ -23,15 +23,15 @@
  * these pin defines.
  */
 
-#define	AWPIO_INPUT		0
-#define	AWPIO_OUTPUT		1
+#define	SXIPIO_INPUT		0
+#define	SXIPIO_OUTPUT		1
 
-#define AWPIO_USB1_PWR		230
-#define AWPIO_USB2_PWR		227
-#define AWPIO_LED_GREEN		244
-#define AWPIO_LED_BLUE		245
-#define AWPIO_SATA_PWR		40
-#define	AWPIO_EMAC_NPINS	18	/* PORTA 0-17 */
+#define SXIPIO_USB1_PWR		230
+#define SXIPIO_USB2_PWR		227
+#define SXIPIO_LED_GREEN		244
+#define SXIPIO_LED_BLUE		245
+#define SXIPIO_SATA_PWR		40
+#define	SXIPIO_EMAC_NPINS	18	/* PORTA 0-17 */
 
 int sxipio_getcfg(int);
 void sxipio_setcfg(int, int);
diff --git a/sys/arch/armv7/sunxi/sxirtc.c b/sys/arch/armv7/sunxi/sxirtc.c
index 17de957f017..33ddcc403aa 100644
--- a/sys/arch/armv7/sunxi/sxirtc.c
+++ b/sys/arch/armv7/sunxi/sxirtc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxirtc.c,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sxirtc.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2008 Mark Kettenis
  * Copyright (c) 2013 Artturi Alm
@@ -30,8 +30,8 @@
 
 #include <armv7/sunxi/sunxivar.h>
 
-#define	AWRTC_YYMMDD	0x00
-#define	AWRTC_HHMMSS	0x04
+#define	SXIRTC_YYMMDD	0x00
+#define	SXIRTC_HHMMSS	0x04
 
 #define LEAPYEAR(y)        \
     (((y) % 4 == 0 &&    \
@@ -98,13 +98,13 @@ sxirtc_gettime(todr_chip_handle_t handle, struct timeval *tv)
 	struct clock_ymdhms dt;
 	uint32_t reg;
 
-	reg = AWREAD4(sc, AWRTC_HHMMSS);
+	reg = SXIREAD4(sc, SXIRTC_HHMMSS);
 	dt.dt_sec = reg & 0x3f;
 	dt.dt_min = reg >> 8 & 0x3f;
 	dt.dt_hour = reg >> 16 & 0x1f;
 	dt.dt_wday = reg >> 29 & 0x07;
 
-	reg = AWREAD4(sc, AWRTC_YYMMDD);
+	reg = SXIREAD4(sc, SXIRTC_YYMMDD);
 	dt.dt_day = reg & 0x1f;
 	dt.dt_mon = reg >> 8 & 0x0f;
 	dt.dt_year = (reg >> 16 & 0x3f) + 2010; /* 0xff on A20 */
@@ -134,11 +134,11 @@ sxirtc_settime(todr_chip_handle_t handle, struct timeval *tv)
 	    dt.dt_mon > 12 || dt.dt_mon == 0)
 		return 1;
 
-	AWCMS4(sc, AWRTC_HHMMSS, 0xe0000000 | 0x1f0000 | 0x3f00 | 0x3f,
+	SXICMS4(sc, SXIRTC_HHMMSS, 0xe0000000 | 0x1f0000 | 0x3f00 | 0x3f,
 	    dt.dt_sec | (dt.dt_min << 8) | (dt.dt_hour << 16) |
 	    (dt.dt_wday << 29));
 
-	AWCMS4(sc, AWRTC_YYMMDD, 0x00400000 | 0x003f0000 | 0x0f00 | 0x1f,
+	SXICMS4(sc, SXIRTC_YYMMDD, 0x00400000 | 0x003f0000 | 0x0f00 | 0x1f,
 	   dt.dt_day | (dt.dt_mon << 8) | ((dt.dt_year - 2010) << 16) |
 	   (LEAPYEAR(dt.dt_year) << 22));
 
diff --git a/sys/arch/armv7/sunxi/sxiuart.c b/sys/arch/armv7/sunxi/sxiuart.c
index caa66b3f783..567be24def8 100644
--- a/sys/arch/armv7/sunxi/sxiuart.c
+++ b/sys/arch/armv7/sunxi/sxiuart.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiuart.c,v 1.1 2013/10/23 17:08:48 jasper Exp $	*/
+/*	$OpenBSD: sxiuart.c,v 1.2 2013/10/23 18:01:52 jasper Exp $	*/
 /*
  * Copyright (c) 2005 Dale Rahn <drahn@motorola.com>
  * Copyright (c) 2013 Artturi Alm
@@ -80,9 +80,9 @@ struct sxiuart_softc {
 	uint8_t		sc_initialize;
 	uint8_t		sc_cua;
 	uint8_t 	*sc_ibuf, *sc_ibufp, *sc_ibufhigh, *sc_ibufend;
-#define AWUART_IBUFSIZE 128
-#define AWUART_IHIGHWATER 100
-	uint8_t		sc_ibufs[2][AWUART_IBUFSIZE];
+#define SXIUART_IBUFSIZE 128
+#define SXIUART_IHIGHWATER 100
+	uint8_t		sc_ibufs[2][SXIUART_IBUFSIZE];
 };
 
 
@@ -170,19 +170,19 @@ sxiuartattach(struct device *parent, struct device *self, void *args)
 
 	sc->sc_frequency = 24000000; /* XXX */
 
-	if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, AWUART_IIR) &
+	if ((bus_space_read_1(sc->sc_iot, sc->sc_ioh, SXIUART_IIR) &
 	  IIR_BUSY) == IIR_BUSY)
-		(void)bus_space_read_4(sc->sc_iot, sc->sc_ioh, AWUART_USR);
+		(void)bus_space_read_4(sc->sc_iot, sc->sc_ioh, SXIUART_USR);
 	sc->sc_ier = 0;
 	/* disable interrupts */
-	bus_space_write_1(iot, ioh, AWUART_IER, sc->sc_ier);
+	bus_space_write_1(iot, ioh, SXIUART_IER, sc->sc_ier);
 
 	/* clear and disable fifo */
-	bus_space_write_1(iot, ioh, AWUART_FCR, 0 | RFIFOR | XFIFOR);
+	bus_space_write_1(iot, ioh, SXIUART_FCR, 0 | RFIFOR | XFIFOR);
 
 	s = splhigh();
 	SET(sc->sc_mcr, MCR_DTR | MCR_RTS | MCR_IENABLE);
-	bus_space_write_1(sc->sc_iot, sc->sc_ioh, AWUART_MCR, sc->sc_mcr);
+	bus_space_write_1(sc->sc_iot, sc->sc_ioh, SXIUART_MCR, sc->sc_mcr);
 	splx(s);
 
 	arm_intr_establish(sxi->sxi_dev->irq[0], IPL_TTY,
@@ -202,10 +202,10 @@ sxiuart_intr(void *arg)
 	uint8_t c, iir, lsr, msr, delta;
 	uint8_t *p;
 
-	iir = bus_space_read_1(iot, ioh, AWUART_IIR);
+	iir = bus_space_read_1(iot, ioh, SXIUART_IIR);
 
 	if ((iir & IIR_IMASK) == IIR_BUSY) {
-		(void)bus_space_read_1(iot, ioh, AWUART_USR);
+		(void)bus_space_read_1(iot, ioh, SXIUART_USR);
 		return (0);
 	}
 	if (ISSET(iir, IIR_NOPEND))
@@ -217,7 +217,7 @@ sxiuart_intr(void *arg)
 	tp = sc->sc_tty;
 	cnt = 0;
 loop:
-	lsr = bus_space_read_1(iot, ioh, AWUART_LSR);
+	lsr = bus_space_read_1(iot, ioh, SXIUART_LSR);
 	if (ISSET(lsr, LSR_RXRDY)) {
 		if (cnt == 0) {
 			p = sc->sc_ibufp;
@@ -225,7 +225,7 @@ loop:
 		}
 		cnt++;
 
-		c = bus_space_read_1(iot, ioh, AWUART_RBR);
+		c = bus_space_read_1(iot, ioh, SXIUART_RBR);
 		if (ISSET(lsr, LSR_BI)) {
 #if defined(DDB)
 			if (ISSET(sc->sc_hwflags,
@@ -248,14 +248,14 @@ loop:
 			    ISSET(tp->t_cflag, CRTSCTS)) {
 				/* XXX */
 				CLR(sc->sc_mcr, MCR_RTS);
-				bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+				bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 			}
 		}
 		goto loop;
 	} else if (cnt > 0)
 		sc->sc_ibufp = p;
 
-	msr = bus_space_read_1(iot, ioh, AWUART_MSR);
+	msr = bus_space_read_1(iot, ioh, SXIUART_MSR);
 	if (msr != sc->sc_msr) {
 		delta = msr ^ sc->sc_msr;
 
@@ -269,7 +269,7 @@ loop:
 			    (*linesw[tp->t_line].l_modem)(tp,
 			    ISSET(msr, MSR_DCD)) == 0) {
 				CLR(sc->sc_mcr, sc->sc_dtr);
-				bus_space_write_1(iot, ioh, AWUART_MCR,
+				bus_space_write_1(iot, ioh, SXIUART_MCR,
 				    sc->sc_mcr);
 			}
 		}
@@ -285,7 +285,7 @@ loop:
 		(*linesw[tp->t_line].l_start)(tp);
 	}
 
-	iir = bus_space_read_1(iot, ioh, AWUART_IIR);
+	iir = bus_space_read_1(iot, ioh, SXIUART_IIR);
 
 	if (ISSET(iir, IIR_NOPEND))
 		goto done;
@@ -312,7 +312,7 @@ sxiuart_param(struct tty *tp, struct termios *t)
 	if (t->c_ospeed < 0 || (t->c_ispeed && t->c_ispeed != t->c_ospeed))
 		return (EINVAL);
 
-	/* XXX get prev state of AWUART_LCR_SBREAK bit */
+	/* XXX get prev state of SXIUART_LCR_SBREAK bit */
 
 	switch (ISSET(t->c_cflag, CSIZE)) {
 	case CS5:
@@ -340,7 +340,7 @@ sxiuart_param(struct tty *tp, struct termios *t)
 
 	if (ospeed == 0) {
 		CLR(sc->sc_mcr, MCR_DTR);
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 	}
 
 	if (ospeed != 0) { /* XXX sc_initialize? */
@@ -354,30 +354,30 @@ sxiuart_param(struct tty *tp, struct termios *t)
 				return (error);
 			}
 		}
-		bus_space_write_1(iot, ioh, AWUART_LCR, lcr | LCR_DLAB);
+		bus_space_write_1(iot, ioh, SXIUART_LCR, lcr | LCR_DLAB);
 		ratediv = 13;
-		bus_space_write_1(iot, ioh, AWUART_DLL, ratediv);
-		bus_space_write_1(iot, ioh, AWUART_DLH, ratediv >> 8);
-		bus_space_write_1(iot, ioh, AWUART_LCR, lcr);
+		bus_space_write_1(iot, ioh, SXIUART_DLL, ratediv);
+		bus_space_write_1(iot, ioh, SXIUART_DLH, ratediv >> 8);
+		bus_space_write_1(iot, ioh, SXIUART_LCR, lcr);
 		SET(sc->sc_mcr, MCR_DTR);
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 	} else
-		bus_space_write_1(iot, ioh, AWUART_LCR, lcr);
+		bus_space_write_1(iot, ioh, SXIUART_LCR, lcr);
 
 	/* setup fifo */
-	bus_space_write_1(iot, ioh, AWUART_FCR, FIFOE | FIFO_RXT0);
+	bus_space_write_1(iot, ioh, SXIUART_FCR, FIFOE | FIFO_RXT0);
 
 	/* When not using CRTSCTS, RTS follows DTR. */
 	if (!ISSET(t->c_cflag, CRTSCTS)) {
 		if (ISSET(sc->sc_mcr, MCR_DTR)) {
 			if (!ISSET(sc->sc_mcr, MCR_RTS)) {
 				SET(sc->sc_mcr, MCR_RTS);
-				bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+				bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 			}
 		} else {
 			if (ISSET(sc->sc_mcr, MCR_RTS)) {
 				CLR(sc->sc_mcr, MCR_RTS);
-				bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+				bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 			}
 		}
 		sc->sc_dtr = MCR_DTR | MCR_RTS;
@@ -400,7 +400,7 @@ sxiuart_param(struct tty *tp, struct termios *t)
 	    ISSET(oldcflag, MDMBUF) != ISSET(tp->t_cflag, MDMBUF) &&
 	    (*linesw[tp->t_line].l_modem)(tp, 0) == 0) {
 		CLR(sc->sc_mcr, sc->sc_dtr);
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 	}
 
 
@@ -446,19 +446,19 @@ sxiuart_start(struct tty *tp)
 
 	if (!ISSET(sc->sc_ier, IER_ETXRDY)) {
 		SET(sc->sc_ier, IER_ETXRDY);
-		bus_space_write_1(iot, ioh, AWUART_IER, sc->sc_ier);
+		bus_space_write_1(iot, ioh, SXIUART_IER, sc->sc_ier);
 	}
 
 	n = q_to_b(&tp->t_outq, buf, sizeof(buf));
 	for (i = 0; i < n; i++)
-		bus_space_write_1(iot, ioh, AWUART_THR, buf[i]);
+		bus_space_write_1(iot, ioh, SXIUART_THR, buf[i]);
 	bzero(buf, n);
 	splx(s);
 	return;
 stopped:
 	if (ISSET(sc->sc_ier, IER_ETXRDY)) {
 		CLR(sc->sc_ier, IER_ETXRDY);
-		bus_space_write_1(iot, ioh, AWUART_IER, sc->sc_ier);
+		bus_space_write_1(iot, ioh, SXIUART_IER, sc->sc_ier);
 	}
 	splx(s);
 }
@@ -492,7 +492,7 @@ sxiuart_raisedtr(void *arg)
 	struct sxiuart_softc *sc = arg;
 
 	SET(sc->sc_mcr, MCR_DTR | MCR_RTS);
-	bus_space_write_1(sc->sc_iot, sc->sc_ioh, AWUART_MCR, sc->sc_mcr);
+	bus_space_write_1(sc->sc_iot, sc->sc_ioh, SXIUART_MCR, sc->sc_mcr);
 }
 
 void
@@ -526,8 +526,8 @@ sxiuart_softint(void *arg)
 
 	sc->sc_ibufp = sc->sc_ibuf = (ibufp == sc->sc_ibufs[0]) ?
 				     sc->sc_ibufs[1] : sc->sc_ibufs[0];
-	sc->sc_ibufhigh = sc->sc_ibuf + AWUART_IHIGHWATER;
-	sc->sc_ibufend = sc->sc_ibuf + AWUART_IBUFSIZE;
+	sc->sc_ibufhigh = sc->sc_ibuf + SXIUART_IHIGHWATER;
+	sc->sc_ibufend = sc->sc_ibuf + SXIUART_IBUFSIZE;
 
 	if (tp == NULL || !ISSET(tp->t_state, TS_ISOPEN)) {
 		splx(s);
@@ -538,7 +538,7 @@ sxiuart_softint(void *arg)
 	    !ISSET(sc->sc_mcr, MCR_RTS)) {
 		/* XXX */
 		SET(sc->sc_mcr, MCR_RTS);
-		bus_space_write_1(sc->sc_iot, sc->sc_ioh, AWUART_MCR,
+		bus_space_write_1(sc->sc_iot, sc->sc_ioh, SXIUART_MCR,
 		    sc->sc_mcr);
 	}
 
@@ -610,25 +610,25 @@ sxiuartopen(dev_t dev, int flag, int mode, struct proc *p)
 		ttsetwater(tp);
 
 		sc->sc_ibufp = sc->sc_ibuf = sc->sc_ibufs[0];
-		sc->sc_ibufhigh = sc->sc_ibuf + AWUART_IHIGHWATER;
-		sc->sc_ibufend = sc->sc_ibuf + AWUART_IBUFSIZE;
+		sc->sc_ibufhigh = sc->sc_ibuf + SXIUART_IHIGHWATER;
+		sc->sc_ibufend = sc->sc_ibuf + SXIUART_IBUFSIZE;
 
 		iot = sc->sc_iot;
 		ioh = sc->sc_ioh;
 
-		bus_space_write_1(iot, ioh, AWUART_FCR, FIFOE | FIFO_RXT2);
+		bus_space_write_1(iot, ioh, SXIUART_FCR, FIFOE | FIFO_RXT2);
 		delay(100);
-		while (ISSET(bus_space_read_1(iot, ioh, AWUART_LSR),
+		while (ISSET(bus_space_read_1(iot, ioh, SXIUART_LSR),
 		    LSR_RXRDY))
-			(void)bus_space_read_1(iot, ioh, AWUART_RBR);
+			(void)bus_space_read_1(iot, ioh, SXIUART_RBR);
 
 		sc->sc_mcr = MCR_DTR | MCR_RTS | MCR_IENABLE;
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 
 		sc->sc_ier = IER_ERXRDY | IER_ERLS | IER_EMSC;
-		bus_space_write_1(iot, ioh, AWUART_IER, sc->sc_ier);
+		bus_space_write_1(iot, ioh, SXIUART_IER, sc->sc_ier);
 
-		sc->sc_msr = bus_space_read_1(iot, ioh, AWUART_MSR);
+		sc->sc_msr = bus_space_read_1(iot, ioh, SXIUART_MSR);
 		if (ISSET(sc->sc_swflags, COM_SW_SOFTCAR) || DEVCUA(dev) ||
 		    ISSET(sc->sc_msr, MSR_DCD) ||
 		    ISSET(tp->t_cflag, MDMBUF))
@@ -704,7 +704,7 @@ sxiuartclose(dev_t dev, int flag, int mode, struct proc *p)
 	if (ISSET(tp->t_state, TS_WOPEN)) {
 		/* tty device is waiting for carrier; drop dtr then re-raise */
 		CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 		timeout_add(&sc->sc_dtr_tmo, hz * 2);
 	} else {
 		/* no one else waiting; turn off the uart */
@@ -788,29 +788,29 @@ sxiuartioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
 	switch (cmd) {
 	case TIOCSBRK:
 		SET(sc->sc_lcr, LCR_SBREAK);
-		bus_space_write_1(iot, ioh, AWUART_LCR, sc->sc_lcr);
+		bus_space_write_1(iot, ioh, SXIUART_LCR, sc->sc_lcr);
 		break;
 	case TIOCCBRK:
 		CLR(sc->sc_lcr, LCR_SBREAK);
-		bus_space_write_1(iot, ioh, AWUART_LCR, sc->sc_lcr);
+		bus_space_write_1(iot, ioh, SXIUART_LCR, sc->sc_lcr);
 		break;
 	case TIOCSDTR:
 		SET(sc->sc_mcr, sc->sc_dtr);
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 		break;
 	case TIOCCDTR:
 		CLR(sc->sc_mcr, sc->sc_dtr);
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 		break;
 	case TIOCMSET:
 		CLR(sc->sc_mcr, MCR_DTR | MCR_RTS);
 	case TIOCMBIS:
 		SET(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 		break;
 	case TIOCMBIC:
 		CLR(sc->sc_mcr, tiocm_xxx2mcr(*(int *)data));
-		bus_space_write_1(iot, ioh, AWUART_MCR, sc->sc_mcr);
+		bus_space_write_1(iot, ioh, SXIUART_MCR, sc->sc_mcr);
 		break;
 	case TIOCMGET: {
 		u_char m;
@@ -830,7 +830,7 @@ sxiuartioctl(dev_t dev, u_long cmd, caddr_t data, int flag, struct proc *p)
 			SET(bits, TIOCM_DSR);
 		if (ISSET(m, MSR_RI | MSR_TERI))
 			SET(bits, TIOCM_RI);
-		if (bus_space_read_1(iot, ioh, AWUART_IER))
+		if (bus_space_read_1(iot, ioh, SXIUART_IER))
 			SET(bits, TIOCM_LE);
 		*(int *)data = bits;
 		break;
@@ -944,19 +944,19 @@ sxiuartcnattach(bus_space_tag_t iot, bus_addr_t iobase, int rate, long freq,
 	sxiuartconscflag = cflag;
 
 	s = splhigh();
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_LCR, LCR_DLAB);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_LCR, LCR_DLAB);
 
 	ratediv = 13; /* for 115200baud with 24000000hz freq */
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_DLL, ratediv);
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_DLH, ratediv >> 8);
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_LCR, LCR_8BITS);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_DLL, ratediv);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_DLH, ratediv >> 8);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_LCR, LCR_8BITS);
 
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_MCR, MCR_DTR | MCR_RTS);
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_IER, 0);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_MCR, MCR_DTR | MCR_RTS);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_IER, 0);
 
-	bus_space_write_1(iot, sxiuartconsioh, AWUART_FCR, FIFOE | FIFO_RXT0);
+	bus_space_write_1(iot, sxiuartconsioh, SXIUART_FCR, FIFOE | FIFO_RXT0);
 
-	(void)bus_space_read_1(iot, sxiuartconsioh, AWUART_IIR);
+	(void)bus_space_read_1(iot, sxiuartconsioh, SXIUART_IIR);
 	splx(s);
 
 	cn_tab = &sxiuartcons;
@@ -973,12 +973,12 @@ sxiuartcngetc(dev_t dev)
 	s = splhigh();
 
 	while (!ISSET(bus_space_read_1(sxiuartconsiot, sxiuartconsioh,
-	    AWUART_LSR), LSR_RXRDY))
+	    SXIUART_LSR), LSR_RXRDY))
 		continue;
-	c = bus_space_read_1(sxiuartconsiot, sxiuartconsioh, AWUART_RBR);
+	c = bus_space_read_1(sxiuartconsiot, sxiuartconsioh, SXIUART_RBR);
 
 	/* clear any pending interrupts */
-	(void)bus_space_read_1(sxiuartconsiot, sxiuartconsioh, AWUART_IIR);
+	(void)bus_space_read_1(sxiuartconsiot, sxiuartconsioh, SXIUART_IIR);
 
 	splx(s);
 	return (c);
@@ -991,10 +991,10 @@ sxiuartcnputc(dev_t dev, int c)
 	int timo = 500;
 
 	while (!ISSET(bus_space_read_1(sxiuartconsiot, sxiuartconsioh,
-	    AWUART_LSR), LSR_THRE) && --timo)
+	    SXIUART_LSR), LSR_THRE) && --timo)
 		continue;
 
-	bus_space_write_1(sxiuartconsiot, sxiuartconsioh, AWUART_THR,
+	bus_space_write_1(sxiuartconsiot, sxiuartconsioh, SXIUART_THR,
 	    (uint8_t)c);
 	bus_space_barrier(sxiuartconsiot, sxiuartconsioh, 0, 1,
 	    BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
diff --git a/sys/arch/armv7/sunxi/sxiuartreg.h b/sys/arch/armv7/sunxi/sxiuartreg.h
index a7d6a13bc02..dea01b6605f 100644
--- a/sys/arch/armv7/sunxi/sxiuartreg.h
+++ b/sys/arch/armv7/sunxi/sxiuartreg.h
@@ -1,19 +1,19 @@
-#define	AWUART_RBR	0x00
-#define	AWUART_THR	0x00
-#define AWUART_DLL	0x00
-#define AWUART_DLH	0x04
-#define AWUART_IER	0x04
-#define AWUART_IIR	0x08
-#define AWUART_FCR	0x08
-#define AWUART_LCR	0x0c
-#define AWUART_MCR	0x10
-#define AWUART_LSR	0x14
-#define AWUART_MSR	0x18
-#define AWUART_SCH	0x1c
-#define AWUART_USR	0x7c
-#define AWUART_TFL	0x80
-#define AWUART_RFL	0x84
-#define AWUART_HALT	0xa4
+#define	SXIUART_RBR	0x00
+#define	SXIUART_THR	0x00
+#define SXIUART_DLL	0x00
+#define SXIUART_DLH	0x04
+#define SXIUART_IER	0x04
+#define SXIUART_IIR	0x08
+#define SXIUART_FCR	0x08
+#define SXIUART_LCR	0x0c
+#define SXIUART_MCR	0x10
+#define SXIUART_LSR	0x14
+#define SXIUART_MSR	0x18
+#define SXIUART_SCH	0x1c
+#define SXIUART_USR	0x7c
+#define SXIUART_TFL	0x80
+#define SXIUART_RFL	0x84
+#define SXIUART_HALT	0xa4
 
 /* interrupt enable register */
 #define IER_PTIME	0x80