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authorpatrick <patrick@openbsd.org>2020-11-06 13:29:45 +0000
committerpatrick <patrick@openbsd.org>2020-11-06 13:29:45 +0000
commit4e7ccb5f3f2b12fa67da66bd2e4efbdfb8154cce (patch)
treeabcbd08ea1465225eb74011ce60bce9417d57bd7
parentRemove unused `anon' argument from uvmfault_unlockall(). (diff)
downloadwireguard-openbsd-4e7ccb5f3f2b12fa67da66bd2e4efbdfb8154cce.tar.xz
wireguard-openbsd-4e7ccb5f3f2b12fa67da66bd2e4efbdfb8154cce.zip
The ClearFog GT 8K device tree references the PP22's gate clock
instead of the core clock, so add this one to mvclock(4) as well. ok kettenis@
-rw-r--r--sys/dev/fdt/mvclock.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/sys/dev/fdt/mvclock.c b/sys/dev/fdt/mvclock.c
index 5a999f174ef..caf657fbcde 100644
--- a/sys/dev/fdt/mvclock.c
+++ b/sys/dev/fdt/mvclock.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: mvclock.c,v 1.7 2020/05/22 10:06:59 patrick Exp $ */
+/* $OpenBSD: mvclock.c,v 1.8 2020/11/06 13:29:45 patrick Exp $ */
/*
* Copyright (c) 2018 Mark Kettenis <kettenis@openbsd.org>
*
@@ -156,6 +156,7 @@ ap806_get_frequency(void *cookie, uint32_t *cells)
#define CP110_CORE_CORE 3
#define CP110_CORE_SDIO 5
+#define CP110_GATE_PPV2 3
#define CP110_GATE_SDIO 4
#define CP110_GATE_SLOW_IO 21
@@ -193,6 +194,9 @@ cp110_get_frequency(void *cookie, uint32_t *cells)
/* Gatable clocks */
if (mod == 1) {
switch (idx) {
+ case CP110_GATE_PPV2:
+ parent[1] = CP110_CORE_PPV2;
+ break;
case CP110_GATE_SDIO:
parent[1] = CP110_CORE_SDIO;
break;