some fixes

- fix the reset path and remove the '#if 0'. firmware loading makes me cry
- update the SW (CRB) register offsets to match the upcoming 3.4.31 firmware
- the link state and ifmedia should work now with a register and code fix
- ...

2 files changed, 201 insertions, 114 deletions

diff --git a/sys/dev/pci/if_nx.c b/sys/dev/pci/if_nx.c
index 8872a3f4f18..a0949d912f5 100644
--- a/sys/dev/pci/if_nx.c
+++ b/sys/dev/pci/if_nx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_nx.c,v 1.35 2007/05/01 16:25:48 reyk Exp $	*/
+/*	$OpenBSD: if_nx.c,v 1.36 2007/05/01 21:56:21 reyk Exp $	*/
 
 /*
  * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org>
@@ -102,6 +102,7 @@ struct nx_softc;
 struct nxb_port {
 	u_int8_t		 nxp_id;
 	u_int8_t		 nxp_mode;
+	u_int8_t		 nxp_phy;
 	u_int8_t		 nxp_lladdr[ETHER_ADDR_LEN];
 
 	struct nx_softc		*nxp_nx;
@@ -122,6 +123,10 @@ struct nxb_softc {
 	bus_space_handle_t	 sc_dbmemh;
 	bus_size_t		 sc_dbmems;
 
+	int			 sc_window;	/* SW memory window */
+	int			 sc_ddrwindow;	/* PCI DDR memory window */
+	int			 sc_qdrwindow;	/* PCI QDR memory window */
+
 	pci_intr_handle_t	 sc_ih;
 
 	u_int			 sc_flags;
@@ -130,7 +135,6 @@ struct nxb_softc {
 	struct nxb_info		 sc_nxbinfo;	/* Information from flash */
 	struct nxb_imageinfo	 sc_nxbimage;	/* Image info from flash */
 
-	int			 sc_window;	/* SW memory window */
 	int			 sc_state;	/* Firmware state */
 	u_int32_t		 sc_fwmajor;	/* Load image major rev */
 	u_int32_t		 sc_fwminor;	/* Load image minor rev */
@@ -178,6 +182,7 @@ u_int32_t nxb_read(struct nxb_softc *, bus_size_t);
 void	 nxb_write(struct nxb_softc *, bus_size_t, u_int32_t);
 int	 nxb_writehw(struct nxb_softc *, u_int32_t, u_int32_t);
 void	 nxb_set_window(struct nxb_softc *, int);
+bus_size_t nxb_set_pciwindow(struct nxb_softc *, bus_size_t);
 int	 nxb_wait(struct nxb_softc *, bus_size_t, u_int32_t, u_int32_t,
 	    int, u_int);
 int	 nxb_read_rom(struct nxb_softc *, u_int32_t, u_int32_t *);
@@ -227,13 +232,14 @@ const struct nxb_board {
 	enum nxb_board_types	brd_type;
 	u_int			brd_mode;
 	u_int			brd_nports;
+	u_int			brd_phy;	/* The default PHY */
 } nxb_boards[] = {
-	{ NXB_BOARDTYPE_P2SB35_4G,	NXNIU_MODE_GBE, 4 },
-	{ NXB_BOARDTYPE_P2SB31_10G,	NXNIU_MODE_XGE, 1 },
-	{ NXB_BOARDTYPE_P2SB31_2G,	NXNIU_MODE_GBE, 2 },
-	{ NXB_BOARDTYPE_P2SB31_10GIMEZ,	NXNIU_MODE_XGE, 2 },
-	{ NXB_BOARDTYPE_P2SB31_10GHMEZ,	NXNIU_MODE_XGE, 2 },
-	{ NXB_BOARDTYPE_P2SB31_10GCX4,	NXNIU_MODE_XGE, 1 }
+	{ NXB_BOARDTYPE_P2SB35_4G,	NXNIU_MODE_GBE, 4, IFM_1000_T },
+	{ NXB_BOARDTYPE_P2SB31_10G,	NXNIU_MODE_XGE, 1, IFM_10G_SR },
+	{ NXB_BOARDTYPE_P2SB31_2G,	NXNIU_MODE_GBE, 2, IFM_1000_T },
+	{ NXB_BOARDTYPE_P2SB31_10GIMEZ,	NXNIU_MODE_XGE, 2, IFM_10G_SR },
+	{ NXB_BOARDTYPE_P2SB31_10GHMEZ,	NXNIU_MODE_XGE, 2, IFM_10G_SR },
+	{ NXB_BOARDTYPE_P2SB31_10GCX4,	NXNIU_MODE_XGE, 1, IFM_10G_CX4 }
 };
 
 extern int ifqmaxlen;
@@ -265,6 +271,8 @@ nxb_attach(struct device *parent, struct device *self, void *aux)
 	sc->sc_dmat = pa->pa_dmat;
 	sc->sc_function = pa->pa_function;
 	sc->sc_window = -1;
+	sc->sc_ddrwindow = -1;
+	sc->sc_qdrwindow = -1;
 
 	/*
 	 * The NetXen NICs can have different PCI memory layouts which
@@ -466,6 +474,7 @@ nxb_query(struct nxb_softc *sc)
 	for (i = 0; i < sc->sc_nports; i++) {
 		sc->sc_nxp[i].nxp_id = i;
 		sc->sc_nxp[i].nxp_mode = board->brd_mode;
+		sc->sc_nxp[i].nxp_phy = board->brd_phy;
 	}
 
 	/*
@@ -552,6 +561,7 @@ nxb_newstate(struct nxb_softc *sc, int newstate)
 		/*
 		 * Initialize and bootstrap the device
 		 */
+		nxb_set_window(sc, 1);
 		nxb_write(sc, NXSW_CMD_PRODUCER_OFF, 0);
 		nxb_write(sc, NXSW_CMD_CONSUMER_OFF, 0);
 		nxb_write(sc, NXSW_CMD_ADDR_LO, 0);
@@ -573,10 +583,10 @@ nxb_newstate(struct nxb_softc *sc, int newstate)
 		}
 		break;
 	case NX_S_RELOADED:
+		assert(oldstate == NX_S_RESET || oldstate == NX_S_BOOT);
 		/*
 		 * Wait for the device to become ready
 		 */
-		assert(oldstate == NX_S_BOOT);
 		sc->sc_reloaded = 20;
 		timeout_add(&sc->sc_reload, hz);
 		break;
@@ -692,11 +702,12 @@ nxb_reloadfirmware(struct nxb_softc *sc, struct nxb_firmware_header *fh,
 	size_t		 memlen;
 	u_int32_t	 addr, *data;
 	u_int		 i;
+	size_t		 bsize = NXFLASHMAP_BOOTLDSIZE;
 
 	/*
 	 * Load the images from flash, setup a fake firmware header
 	 */
-	memlen = sc->sc_nxbimage.nim_bootld_size + sizeof(*fh);
+	memlen = bsize + sizeof(*fh);
 	mem = (u_int8_t *)malloc(memlen, M_DEVBUF, M_NOWAIT);
 	if (mem == NULL)
 		return (-1);
@@ -705,16 +716,16 @@ nxb_reloadfirmware(struct nxb_softc *sc, struct nxb_firmware_header *fh,
 	fh->fw_image_ver = htonl(sc->sc_nxbimage.nim_image_ver);
 	fh->fw_image_size = 0;	/* Reload firmware image from flash */
 	fh->fw_bootld_ver = htonl(sc->sc_nxbimage.nim_bootld_ver);
-	fh->fw_bootld_size = htonl(sc->sc_nxbimage.nim_bootld_size);
+	fh->fw_bootld_size = htonl(bsize);
 	bcopy(fh, mem, sizeof(*fh));
 
 	addr = NXFLASHMAP_BOOTLOADER;
 	data = (u_int32_t *)(mem + sizeof(*fh));
-	for (i = 0; i < (sc->sc_nxbimage.nim_bootld_size / 4); i++) {
+	for (i = 0; i < (bsize / 4); i++) {
 		if (nxb_read_rom(sc, addr, data) != 0)
 			goto fail;
 		addr += sizeof(u_int32_t);
-		data++;
+		*data++;
 	}
 
 	*fw = mem;
@@ -737,6 +748,51 @@ nxb_reset(struct nxb_softc *sc)
 	u_int32_t			*data, addr, addr1, val, ncrb;
 	bus_size_t			 reg;
 
+	nxb_set_window(sc, 1);
+
+	/*
+	 * Load the firmware from disk or from flash
+	 */
+	bzero(&fh, sizeof(fh));
+	if (sc->sc_flags & NXFLAG_FWINVALID) {
+		if (nxb_loadfirmware(sc, &fh, &fw, &fwlen) != 0) {
+			printf("%s: failed to load firmware from disk\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+	} else {
+		if (nxb_reloadfirmware(sc, &fh, &fw, &fwlen) != 0) {
+			printf("%s: failed to reload firmware from flash\n",
+			    sc->sc_dev.dv_xname);
+			goto fail;
+		}
+	}
+
+	/*
+	 * Validate the information found in the extra header
+	 */
+	val = ntohl(fh.fw_image_ver);
+	sc->sc_fwmajor = (val & NXB_IMAGE_MAJOR_M) >> NXB_IMAGE_MAJOR_S;
+	sc->sc_fwminor = (val & NXB_IMAGE_MINOR_M) >> NXB_IMAGE_MINOR_S;
+	sc->sc_fwbuild = (val & NXB_IMAGE_BUILD_M) >> NXB_IMAGE_BUILD_S;
+	if (sc->sc_flags & NXFLAG_FWINVALID)
+		printf("%s: using firmware %u.%u.%u\n", sc->sc_dev.dv_xname,
+		    sc->sc_fwmajor, sc->sc_fwminor, sc->sc_fwbuild);
+	if (sc->sc_fwmajor != NX_FIRMWARE_MAJOR ||
+	    sc->sc_fwminor != NX_FIRMWARE_MINOR) {
+		printf("%s: unsupported firmware version\n",
+		    sc->sc_dev.dv_xname);
+		goto fail;
+	}
+
+	bootsz = ntohl(fh.fw_bootld_size);
+	imagesz = ntohl(fh.fw_image_size);
+	if ((imagesz + bootsz) != (fwlen - sizeof(fh)) ||
+	    (imagesz % 4) || (bootsz % 4)) {
+		printf("%s: invalid firmware image\n", sc->sc_dev.dv_xname);
+		goto fail;
+	}
+
 	/*
 	 * Reset the SW registers
 	 */
@@ -750,7 +806,7 @@ nxb_reset(struct nxb_softc *sc)
 		goto fail1;
 	ncrb &= NXFLASHMAP_CRBINIT_M;
 	if (ncrb == 0 || ncrb > NXFLASHMAP_CRBINIT_MAX)
-		goto load;	/* ignore CRBINIT and skip step */
+		goto fail1;	/* ignore CRBINIT and skip step */
 
 	/* 3. Write the CRBINIT are to PCI memory */
 	for (i = 0; i < ncrb; i++) {
@@ -784,50 +840,6 @@ nxb_reset(struct nxb_softc *sc)
 	nxb_write(sc, NXPPE_3(0xc), 0);
 	nxb_set_window(sc, 1);
 
- load:
-	/*
-	 * Load the firmware from disk or from flash
-	 */
-	bzero(&fh, sizeof(fh));
-	if (sc->sc_flags & NXFLAG_FWINVALID) {
-		if (nxb_loadfirmware(sc, &fh, &fw, &fwlen) != 0) {
-			printf("%s: failed to load firmware from disk\n",
-			    sc->sc_dev.dv_xname);
-			goto fail;
-		}
-	} else {
-		if (nxb_reloadfirmware(sc, &fh, &fw, &fwlen) != 0) {
-			printf("%s: failed to reload firmware from flash\n",
-			    sc->sc_dev.dv_xname);
-			goto fail;
-		}
-	}
-
-	/*
-	 * Validate the information found in the extra header
-	 */
-	val = ntohl(fh.fw_image_ver);
-	sc->sc_fwmajor = (val & NXB_IMAGE_MAJOR_M) >> NXB_IMAGE_MAJOR_S;
-	sc->sc_fwminor = (val & NXB_IMAGE_MINOR_M) >> NXB_IMAGE_MINOR_S;
-	sc->sc_fwbuild = (val & NXB_IMAGE_BUILD_M) >> NXB_IMAGE_BUILD_S;
-	if (sc->sc_flags & NXFLAG_FWINVALID)
-		printf("%s: using firmware %u.%u.%u\n", sc->sc_dev.dv_xname,
-		    sc->sc_fwmajor, sc->sc_fwminor, sc->sc_fwbuild);
-	if (sc->sc_fwmajor != NX_FIRMWARE_MAJOR ||
-	    sc->sc_fwminor != NX_FIRMWARE_MINOR) {
-		printf("%s: unsupported firmware version\n",
-		    sc->sc_dev.dv_xname);
-		goto fail;
-	}
-
-	bootsz = ntohl(fh.fw_bootld_size);
-	imagesz = ntohl(fh.fw_image_size);
-	if ((imagesz + bootsz) != (fwlen - sizeof(fh)) ||
-	    (imagesz % 4) || (bootsz % 4)) {
-		printf("%s: invalid firmware image\n", sc->sc_dev.dv_xname);
-		goto fail;
-	}
-
 	/*
 	 * Load the images into RAM
 	 */
@@ -835,20 +847,24 @@ nxb_reset(struct nxb_softc *sc)
 	/* Reset casper boot chip */
 	nxb_write(sc, NXROMUSB_GLB_CAS_RESET, NXROMUSB_GLB_CAS_RESET_ENABLE);
 
-#if 0
-	reg = NXFLASHMAP_BOOTLOADER;
+	addr = NXFLASHMAP_BOOTLOADER;
 	data = (u_int32_t *)(fw + sizeof(fh));
 	for (i = 0; i < (bootsz / 4); i++) {
+		reg = nxb_set_pciwindow(sc, addr);
+		if (reg == ~0ULL)
+			goto fail1;
 		nxb_write(sc, reg, *data);
-		reg += sizeof(u_int32_t);
+		addr += sizeof(u_int32_t);
 		data++;
 	}
-#endif
 	if (imagesz) {
-		reg = NXFLASHMAP_FIRMWARE_0;
+		addr = NXFLASHMAP_FIRMWARE_0;
 		for (i = 0; i < (imagesz / 4); i++) {
+			reg = nxb_set_pciwindow(sc, addr);
+			if (reg == ~0ULL)
+				goto fail1;
 			nxb_write(sc, reg, *data);
-			reg += sizeof(u_int32_t);
+			addr += sizeof(u_int32_t);
 			data++;
 		}
 		/* tell the bootloader to load the firmware image from RAM */
@@ -901,15 +917,15 @@ nxb_writehw(struct nxb_softc *sc, u_int32_t addr, u_int32_t val)
 {
 	/* Translation table of NIC addresses to PCI addresses */
 	static u_int16_t hwtrans[] = {
-	        0x29a0, 0x7730, 0x2950, 0x2a50, 0x0000, 0x0d00,
+		0x29a0, 0x7730, 0x2950, 0x2a50, 0x0000, 0x0d00,
 		0x1b10, 0x0e60, 0x0e00, 0x0e10, 0x0e20, 0x0e30,
-	        0x7000, 0x7010, 0x7020, 0x7030, 0x7040, 0x3400,
+		0x7000, 0x7010, 0x7020, 0x7030, 0x7040, 0x3400,
 		0x3410, 0x3420, 0x3430, 0x3450, 0x3440, 0x3c00,
-	        0x3c10, 0x3c20, 0x3c30, 0x3c50, 0x3c40, 0x4100,
+		0x3c10, 0x3c20, 0x3c30, 0x3c50, 0x3c40, 0x4100,
 		0x0000, 0x0d10, 0x0000, 0x0000, 0x4160, 0x0c60,
-	        0x0c70, 0x0c80, 0x7580, 0x7590, 0x4170, 0x0000,
+		0x0c70, 0x0c80, 0x7580, 0x7590, 0x4170, 0x0000,
 		0x0890, 0x70a0, 0x70b0, 0x70c0, 0x08d0, 0x08e0,
-	        0x70f0, 0x4050, 0x4200, 0x4210, 0x0000, 0x0880,
+		0x70f0, 0x4050, 0x4200, 0x4210, 0x0000, 0x0880,
 		0x0000, 0x0000, 0x0000, 0x0000, 0x7180, 0x0000
 	};
 	u_int32_t base = (addr & NXMEMMAP_HWTRANS_M) >> 16;
@@ -940,15 +956,13 @@ nxb_writehw(struct nxb_softc *sc, u_int32_t addr, u_int32_t val)
 	if (reg == NXSW_BOOTLD_CONFIG)
 		return (0);
 	else if (reg == NXROMUSB_GLB_SW_RESET) {
-		val = 0x8000ff;
+		val = NXROMUSB_GLB_SW_RESET_XDMA;
 		timo = hz;
 	}
 	nxb_set_window(sc, window);
 	nxb_write(sc, reg, val);
 	nxb_set_window(sc, 1);
-
-	if (tsleep(sc, PCATCH, "nxbcrb", timo) == EINTR)
-		return (-1);
+	delay(timo);
 
 	DPRINTF(NXDBG_CRBINIT, "%s(%s) addr 0x%08x -> reg 0x%08x, "
 	    "val 0x%08x, window %d\n",
@@ -957,6 +971,52 @@ nxb_writehw(struct nxb_softc *sc, u_int32_t addr, u_int32_t val)
 	return (0);
 }
 
+bus_size_t
+nxb_set_pciwindow(struct nxb_softc *sc, bus_size_t reg)
+{
+	int32_t		 window = -1;
+	bus_size_t	 wreg = ~0ULL;
+
+	/*
+	 * Get the correct offset in the mapped PCI space
+	 */
+	if (reg <= NXADDR_DDR_NET_END) {
+		window = (reg >> NXDDR_WINDOW_S) & NXDDR_WINDOW_M;
+		reg -= (window * NXDDR_WINDOW_SIZE);
+		if (sc->sc_ddrwindow != window) {
+			sc->sc_ddrwindow = window;
+			wreg = NXDDR_WINDOW(sc->sc_function);
+		}
+	} else if (reg >= NXADDR_OCM0 && reg <= NXADDR_OCM0_END) {
+		reg -= NXADDR_OCM0;
+		reg += NXPCIMAP_OCM0;
+	} else if (reg >= NXADDR_OCM1 && reg <= NXADDR_OCM1_END) {
+		reg -= NXADDR_OCM1;
+		reg += NXPCIMAP_OCM1;
+	} else if (reg >= NXADDR_QDR_NET && reg <= NXADDR_QDR_NET_END) {
+		reg -= NXADDR_QDR_NET;
+		window = (reg >> NXDDR_WINDOW_S) & NXDDR_WINDOW_M;
+		reg -= (window * NXQDR_WINDOW_SIZE);
+		reg += NXPCIMAP_QDR_NET;
+		if (sc->sc_qdrwindow != window) {
+			sc->sc_qdrwindow = window;
+			wreg = NXQDR_WINDOW(sc->sc_function);
+		}
+	} else
+		reg = ~0ULL;
+
+	/*
+	 * Update the PCI window
+	 */
+	if (wreg != ~0ULL) {
+		nxb_write(sc, wreg, window);
+		(void)nxb_read(sc, wreg);
+		delay(10);
+	}
+
+	return (reg);
+}
+
 void
 nxb_set_window(struct nxb_softc *sc, int window)
 {
@@ -1096,10 +1156,11 @@ nxb_temp_sensor(void *arg)
 		sc->sc_sensor.status = SENSOR_S_CRIT;
 		break;
 	default:
-		sc->sc_sensor.flags = SENSOR_FINVALID;
+		sc->sc_sensor.flags = SENSOR_FUNKNOWN;
+		sc->sc_sensor.status = SENSOR_S_UNSPEC;
 		return;
 	}
-	sc->sc_sensor.value = val * 1000000 + 273150000; 
+	sc->sc_sensor.value = val * 1000000 + 273150000;
 	sc->sc_sensor.flags = 0;
 }
 
@@ -1169,16 +1230,14 @@ nx_attach(struct device *parent, struct device *self, void *aux)
 
 	ifmedia_init(&nx->nx_mii.mii_media, 0,
 	    nx_media_change, nx_media_status);
-	ifmedia_add(&nx->nx_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, NULL);
-	ifmedia_set(&nx->nx_mii.mii_media, IFM_ETHER | IFM_AUTO);
+	ifmedia_add(&nx->nx_mii.mii_media, IFM_ETHER|nxp->nxp_phy, 0, NULL);
+	ifmedia_set(&nx->nx_mii.mii_media, IFM_ETHER|nxp->nxp_phy);
 
 	if_attach(ifp);
 	ether_ifattach(ifp);
 
 	timeout_set(&nx->nx_tick, nx_tick, nx);
 	timeout_add(&nx->nx_tick, hz);
-
-	return;
 }
 
 int
@@ -1220,11 +1279,10 @@ nx_media_status(struct ifnet *ifp, struct ifmediareq *imr)
 
 	switch (nxp->nxp_mode) {
 	case NXNIU_MODE_XGE:
-		imr->ifm_active = IFM_ETHER | IFM_AUTO;
+		imr->ifm_active = IFM_ETHER | nxp->nxp_phy;
 		imr->ifm_status = IFM_AVALID;
 		nx_link_state(nx);
-		if (LINK_STATE_IS_UP(ifp->if_link_state) &&
-		    ifp->if_flags & IFF_UP)
+		if (LINK_STATE_IS_UP(ifp->if_link_state))
 			imr->ifm_status |= IFM_ACTIVE;
 		break;
 	case NXNIU_MODE_GBE:
@@ -1271,8 +1329,8 @@ int
 nx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 {
 	struct nx_softc		*nx = (struct nx_softc *)ifp->if_softc;
-	struct ifaddr		*ifa;
-	struct ifreq		*ifr;
+	struct ifaddr		*ifa = (struct ifaddr *)data;
+	struct ifreq		*ifr = (struct ifreq *)data;
 	int			 s, error = 0;
 
 	s = splnet();
@@ -1284,7 +1342,6 @@ nx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 
 	switch (cmd) {
 	case SIOCSIFADDR:
-		ifa = (struct ifaddr *)data;
 		ifp->if_flags |= IFF_UP;
 #ifdef INET
 		if (ifa->ifa_addr->sa_family == AF_INET)
@@ -1312,7 +1369,6 @@ nx_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
 
 	case SIOCADDMULTI:
 	case SIOCDELMULTI:
-		ifr = (struct ifreq *)data;
 		error = (cmd == SIOCADDMULTI) ?
 		    ether_addmulti(ifr, &nx->nx_ac) :
 		    ether_delmulti(ifr, &nx->nx_ac);
diff --git a/sys/dev/pci/if_nxreg.h b/sys/dev/pci/if_nxreg.h
index 80c7331eae3..e0c65ac59fd 100644
--- a/sys/dev/pci/if_nxreg.h
+++ b/sys/dev/pci/if_nxreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_nxreg.h,v 1.18 2007/05/01 16:25:48 reyk Exp $	*/
+/*	$OpenBSD: if_nxreg.h,v 1.19 2007/05/01 21:56:21 reyk Exp $	*/
 
 /*
  * Copyright (c) 2007 Reyk Floeter <reyk@openbsd.org>
@@ -40,7 +40,11 @@
 #define NX_FIRMWARE_MAJOR	3
 #define NX_FIRMWARE_MINOR	4
 #define NX_FIRMWARE_BUILD	31
-#define NX_FIRMWARE_VER		0x001f0403
+
+#define NX_FIRMWARE_VER		(					\
+	(NX_FIRMWARE_MAJOR << 16) | (NX_FIRMWARE_MINOR << 8) |		\
+	NX_FIRMWARE_BUILD						\
+)
 
 /* Used to indicate various states of the NIC and its firmware */
 enum nx_state {
@@ -141,9 +145,25 @@ struct nx_statusdesc {
 #define NXPCIMEM_SIZE_128MB	0x08000000	/* 128MB size */
 #define NXPCIMEM_SIZE_32MB	0x02000000	/* 32MB size */
 
+/* PCI memory address ranges */
+#define NXADDR_DDR_NET		0x0000000000000000
+#define NXADDR_DDR_NET_END	0x000000000fffffff
+#define NXADDR_PCIE		0x0000000800000000
+#define NXADDR_PCIE_END		0x0000000fffffffff
+#define NXADDR_OCM0		0x0000000200000000
+#define NXADDR_OCM0_END		0x00000002000fffff
+#define NXADDR_OCM1		0x0000000200400000
+#define NXADDR_OCM1_END		0x00000002004fffff
+#define NXADDR_QDR_NET		0x0000000300000000
+#define NXADDR_QDR_NET_END	0x00000003001fffff
+
+/* Memory mapping in the default PCI window */
 #define NXPCIMAP_DDR_NET	0x00000000
 #define NXPCIMAP_DDR_MD		0x02000000
+#define NXPCIMAP_QDR_NET	0x04000000
 #define NXPCIMAP_DIRECT_CRB	0x04400000
+#define NXPCIMAP_OCM0		0x05000000
+#define NXPCIMAP_OCM1		0x05100000
 #define NXPCIMAP_CRB		0x06000000
 
 /* Offsets inside NXPCIMAP_CRB */
@@ -192,7 +212,7 @@ struct nx_statusdesc {
 #define NXFLASHMAP_INFO		0x00004000	/* board configuration */
 #define NXFLASHMAP_INITCODE	0x00006000	/* chipset-specific code */
 #define NXFLASHMAP_BOOTLOADER	0x00010000	/* boot loader */
-#define  NXFLASHMAP_BOOTLDSIZE	1024		/* boot loader size */
+#define  NXFLASHMAP_BOOTLDSIZE	0x4000		/* boot loader size */
 #define NXFLASHMAP_FIRMWARE_0	0x00043000	/* compressed firmware image */
 #define NXFLASHMAP_FIRMWARE_1	0x00200000	/* backup firmware image */
 #define NXFLASHMAP_PXE		0x003d0000	/* PXE image */
@@ -221,7 +241,17 @@ struct nx_statusdesc {
 #define  NXISR_INT_MASK_TARGET0		(1<<7)	/* mask for function 0 */
 #define  NXISR_INT_MASK_RC_INT		(1<<5)	/* root complex mask */
 
-/* SW Window */
+/* Memory windows */
+#define NXDDR_WINDOW(_f)		NXPCIE_FUNC(0x00010200, _f)
+#define  NXDDR_WINDOW_1			(1<<25)	/* Set this flag for Win 1 */
+#define  NXDDR_WINDOW_S			25
+#define  NXDDR_WINDOW_M			0x000003ff
+#define  NXDDR_WINDOW_SIZE		0x02000000
+#define NXQDR_WINDOW(_f)		NXPCIE_FUNC(0x00010208, _f)
+#define  NXQDR_WINDOW_1			(1<<25)	/* Set this flag for Win 1 */
+#define  NXQDR_WINDOW_S			22
+#define  NXQDR_WINDOW_M			0x0000003f
+#define  NXQDR_WINDOW_SIZE		0x00400000
 #define NXCRB_WINDOW(_f)		NXPCIE_FUNC(0x00010210, _f)
 #define  NXCRB_WINDOW_1			(1<<25)	/* Set this flag for Win 1 */
 
@@ -318,37 +348,37 @@ struct nx_statusdesc {
 /* Misc SW registers */
 #define NXSW_CMD_PRODUCER_OFF	NXSW(0x2208)	/* Producer CMD ring index */
 #define NXSW_CMD_CONSUMER_OFF	NXSW(0x220c)	/* Consumer CMD ring index */
-#define NXSW_RCV_PRODUCER_OFF	NXSW(0x2218)	/* Producer Rx ring index */
-#define NXSW_RCV_CONSUMER_OFF	NXSW(0x221c)	/* Consumer Rx ring index */
-#define NXSW_RCV_GLOBAL_RING	NXSW(0x2220)	/* Address of Rx buffer */
-#define NXSW_RCV_STATUS_RING	NXSW(0x2224)	/* Address of Rx status ring */
-#define NXSW_RCV_STATUS_PROD	NXSW(0x2228)	/* Producer Rx status index */
-#define NXSW_RCV_STATUS_CONS	NXSW(0x222c)	/* Consumer Rx status index */
-#define NXSW_CMD_ADDR_HI	NXSW(0x2230)	/* CMD ring phys address */
-#define NXSW_CMD_ADDR_LO	NXSW(0x2234)	/* CMD ring phys address */
-#define NXSW_CMD_RING_SIZE	NXSW(0x2238)	/* Entries in the CMD ring */
-#define NXSW_RCV_RING_SIZE	NXSW(0x223c)	/* Entries in the Rx ring */
-#define NXSW_JRCV_RING_SIZE	NXSW(0x2240)	/* Entries in the jumbo ring */
-#define NXSW_RCVPEG_STATE	NXSW(0x2248)	/* State of the NX2031 */
+#define NXSW_RCV_PRODUCER_OFF	NXSW(0x2300)	/* Producer Rx ring index */
+#define NXSW_RCV_CONSUMER_OFF	NXSW(0x2304)	/* Consumer Rx ring index */
+#define NXSW_RCV_GLOBAL_RING	NXSW(0x2308)	/* Address of Rx buffer */
+#define NXSW_RCV_STATUS_RING	NXSW(0x2360)	/* Address of Rx status ring */
+#define NXSW_RCV_STATUS_PROD	NXSW(0x2364)	/* Producer Rx status index */
+#define NXSW_RCV_STATUS_CONS	NXSW(0x2368)	/* Consumer Rx status index */
+#define NXSW_CMD_ADDR_HI	NXSW(0x2218)	/* CMD ring phys address */
+#define NXSW_CMD_ADDR_LO	NXSW(0x221c)	/* CMD ring phys address */
+#define NXSW_CMD_RING_SIZE	NXSW(0x22c8)	/* Entries in the CMD ring */
+#define NXSW_RCV_RING_SIZE	NXSW(0x230c)	/* Entries in the Rx ring */
+#define NXSW_JRCV_RING_SIZE	NXSW(0x230c)	/* Entries in the jumbo ring */
+#define NXSW_RCVPEG_STATE	NXSW(0x236c)	/* State of the NX2031 */
 #define NXSW_CMDPEG_STATE	NXSW(0x2250)	/* State of the firmware */
 #define  NXSW_CMDPEG_STATE_M	0xffff		/* State mask */
 #define  NXSW_CMDPEG_INIT_START	0xff00		/* Start of initialization */
 #define  NXSW_CMDPEG_INIT_DONE	0xff01		/* Initialization complete */
 #define  NXSW_CMDPEG_INIT_FAIL	0xffff		/* Initialization failed */
-#define NXSW_GLOBAL_INT_COAL	NXSW(0x2280)	/* Interrupt coalescing */
-#define NXSW_INT_COAL_MODE	NXSW(0x2284)	/* Reserved */
-#define NXSW_MAX_RCV_BUFS	NXSW(0x2288)	/* Interrupt tuning register */
-#define NXSW_TX_INT_THRESHOLD	NXSW(0x228c)	/* Interrupt tuning register */
-#define NXSW_RX_PKT_TIMER	NXSW(0x2290)	/* Interrupt tuning register */
-#define NXSW_TX_PKT_TIMER	NXSW(0x2294)	/* Interrupt tuning register */
-#define NXSW_RX_PKT_CNT		NXSW(0x2298)	/* Rx packet count register */
-#define NXSW_RX_TMR_CNT		NXSW(0x229c)	/* Rx timer count register */
-#define NXSW_XG_STATE		NXSW(0x22a0)	/* PHY state register */
+#define NXSW_GLOBAL_INT_COAL	NXSW(0x2264)	/* Interrupt coalescing */
+#define NXSW_INT_COAL_MODE	NXSW(0x2268)	/* Reserved */
+#define NXSW_MAX_RCV_BUFS	NXSW(0x226c)	/* Interrupt tuning register */
+#define NXSW_TX_INT_THRESHOLD	NXSW(0x2270)	/* Interrupt tuning register */
+#define NXSW_RX_PKT_TIMER	NXSW(0x2274)	/* Interrupt tuning register */
+#define NXSW_TX_PKT_TIMER	NXSW(0x2278)	/* Interrupt tuning register */
+#define NXSW_RX_PKT_CNT		NXSW(0x227c)	/* Rx packet count register */
+#define NXSW_RX_TMR_CNT		NXSW(0x2280)	/* Rx timer count register */
+#define NXSW_XG_STATE		NXSW(0x2294)	/* PHY state register */
 #define  NXSW_XG_LINK_UP	(1<<4)		/* 10G PHY state up */
 #define  NXSW_XG_LINK_DOWN	(1<<5)		/* 10G PHY state down */
-#define NXSW_JRCV_PRODUCER_OFF	NXSW(0x2300)	/* Producer jumbo ring index */
-#define NXSW_JRCV_CONSUMER_OFF	NXSW(0x2304)	/* Consumer jumbo ring index */
-#define NXSW_JRCV_GLOBAL_RING	NXSW(0x2220)	/* Address of jumbo buffer */
+#define NXSW_JRCV_PRODUCER_OFF	NXSW(0x22f4)	/* Producer jumbo ring index */
+#define NXSW_JRCV_CONSUMER_OFF	NXSW(0x22f8)	/* Consumer jumbo ring index */
+#define NXSW_JRCV_GLOBAL_RING	NXSW(0x2308)	/* Address of jumbo buffer */
 #define NXSW_TEMP		NXSW(0x23b4)	/* Temperature sensor */
 #define  NXSW_TEMP_STATE_M	0x0000ffff	/* Temp state mask */
 #define  NXSW_TEMP_STATE_S	0		/* Temp state shift */
@@ -398,6 +428,7 @@ struct nx_statusdesc {
 #define  NXROMUSB_GLB_SW_RESET_U0PEG1	(1<<7)	/* Network Pegasus1 reset */
 #define  NXROMUSB_GLB_SW_RESET_U0PEG0	(1<<6)	/* Network Pegasus0 reset */
 #define  NXROMUSB_GLB_SW_RESET_PPE	0xf0	/* Protocol Processing Engine */
+#define  NXROMUSB_GLB_SW_RESET_XDMA	0x8000ff;
 #define NXROMUSB_GLB_SW_RESET_DEF	0xffffffff
 
 /* Casper Reset Register */