diff options
| author |   miod <miod@openbsd.org> | 2014-10-23 16:51:30 +0000 |
|---|---|---|
| committer | miod <miod@openbsd.org> | 2014-10-23 16:51:30 +0000 |
| commit | 5636df3cc62687518690d85aa7ddbbf5840048ad (patch) | |
| tree | 13e26dd1ec6ee99ebec3b5f845c66ceabbbb4dc3 | |
| parent | Revert limiting physmem to 2GB; the culprit was likely in uvm and uvm has (diff) | |
| download | wireguard-openbsd-5636df3cc62687518690d85aa7ddbbf5840048ad.tar.xz wireguard-openbsd-5636df3cc62687518690d85aa7ddbbf5840048ad.zip | |
In the various desidhash_*() functions, make sure we clear the `set to clear'
bit fields with their right sizes (the L2PARERR field on PCXL processors being
4 bits wide, not 1 bit), and make comments consistent accross these functions.
ok kettenis@
| -rw-r--r-- | sys/arch/hppa/hppa/locore.S | 20 |
1 files changed, 13 insertions, 7 deletions
diff --git a/sys/arch/hppa/hppa/locore.S b/sys/arch/hppa/hppa/locore.S index 242345ec935..19e01820bed 100644 --- a/sys/arch/hppa/hppa/locore.S +++ b/sys/arch/hppa/hppa/locore.S @@ -1,4 +1,4 @@ -/* $OpenBSD: locore.S,v 1.191 2014/10/14 17:25:48 miod Exp $ */ +/* $OpenBSD: locore.S,v 1.192 2014/10/23 16:51:30 miod Exp $ */ /* * Copyright (c) 1998-2004 Michael Shalayeff @@ -1840,8 +1840,9 @@ LEAF_ENTRY(desidhash_s) MFCPU_T(DR_CPUCFG,22) nop nop - depi 0, DR0_PCXS_DHE, 3, t1 /* 3 4 DR0_PCXS_DOMAIN|DR0_PCXS_IHE */ + depi 0, DR0_PCXS_DHE, 3, t1 /* 3: DR0_PCXS_DOMAIN|DR0_PCXS_IHE */ depi 1, DR0_PCXS_EQWSTO, 1, t1 + /* clear `write to clear' bits so they don't get reset */ depi 0, DR0_PCXS_DHPMC, 1, t1 depi 0, DR0_PCXS_ILPMC, 1, t1 sync @@ -1866,6 +1867,7 @@ LEAF_ENTRY(desidhash_t) nop depi 0, DR0_PCXT_IHE, 1, t1 depi 0, DR0_PCXT_DHE, 1, t1 + /* clear `write to clear' bits so they don't get reset */ depi 0, DR0_PCXT_DHPMC, 1, t1 depi 0, DR0_PCXT_ILPMC, 1, t1 sync @@ -1957,11 +1959,15 @@ LEAF_ENTRY(desidhash_l) MFCPU_C(DR_CPUCFG,22) /* t1 */ nop nop - depi 0, DR0_PCXL_L2IHASH_EN, 2, t1 /* + DR0_PCXL_L2DHASH_EN */ - depi 0, DR0_PCXL_L2IHPMC, 1, t1 /* don't reset */ - depi 0, DR0_PCXL_L2DHPMC, 1, t1 /* don't reset */ - depi 0, DR0_PCXL_L1IHPMC, 1, t1 /* don't reset */ - depi 0, DR0_PCXL_L2PARERR,1, t1 /* don't reset */ + depi 0, DR0_PCXL_L2IHASH_EN, 2, t1 /* 2: DR0_PCXL_L2DHASH_EN */ +#if 0 /* better trust the PROM if it left some bits set here */ + depi 0, DR0_PCXL_DUAL_DIS, 2, t1 +#endif + /* clear `write to clear' bits so they don't get reset */ + depi 0, DR0_PCXL_L2IHPMC, 1, t1 + depi 0, DR0_PCXL_L2DHPMC, 1, t1 + depi 0, DR0_PCXL_L1IHPMC, 1, t1 + depi 0, DR0_PCXL_L2PARERR, 4, t1 sync MTCPU_C(22,DR_CPUCFG) nop |