Add a bunch of i.MX7 clocks.

2 files changed, 67 insertions, 1 deletions

diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index de062871f4e..69f776fa799 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.5 2018/06/11 09:20:46 kettenis Exp $ */
+/* $OpenBSD: imxccm.c,v 1.6 2018/06/12 20:19:57 kettenis Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -377,6 +377,29 @@ imxccm_get_ipg_perclk(struct imxccm_softc *sc)
 }
 
 uint32_t
+imxccm_imx7d_enet(struct imxccm_softc *sc, uint32_t idx)
+{
+	uint32_t mux;
+
+	if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+		return 0;
+
+	mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+	mux >>= sc->sc_muxs[idx].shift;
+	mux &= sc->sc_muxs[idx].mask;
+
+	switch (mux) {
+	case 0:
+		return clock_get_frequency(sc->sc_node, "osc");
+	case 7:
+		return 392000000; /* pll_sys_pfd4_clk XXX not fixed */
+	default:
+		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+		return 0;
+	}
+}
+
+uint32_t
 imxccm_imx7d_i2c(struct imxccm_softc *sc, uint32_t idx)
 {
 	uint32_t mux;
@@ -675,6 +698,8 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 		}
 	} else if (sc->sc_gates == imx7d_gates) {
 		switch (idx) {
+		case IMX7D_ENET_AXI_ROOT_SRC:
+			return imxccm_imx7d_enet(sc, idx);
 		case IMX7D_I2C1_ROOT_SRC:
 		case IMX7D_I2C2_ROOT_SRC:
 		case IMX7D_I2C3_ROOT_SRC:
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index 5cb0db871c8..112cf838b9c 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -78,6 +78,23 @@ struct imxccm_gate imx6ul_gates[] = {
  * i.MX7D clocks.
  */
 
+#define IMX7D_PLL_ENET_MAIN_125M_CLK	0x2a
+#define IMX7D_ENET_AXI_ROOT_CLK		0x52
+#define IMX7D_ENET_AXI_ROOT_SRC		0x53
+#define IMX7D_ENET_AXI_ROOT_CG		0x54
+#define IMX7D_ENET_AXI_ROOT_DIV		0x55
+#define IMX7D_ENET1_TIME_ROOT_CLK	0xa2
+#define IMX7D_ENET1_TIME_ROOT_SRC	0xa3
+#define IMX7D_ENET1_TIME_ROOT_CG	0xa4
+#define IMX7D_ENET1_TIME_ROOT_DIV	0xa5
+#define IMX7D_ENET2_TIME_ROOT_CLK	0xaa
+#define IMX7D_ENET2_TIME_ROOT_SRC	0xab
+#define IMX7D_ENET2_TIME_ROOT_CG	0xac
+#define IMX7D_ENET2_TIME_ROOT_DIV	0xad
+#define IMX7D_ENET_PHY_REF_ROOT_CLK	0xae
+#define IMX7D_ENET_PHY_REF_ROOT_SRC	0xaf
+#define IMX7D_ENET_PHY_REF_ROOT_CG	0xb0
+#define IMX7D_ENET_PHY_REF_ROOT_DIV	0xb1
 #define IMX7D_USDHC1_ROOT_CLK		0xbe
 #define IMX7D_USDHC1_ROOT_SRC		0xbf
 #define IMX7D_USDHC1_ROOT_CG		0xc0
@@ -134,6 +151,10 @@ struct imxccm_gate imx6ul_gates[] = {
 #define IMX7D_UART7_ROOT_SRC		0xfb
 #define IMX7D_UART7_ROOT_CG		0xfc
 #define IMX7D_UART7_ROOT_DIV		0xfd
+#define IMX7D_ENET_AXI_ROOT_PRE_DIV	0x15a
+#define IMX7D_ENET1_TIME_ROOT_PRE_DIV	0x16a
+#define IMX7D_ENET2_TIME_ROOT_PRE_DIV	0x16c
+#define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV	0x16d
 #define IMX7D_USDHC1_ROOT_PRE_DIV	0x171
 #define IMX7D_USDHC2_ROOT_PRE_DIV	0x172
 #define IMX7D_USDHC3_ROOT_PRE_DIV	0x173
@@ -153,6 +174,10 @@ struct imxccm_gate imx6ul_gates[] = {
 #define IMX7D_USB_PHY2_CLK		0x1a8
 
 struct imxccm_gate imx7d_gates[] = {
+	[IMX7D_ENET_AXI_ROOT_CG] = { 0x8900, 28, IMX7D_ENET_AXI_ROOT_SRC },
+	[IMX7D_ENET1_TIME_ROOT_CG] = { 0xa780, 28, IMX7D_ENET1_TIME_ROOT_SRC },
+	[IMX7D_ENET2_TIME_ROOT_CG] = { 0xa880, 28, IMX7D_ENET2_TIME_ROOT_SRC },
+	[IMX7D_ENET_PHY_REF_ROOT_CG] = { 0xa900, 28, IMX7D_ENET_PHY_REF_ROOT_SRC },
 	[IMX7D_USDHC1_ROOT_CG] = { 0xab00, 28, IMX7D_USDHC1_ROOT_SRC },
 	[IMX7D_USDHC2_ROOT_CG] = { 0xab80, 28, IMX7D_USDHC2_ROOT_SRC },
 	[IMX7D_USDHC3_ROOT_CG] = { 0xabc0, 28, IMX7D_USDHC3_ROOT_SRC },
@@ -167,6 +192,10 @@ struct imxccm_gate imx7d_gates[] = {
 	[IMX7D_UART5_ROOT_CG] = { 0xb180, 28, IMX7D_UART5_ROOT_SRC },
 	[IMX7D_UART6_ROOT_CG] = { 0xb200, 28, IMX7D_UART6_ROOT_SRC },
 	[IMX7D_UART7_ROOT_CG] = { 0xb280, 28, IMX7D_UART7_ROOT_SRC },
+	[IMX7D_ENET_AXI_ROOT_CLK] = { 0x4060, 0, IMX7D_ENET_AXI_ROOT_DIV },
+	[IMX7D_ENET1_TIME_ROOT_CLK] = { 0x44f0, 0, IMX7D_ENET1_TIME_ROOT_DIV },
+	[IMX7D_ENET2_TIME_ROOT_CLK] = { 0x4510, 0, IMX7D_ENET2_TIME_ROOT_DIV },
+	[IMX7D_ENET_PHY_REF_ROOT_CLK] = { 0x4520, 0, IMX7D_ENET_PHY_REF_ROOT_DIV },
 	[IMX7D_USB_CTRL_CLK] = { 0x4680, 0 },
 	[IMX7D_USB_PHY1_CLK] = { 0x46a0, 0 },
 	[IMX7D_USB_PHY2_CLK] = { 0x46b0, 0 },
@@ -187,6 +216,10 @@ struct imxccm_gate imx7d_gates[] = {
 };
 
 struct imxccm_divider imx7d_divs[] = {
+	[IMX7D_ENET_AXI_ROOT_PRE_DIV] = { 0x8900, 16, 0x7, IMX7D_ENET_AXI_ROOT_CG },
+	[IMX7D_ENET1_TIME_ROOT_PRE_DIV] = { 0xa780, 16, 0x7, IMX7D_ENET1_TIME_ROOT_CG },
+	[IMX7D_ENET2_TIME_ROOT_PRE_DIV] = { 0xa880, 16, 0x7, IMX7D_ENET2_TIME_ROOT_CG },
+	[IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = { 0xa900, 16, 0x7, IMX7D_ENET_PHY_REF_ROOT_CG },
 	[IMX7D_USDHC1_ROOT_PRE_DIV] = { 0xab00, 16, 0x7, IMX7D_USDHC1_ROOT_CG },
 	[IMX7D_USDHC2_ROOT_PRE_DIV] = { 0xab80, 16, 0x7, IMX7D_USDHC2_ROOT_CG },
 	[IMX7D_USDHC3_ROOT_PRE_DIV] = { 0xac00, 16, 0x7, IMX7D_USDHC3_ROOT_CG },
@@ -201,6 +234,10 @@ struct imxccm_divider imx7d_divs[] = {
 	[IMX7D_UART5_ROOT_PRE_DIV] = { 0xb180, 16, 0x7, IMX7D_UART5_ROOT_CG },
 	[IMX7D_UART6_ROOT_PRE_DIV] = { 0xb200, 16, 0x7, IMX7D_UART6_ROOT_CG },
 	[IMX7D_UART7_ROOT_PRE_DIV] = { 0xb280, 16, 0x7, IMX7D_UART7_ROOT_CG },
+	[IMX7D_ENET_AXI_ROOT_DIV] = { 0x8900, 0, 0x3f, IMX7D_ENET_AXI_ROOT_PRE_DIV },
+	[IMX7D_ENET1_TIME_ROOT_DIV] = { 0xa780, 0, 0x3f, IMX7D_ENET1_TIME_ROOT_PRE_DIV },
+	[IMX7D_ENET2_TIME_ROOT_DIV] = { 0xa880, 0, 0x3f, IMX7D_ENET2_TIME_ROOT_PRE_DIV },
+	[IMX7D_ENET_PHY_REF_ROOT_DIV] = { 0xa900, 0, 0x3f, IMX7D_ENET_PHY_REF_ROOT_PRE_DIV },
 	[IMX7D_USDHC1_ROOT_DIV] = { 0xab00, 0, 0x3f, IMX7D_USDHC1_ROOT_PRE_DIV },
 	[IMX7D_USDHC2_ROOT_DIV] = { 0xab80, 0, 0x3f, IMX7D_USDHC2_ROOT_PRE_DIV },
 	[IMX7D_USDHC3_ROOT_DIV] = { 0xac00, 0, 0x3f, IMX7D_USDHC3_ROOT_PRE_DIV },
@@ -218,6 +255,10 @@ struct imxccm_divider imx7d_divs[] = {
 };
 
 struct imxccm_mux imx7d_muxs[] = {
+	[IMX7D_ENET_AXI_ROOT_SRC] = { 0x8900, 24, 0x7 },
+	[IMX7D_ENET1_TIME_ROOT_SRC] = { 0xa780, 24, 0x7 },
+	[IMX7D_ENET2_TIME_ROOT_SRC] = { 0xa880, 24, 0x7 },
+	[IMX7D_ENET_PHY_REF_ROOT_SRC] = { 0xa900, 24, 0x7 },
 	[IMX7D_USDHC1_ROOT_SRC] = { 0xab00, 24, 0x7 },
 	[IMX7D_USDHC2_ROOT_SRC] = { 0xab80, 24, 0x7 },
 	[IMX7D_USDHC3_ROOT_SRC] = { 0xac00, 24, 0x7 },