Add support for the i.MX8MP USB clocks.

2 files changed, 88 insertions, 2 deletions

diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index 91253a01350..c245a5317ce 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.23 2020/11/07 21:42:47 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.24 2020/12/18 16:29:57 patrick Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -248,6 +248,7 @@ uint32_t imxccm_imx8mm_ahb(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mm_i2c(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mm_uart(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mm_usdhc(struct imxccm_softc *sc, uint32_t);
+uint32_t imxccm_imx8mp_hsio_axi(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t);
 uint32_t imxccm_imx8mq_ahb(struct imxccm_softc *sc, uint32_t);
@@ -883,6 +884,29 @@ imxccm_imx8mm_usdhc(struct imxccm_softc *sc, uint32_t idx)
 }
 
 uint32_t
+imxccm_imx8mp_hsio_axi(struct imxccm_softc *sc, uint32_t idx)
+{
+	uint32_t mux;
+
+	if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+		return 0;
+
+	mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+	mux >>= sc->sc_muxs[idx].shift;
+	mux &= sc->sc_muxs[idx].mask;
+
+	switch (mux) {
+	case 0:
+		return clock_get_frequency(sc->sc_node, "osc_24m");
+	case 1:
+		return 500 * 1000 * 1000; /* sys2_pll_500m */
+	default:
+		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+		return 0;
+	}
+}
+
+uint32_t
 imxccm_imx8mq_ecspi(struct imxccm_softc *sc, uint32_t idx)
 {
 	uint32_t mux;
@@ -1500,6 +1524,9 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 			case IMX8MP_CLK_ENET_AXI:
 				freq = imxccm_imx8mm_enet(sc, idx);
 				break;
+			case IMX8MP_CLK_AHB:
+				freq = imxccm_imx8mm_ahb(sc, idx);
+				break;
 			case IMX8MP_CLK_I2C1:
 			case IMX8MP_CLK_I2C2:
 			case IMX8MP_CLK_I2C3:
@@ -1519,6 +1546,9 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 			case IMX8MP_CLK_USDHC3:
 				freq = imxccm_imx8mm_usdhc(sc, idx);
 				break;
+			case IMX8MP_CLK_HSIO_AXI:
+				freq = imxccm_imx8mp_hsio_axi(sc, idx);
+				break;
 			default:
 				printf("%s: 0x%08x\n", __func__, idx);
 				return 0;
@@ -1694,6 +1724,13 @@ imxccm_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)
 			parent_freq = imxccm_imx8mm_usdhc(sc, idx);
 			return imxccm_imx8m_set_div(sc, idx, freq, parent_freq);
 		}
+	} else if (sc->sc_divs == imx8mp_divs) {
+		switch (idx) {
+		case IMX8MP_CLK_HSIO_AXI:
+			if (imxccm_get_frequency(sc, cells) != freq)
+				break;
+			return 0;
+		}
 	} else if (sc->sc_divs == imx8mq_divs) {
 		switch (idx) {
 		case IMX8MQ_CLK_ARM:
@@ -1813,6 +1850,25 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
 			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
 			return 0;
 		}
+	} else if (sc->sc_muxs == imx8mp_muxs) {
+		switch (idx) {
+		case IMX8MP_CLK_USB_PHY_REF:
+			if (pidx != IMX8MP_CLK_24M)
+				break;
+			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+			mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);
+			mux |= (0x0 << sc->sc_muxs[idx].shift);
+			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
+			return 0;
+		case IMX8MP_CLK_HSIO_AXI:
+			if (pidx != IMX8MP_SYS_PLL2_500M)
+				break;
+			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+			mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);
+			mux |= (0x1 << sc->sc_muxs[idx].shift);
+			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
+			return 0;
+		}
 	} else if (sc->sc_muxs == imx8mq_muxs) {
 		switch (idx) {
 		case IMX8MQ_CLK_A53_SRC:
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index 8c5da8091f4..8fa68d8acfe 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -477,11 +477,15 @@ struct imxccm_mux imx8mm_muxs[] = {
  * i.MX8MP clocks.
  */
 
+#define IMX8MP_CLK_24M			0x02
 #define IMX8MP_SYS_PLL1_266M		0x36
 #define IMX8MP_SYS_PLL2_100M		0x3a
 #define IMX8MP_SYS_PLL2_125M		0x3b
+#define IMX8MP_SYS_PLL2_500M		0x40
 #define IMX8MP_CLK_ENET_AXI		0x5e
 #define IMX8MP_CLK_NAND_USDHC_BUS	0x5f
+#define IMX8MP_CLK_AHB			0x6b
+#define IMX8MP_CLK_IPG_ROOT		0x6e
 #define IMX8MP_CLK_I2C5			0x79
 #define IMX8MP_CLK_I2C6			0x7a
 #define IMX8MP_CLK_ENET_QOS		0x81
@@ -499,6 +503,9 @@ struct imxccm_mux imx8mm_muxs[] = {
 #define IMX8MP_CLK_UART2		0x8f
 #define IMX8MP_CLK_UART3		0x90
 #define IMX8MP_CLK_UART4		0x91
+#define IMX8MP_CLK_USB_CORE_REF		0x92
+#define IMX8MP_CLK_USB_PHY_REF		0x93
+#define IMX8MP_CLK_USDHC3		0xa9
 #define IMX8MP_CLK_ENET1_ROOT		0xc0
 #define IMX8MP_CLK_I2C1_ROOT		0xcd
 #define IMX8MP_CLK_I2C2_ROOT		0xce
@@ -514,14 +521,18 @@ struct imxccm_mux imx8mm_muxs[] = {
 #define IMX8MP_CLK_UART2_ROOT		0xfc
 #define IMX8MP_CLK_UART3_ROOT		0xfd
 #define IMX8MP_CLK_UART4_ROOT		0xfe
-#define IMX8MP_CLK_USDHC3		0xa9
+#define IMX8MP_CLK_USB_ROOT		0xff
+#define IMX8MP_CLK_USB_PHY_ROOT		0x100
 #define IMX8MP_CLK_USDHC1_ROOT		0x101
 #define IMX8MP_CLK_USDHC2_ROOT		0x102
+#define IMX8MP_CLK_HSIO_ROOT		0x10c
 #define IMX8MP_CLK_USDHC3_ROOT		0x115
+#define IMX8MP_CLK_HSIO_AXI		0x137
 
 struct imxccm_gate imx8mp_gates[] = {
 	[IMX8MP_CLK_ENET_AXI] = { 0x8880, 14 },
 	[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 14 },
+	[IMX8MP_CLK_AHB] = { 0x9000, 14 },
 	[IMX8MP_CLK_I2C5] = { 0xa480, 14 },
 	[IMX8MP_CLK_I2C6] = { 0xa500, 14 },
 	[IMX8MP_CLK_ENET_REF] = { 0xa980, 14 },
@@ -537,6 +548,8 @@ struct imxccm_gate imx8mp_gates[] = {
 	[IMX8MP_CLK_UART2] = { 0xaf80, 14 },
 	[IMX8MP_CLK_UART3] = { 0xb000, 14 },
 	[IMX8MP_CLK_UART4] = { 0xb080, 14 },
+	[IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 14 },
+	[IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 14 },
 	[IMX8MP_CLK_USDHC3] = { 0xbc80, 14 },
 	[IMX8MP_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MP_CLK_ENET_AXI },
 	[IMX8MP_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MP_CLK_I2C1 },
@@ -550,14 +563,20 @@ struct imxccm_gate imx8mp_gates[] = {
 	[IMX8MP_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MP_CLK_UART2 },
 	[IMX8MP_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MP_CLK_UART3 },
 	[IMX8MP_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MP_CLK_UART4 },
+	[IMX8MP_CLK_USB_ROOT] = { 0x44d0, 0 },
+	[IMX8MP_CLK_USB_PHY_ROOT] = { 0x44f0, 0, IMX8MP_CLK_USB_PHY_REF },
 	[IMX8MP_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MP_CLK_USDHC1 },
 	[IMX8MP_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MP_CLK_USDHC2 },
+	[IMX8MP_CLK_HSIO_ROOT] = { 0x45c0, 0, IMX8MP_CLK_IPG_ROOT },
 	[IMX8MP_CLK_USDHC3_ROOT] = { 0x45e0, 0, IMX8MP_CLK_USDHC3 },
+	[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 14 },
 };
 
 struct imxccm_divider imx8mp_divs[] = {
 	[IMX8MP_CLK_ENET_AXI] = { 0x8880, 0, 0x3f },
 	[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f },
+	[IMX8MP_CLK_AHB] = { 0x9000, 0, 0x3f },
+	[IMX8MP_CLK_IPG_ROOT] = { 0x9080, 0, 0x1, IMX8MP_CLK_AHB },
 	[IMX8MP_CLK_I2C5] = { 0xa480, 0, 0x3f },
 	[IMX8MP_CLK_I2C6] = { 0xa500, 0, 0x3f },
 	[IMX8MP_CLK_ENET_REF] = { 0xa980, 0, 0x3f },
@@ -573,12 +592,16 @@ struct imxccm_divider imx8mp_divs[] = {
 	[IMX8MP_CLK_UART2] = { 0xaf80, 0, 0x3f },
 	[IMX8MP_CLK_UART3] = { 0xb000, 0, 0x3f },
 	[IMX8MP_CLK_UART4] = { 0xb080, 0, 0x3f },
+	[IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 0, 0x3f },
+	[IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 0, 0x3f },
 	[IMX8MP_CLK_USDHC3] = { 0xbc80, 0, 0x3f },
+	[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 0, 0x3f },
 };
 
 struct imxccm_divider imx8mp_predivs[] = {
 	[IMX8MP_CLK_ENET_AXI] = { 0x8880, 16, 0x7 },
 	[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 },
+	[IMX8MP_CLK_AHB] = { 0x9000, 16, 0x7 },
 	[IMX8MP_CLK_I2C5] = { 0xa480, 16, 0x7 },
 	[IMX8MP_CLK_I2C6] = { 0xa500, 16, 0x7 },
 	[IMX8MP_CLK_ENET_REF] = { 0xa980, 16, 0x7 },
@@ -594,12 +617,16 @@ struct imxccm_divider imx8mp_predivs[] = {
 	[IMX8MP_CLK_UART2] = { 0xaf80, 16, 0x7 },
 	[IMX8MP_CLK_UART3] = { 0xb000, 16, 0x7 },
 	[IMX8MP_CLK_UART4] = { 0xb080, 16, 0x7 },
+	[IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 16, 0x7 },
+	[IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 16, 0x7 },
 	[IMX8MP_CLK_USDHC3] = { 0xbc80, 16, 0x7 },
+	[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 16, 0x7 },
 };
 
 struct imxccm_mux imx8mp_muxs[] = {
 	[IMX8MP_CLK_ENET_AXI] = { 0x8880, 24, 0x7 },
 	[IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 },
+	[IMX8MP_CLK_AHB] = { 0x9000, 24, 0x7 },
 	[IMX8MP_CLK_I2C5] = { 0xa480, 24, 0x7 },
 	[IMX8MP_CLK_I2C6] = { 0xa500, 24, 0x7 },
 	[IMX8MP_CLK_ENET_REF] = { 0xa980, 24, 0x7 },
@@ -615,7 +642,10 @@ struct imxccm_mux imx8mp_muxs[] = {
 	[IMX8MP_CLK_UART2] = { 0xaf80, 24, 0x7 },
 	[IMX8MP_CLK_UART3] = { 0xb000, 24, 0x7 },
 	[IMX8MP_CLK_UART4] = { 0xb080, 24, 0x7 },
+	[IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 24, 0x7 },
+	[IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 24, 0x7 },
 	[IMX8MP_CLK_USDHC3] = { 0xbc80, 24, 0x7 },
+	[IMX8MP_CLK_HSIO_AXI] = { 0x8400, 24, 0x7 },
 };
 
 /*