diff options
| author |   visa <visa@openbsd.org> | 2016-11-21 13:50:22 +0000 |
|---|---|---|
| committer | visa <visa@openbsd.org> | 2016-11-21 13:50:22 +0000 |
| commit | 5bdf2a7e49fb50ca8e0c1f3d2b39f3f9788ad570 (patch) | |
| tree | 1fe2903a50143ede0fb9f7e1eed39878574589f3 | |
| parent | sync (diff) | |
| download | wireguard-openbsd-5bdf2a7e49fb50ca8e0c1f3d2b39f3f9788ad570.tar.xz wireguard-openbsd-5bdf2a7e49fb50ca8e0c1f3d2b39f3f9788ad570.zip | |
Enabling Loongson 3A bits turned on a code path that uses a MIPS64r2
register on Loongson 2. This causes a boot failure on LS2 because
the CPU does not implement the register. Disable the code on LS2
similarly to mips64 pte.h.
Yeelong boot hang reported and fix tested by matthieu@
| -rw-r--r-- | sys/arch/mips64/mips64/pmap.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/arch/mips64/mips64/pmap.c b/sys/arch/mips64/mips64/pmap.c index f0b5531c4e9..ef4f1f53b40 100644 --- a/sys/arch/mips64/mips64/pmap.c +++ b/sys/arch/mips64/mips64/pmap.c @@ -1,4 +1,4 @@ -/* $OpenBSD: pmap.c,v 1.94 2016/10/19 08:28:20 guenther Exp $ */ +/* $OpenBSD: pmap.c,v 1.95 2016/11/21 13:50:22 visa Exp $ */ /* * Copyright (c) 2001-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -386,7 +386,7 @@ pmap_bootstrap(void) pmap_asid_info[i].pma_asid = MIN_USER_ASID + 1; } -#ifdef CPU_MIPS64R2 +#if defined(CPU_MIPS64R2) && !defined(CPU_LOONGSON2) if (cp0_get_pagegrain() & PGRAIN_XIE) pg_xi = PG_XI; #endif |