1 << 31 cleanup. Eitan Adler pointed out that there has been a

resurrection of the bad idiom in the tree.
sufficient review by miod, kettenis, tedu

47 files changed, 324 insertions, 324 deletions

diff --git a/lib/libc/arch/sparc64/fpu/fpu_div.c b/lib/libc/arch/sparc64/fpu/fpu_div.c
index 46573a9eac2..197ac15b1bd 100644
--- a/lib/libc/arch/sparc64/fpu/fpu_div.c
+++ b/lib/libc/arch/sparc64/fpu/fpu_div.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_div.c,v 1.2 2012/12/05 23:19:59 deraadt Exp $	*/
+/*	$OpenBSD: fpu_div.c,v 1.3 2013/11/26 20:33:07 deraadt Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -139,7 +139,7 @@ __FBSDID("$FreeBSD: src/lib/libc/sparc64/fpu/fpu_div.c,v 1.3 2002/03/22 21:52:58
  *	} while ((bit >>= 1) != 0);
  *	Q[0] = q;
  *	for (i = 1; i < 4; i++) {
- *		q = 0, bit = 1 << 31;
+ *		q = 0, bit = 1U << 31;
  *		do {
  *			D = R - Y;
  *			if (D >= 0) {
@@ -238,7 +238,7 @@ __fpu_div(fe)
 
 #define	WORD(r, i)			/* calculate r->fp_mant[i] */ \
 	q = 0; \
-	bit = 1 << 31; \
+	bit = 1U << 31; \
 	LOOP; \
 	(x)->fp_mant[i] = q
 
diff --git a/lib/libc/arch/sparc64/fpu/fpu_sqrt.c b/lib/libc/arch/sparc64/fpu/fpu_sqrt.c
index bc493af5a87..be0e9d57ea8 100644
--- a/lib/libc/arch/sparc64/fpu/fpu_sqrt.c
+++ b/lib/libc/arch/sparc64/fpu/fpu_sqrt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_sqrt.c,v 1.2 2012/12/05 23:19:59 deraadt Exp $	*/
+/*	$OpenBSD: fpu_sqrt.c,v 1.3 2013/11/26 20:33:07 deraadt Exp $	*/
 
 /*
  * Copyright (c) 1992, 1993
@@ -263,7 +263,7 @@ __fpu_sqrt(fe)
 	 * double x correctly while doing the `known q=1.0'.
 	 *
 	 * We do this one mantissa-word at a time, as noted above, to
-	 * save work.  To avoid `(1 << 31) << 1', we also do the top bit
+	 * save work.  To avoid `(1U << 31) << 1', we also do the top bit
 	 * outside of each per-word loop.
 	 *
 	 * The calculation `t = y + bit' breaks down into `t0 = y0, ...,
@@ -301,7 +301,7 @@ __fpu_sqrt(fe)
 #define t1 tt
 	q = 0;
 	y1 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t1 = bit;
 	FPU_SUBS(d1, x1, t1);
@@ -332,7 +332,7 @@ __fpu_sqrt(fe)
 #define t2 tt
 	q = 0;
 	y2 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t2 = bit;
 	FPU_SUBS(d2, x2, t2);
@@ -365,7 +365,7 @@ __fpu_sqrt(fe)
 #define t3 tt
 	q = 0;
 	y3 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t3 = bit;
 	FPU_SUBS(d3, x3, t3);
diff --git a/lib/libc/rpc/xdr_rec.c b/lib/libc/rpc/xdr_rec.c
index da3d41838bd..e280c1d697c 100644
--- a/lib/libc/rpc/xdr_rec.c
+++ b/lib/libc/rpc/xdr_rec.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: xdr_rec.c,v 1.16 2013/04/17 17:40:35 tedu Exp $ */
+/*	$OpenBSD: xdr_rec.c,v 1.17 2013/11/26 20:33:08 deraadt Exp $ */
 
 /*
  * Copyright (c) 2010, Oracle America, Inc.
@@ -95,7 +95,7 @@ static struct  xdr_ops xdrrec_ops = {
  * meet the needs of xdr and rpc based on tcp.
  */
 
-#define LAST_FRAG ((u_int32_t)(1 << 31))
+#define LAST_FRAG ((u_int32_t)(1U << 31))
 
 typedef struct rec_strm {
 	caddr_t tcp_handle;
diff --git a/sys/arch/arm/include/armreg.h b/sys/arch/arm/include/armreg.h
index a64beda3e79..b14a59bb6e9 100644
--- a/sys/arch/arm/include/armreg.h
+++ b/sys/arch/arm/include/armreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: armreg.h,v 1.13 2013/08/06 23:15:43 jsg Exp $	*/
+/*	$OpenBSD: armreg.h,v 1.14 2013/11/26 20:33:11 deraadt Exp $	*/
 /*	$NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $	*/
 
 /*
@@ -53,7 +53,7 @@
  */
 
 #define PSR_FLAGS 0xf0000000	/* flags */
-#define PSR_N_bit (1 << 31)	/* negative */
+#define PSR_N_bit (1U << 31)	/* negative */
 #define PSR_Z_bit (1 << 30)	/* zero */
 #define PSR_C_bit (1 << 29)	/* carry */
 #define PSR_V_bit (1 << 28)	/* overflow */
diff --git a/sys/arch/armv7/imx/imxccm.c b/sys/arch/armv7/imx/imxccm.c
index 26dcc478a69..ab82ab68f0f 100644
--- a/sys/arch/armv7/imx/imxccm.c
+++ b/sys/arch/armv7/imx/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.2 2013/11/06 19:03:07 syl Exp $ */
+/* $OpenBSD: imxccm.c,v 1.3 2013/11/26 20:33:11 deraadt Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -122,7 +122,7 @@
 #define CCM_ANALOG_PLL_USB2_POWER		(1 << 12)
 #define CCM_ANALOG_PLL_USB2_ENABLE		(1 << 13)
 #define CCM_ANALOG_PLL_USB2_BYPASS		(1 << 16)
-#define CCM_ANALOG_PLL_USB2_LOCK		(1 << 31)
+#define CCM_ANALOG_PLL_USB2_LOCK		(1U << 31)
 #define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK	0x1
 #define CCM_ANALOG_USB2_CHRG_DETECT_CHK_CHRG_B	(1 << 19)
 #define CCM_ANALOG_USB2_CHRG_DETECT_EN_B	(1 << 20)
@@ -133,7 +133,7 @@
 #define CCM_ANALOG_PLL_ENET_BYPASS		(1 << 16)
 #define CCM_ANALOG_PLL_ENET_125M_PCIE		(1 << 19)
 #define CCM_ANALOG_PLL_ENET_100M_SATA		(1 << 20)
-#define CCM_ANALOG_PLL_ENET_LOCK		(1 << 31)
+#define CCM_ANALOG_PLL_ENET_LOCK		(1U << 31)
 #define CCM_ANALOG_PFD_480_PFDx_FRAC(x, y)	(((x) >> ((y) << 3)) & 0x3f)
 #define CCM_ANALOG_PFD_528_PFDx_FRAC(x, y)	(((x) >> ((y) << 3)) & 0x3f)
 #define CCM_PMU_MISC1_LVDSCLK1_CLK_SEL_SATA	(0xB << 0)
diff --git a/sys/arch/armv7/imx/imxehci.c b/sys/arch/armv7/imx/imxehci.c
index a6cd11c699c..393e39cd09f 100644
--- a/sys/arch/armv7/imx/imxehci.c
+++ b/sys/arch/armv7/imx/imxehci.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: imxehci.c,v 1.2 2013/11/06 19:03:07 syl Exp $ */
+/*	$OpenBSD: imxehci.c,v 1.3 2013/11/26 20:33:11 deraadt Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -47,7 +47,7 @@
 #define USBPHY_CTRL_ENUTMILEVEL2	(1 << 14)
 #define USBPHY_CTRL_ENUTMILEVEL3	(1 << 15)
 #define USBPHY_CTRL_CLKGATE		(1 << 30)
-#define USBPHY_CTRL_SFTRST		(1 << 31)
+#define USBPHY_CTRL_SFTRST		(1U << 31)
 
 /* ehci */
 #define EHCI_USBMODE			0x68
diff --git a/sys/arch/armv7/omap/if_cpsw.c b/sys/arch/armv7/omap/if_cpsw.c
index eed4cf6be63..7715d98a000 100644
--- a/sys/arch/armv7/omap/if_cpsw.c
+++ b/sys/arch/armv7/omap/if_cpsw.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: if_cpsw.c,v 1.20 2013/11/15 14:31:52 fgsch Exp $ */
+/* $OpenBSD: if_cpsw.c,v 1.21 2013/11/26 20:33:11 deraadt Exp $ */
 /*	$NetBSD: if_cpsw.c,v 1.3 2013/04/17 14:36:34 bouyer Exp $	*/
 
 /*
@@ -640,7 +640,7 @@ cpsw_mii_wait(struct cpsw_softc * const sc, int reg)
 	u_int tries;
 
 	for(tries = 0; tries < 1000; tries++) {
-		if ((cpsw_read_4(sc, reg) & (1 << 31)) == 0)
+		if ((cpsw_read_4(sc, reg) & (1U << 31)) == 0)
 			return 0;
 		delay(1);
 	}
@@ -656,7 +656,7 @@ cpsw_mii_readreg(struct device *dev, int phy, int reg)
 	if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
 		return 0;
 
-	cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) |
+	cpsw_write_4(sc, MDIOUSERACCESS0, (1U << 31) |
 	    ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16));
 
 	if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
@@ -680,7 +680,7 @@ cpsw_mii_writereg(struct device *dev, int phy, int reg, int val)
 	if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
 		goto out;
 
-	cpsw_write_4(sc, MDIOUSERACCESS0, (1 << 31) | (1 << 30) |
+	cpsw_write_4(sc, MDIOUSERACCESS0, (1U << 31) | (1 << 30) |
 	    ((reg & 0x1F) << 21) | ((phy & 0x1F) << 16) | val);
 
 	if (cpsw_mii_wait(sc, MDIOUSERACCESS0) != 0)
diff --git a/sys/arch/armv7/sunxi/sxiccmu.c b/sys/arch/armv7/sunxi/sxiccmu.c
index 27a471d6ed7..ddfc415dbb5 100644
--- a/sys/arch/armv7/sunxi/sxiccmu.c
+++ b/sys/arch/armv7/sunxi/sxiccmu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sxiccmu.c,v 1.4 2013/11/06 19:03:07 syl Exp $	*/
+/*	$OpenBSD: sxiccmu.c,v 1.5 2013/11/26 20:33:12 deraadt Exp $	*/
 /*
  * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org>
  * Copyright (c) 2013 Artturi Alm
@@ -38,12 +38,12 @@
 #define DPRINTF(x)
 #endif
 
-#define	CCMU_SCLK_GATING		(1 << 31)
+#define	CCMU_SCLK_GATING		(1U << 31)
 #define	CCMU_GET_CLK_DIV_RATIO_N(x)	(((x) >> 16) & 0x03)
 #define	CCMU_GET_CLK_DIV_RATIO_M(x)	((x) & 0x07)
 
 #define	CCMU_PLL6_CFG			0x28
-#define	CCMU_PLL6_EN			(1 << 31)
+#define	CCMU_PLL6_EN			(1U << 31)
 #define	CCMU_PLL6_BYPASS_EN		(1 << 30)
 #define	CCMU_PLL6_SATA_CLK_EN		(1 << 14)
 #define	CCMU_PLL6_FACTOR_N		(31 << 8)
diff --git a/sys/arch/hppa/dev/cpu.c b/sys/arch/hppa/dev/cpu.c
index dd1b3d3aaf6..32b40cfa07f 100644
--- a/sys/arch/hppa/dev/cpu.c
+++ b/sys/arch/hppa/dev/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.39 2011/01/02 20:41:22 kettenis Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.40 2013/11/26 20:33:12 deraadt Exp $	*/
 
 /*
  * Copyright (c) 1998-2003 Michael Shalayeff
@@ -250,12 +250,12 @@ cpu_hatch(void)
 	hppa_ipi_init(ci);
 
 	/* Initialise clock. */
-	mtctl((1 << 31), CR_EIRR);
+	mtctl((1U << 31), CR_EIRR);
 	mfctl(CR_ITMR, itmr);
 	ci->ci_itmr = itmr;
 	itmr += cpu_hzticks;
 	mtctl(itmr, CR_ITMR);
-	ci->ci_mask |= (1 << 31);
+	ci->ci_mask |= (1U << 31);
 
 	/* Enable interrupts. */
 	mtctl(ci->ci_mask, CR_EIEM);
diff --git a/sys/arch/hppa/hppa/intr.c b/sys/arch/hppa/hppa/intr.c
index b685b069e8f..b850fd608cc 100644
--- a/sys/arch/hppa/hppa/intr.c
+++ b/sys/arch/hppa/hppa/intr.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: intr.c,v 1.41 2013/07/12 04:08:26 jsg Exp $	*/
+/*	$OpenBSD: intr.c,v 1.42 2013/11/26 20:33:12 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2002-2004 Michael Shalayeff
@@ -126,7 +126,7 @@ cpu_intr_init(void)
 	mtctl(ci->ci_mask, CR_EIEM);
 	/* ack the unwanted interrupts */
 	mfctl(CR_EIRR, mask);
-	mtctl(mask & (1 << 31), CR_EIRR);
+	mtctl(mask & (1U << 31), CR_EIRR);
 
 	/* in spl*() we trust, clock is started in initclocks() */
 	ci->ci_psw |= PSL_I;
diff --git a/sys/arch/hppa/spmath/dbl_float.h b/sys/arch/hppa/spmath/dbl_float.h
index 871b0e48f40..2e62248f03f 100644
--- a/sys/arch/hppa/spmath/dbl_float.h
+++ b/sys/arch/hppa/spmath/dbl_float.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: dbl_float.h,v 1.11 2006/11/29 10:40:44 mickey Exp $	*/
+/*	$OpenBSD: dbl_float.h,v 1.12 2013/11/26 20:33:12 deraadt Exp $	*/
 /*
   (c) Copyright 1986 HEWLETT-PACKARD COMPANY
   To anyone who acknowledges that this file is provided "AS IS"
@@ -305,8 +305,8 @@
 #define Dbl_setzerop1(dbl_value) Dallp1(dbl_value) = 0
 #define Dbl_setzerop2(dbl_value) Dallp2(dbl_value) = 0
 #define Dbl_setnegativezero(dbl_value) \
-    Dallp1(dbl_value) = 1 << 31; Dallp2(dbl_value) = 0
-#define Dbl_setnegativezerop1(dbl_value) Dallp1(dbl_value) = 1 << 31
+    Dallp1(dbl_value) = 1U << 31; Dallp2(dbl_value) = 0
+#define Dbl_setnegativezerop1(dbl_value) Dallp1(dbl_value) = 1U << 31
 
 /* Use the following macro for both overflow & underflow conditions */
 #define ovfl -
diff --git a/sys/arch/hppa/spmath/sgl_float.h b/sys/arch/hppa/spmath/sgl_float.h
index c4725bbb54b..7f42e05f5db 100644
--- a/sys/arch/hppa/spmath/sgl_float.h
+++ b/sys/arch/hppa/spmath/sgl_float.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: sgl_float.h,v 1.11 2006/11/29 10:40:44 mickey Exp $	*/
+/*	$OpenBSD: sgl_float.h,v 1.12 2013/11/26 20:33:12 deraadt Exp $	*/
 /*
   (c) Copyright 1986 HEWLETT-PACKARD COMPANY
   To anyone who acknowledges that this file is provided "AS IS"
@@ -183,7 +183,7 @@
 #define Sgl_setzero_mantissa(sgl_value) Sall(sgl_value) &= 0xff800000
 #define Sgl_setzero_exponentmantissa(sgl_value)  Sall(sgl_value) &= 0x80000000
 #define Sgl_setzero(sgl_value) Sall(sgl_value) = 0
-#define Sgl_setnegativezero(sgl_value) Sall(sgl_value) = 1 << 31
+#define Sgl_setnegativezero(sgl_value) Sall(sgl_value) = 1U << 31
 
 /* Use following macro for both overflow & underflow conditions */
 #define ovfl -
diff --git a/sys/arch/i386/pci/pciide_gcsc_reg.h b/sys/arch/i386/pci/pciide_gcsc_reg.h
index 1e9a5148505..2609897690b 100644
--- a/sys/arch/i386/pci/pciide_gcsc_reg.h
+++ b/sys/arch/i386/pci/pciide_gcsc_reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pciide_gcsc_reg.h,v 1.1 2009/01/04 10:37:40 jsg Exp $	*/
+/*	$OpenBSD: pciide_gcsc_reg.h,v 1.2 2013/11/26 20:33:13 deraadt Exp $	*/
 /*	$NetBSD: gcscide.c,v 1.6 2007/10/06 07:21:03 xtraeme Exp $	*/
 
 /*-
@@ -55,7 +55,7 @@
  * and data per drive, while Format 0 selects the slowest speed
  * of the two drives.
  */
-#define GCSC_ATAC_PIO_FORMAT		(1 << 31) /* PIO Mode Format 1 */
+#define GCSC_ATAC_PIO_FORMAT		(1U << 31) /* PIO Mode Format 1 */
 /*
  * DMA_SEL (bit 20): sets Ultra DMA mode (if enabled) or Multi-word
  * DMA mode (if disabled).
diff --git a/sys/arch/mips64/mips64/cache_r5k.c b/sys/arch/mips64/mips64/cache_r5k.c
index d27f407682d..c9694b3464c 100644
--- a/sys/arch/mips64/mips64/cache_r5k.c
+++ b/sys/arch/mips64/mips64/cache_r5k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.c,v 1.8 2012/10/03 11:18:23 miod Exp $	*/
+/*	$OpenBSD: cache_r5k.c,v 1.9 2013/11/26 20:33:13 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -81,19 +81,19 @@
 /*
  *  R5000 and RM52xx config register bits.
  */
-#define	CF_5_SE		(1 << 12)	/* Secondary cache enable */
-#define	CF_5_SC		(1 << 17)	/* Secondary cache not present */
-#define	CF_5_SS		(3 << 20)	/* Secondary cache size */
+#define	CF_5_SE		(1U << 12)	/* Secondary cache enable */
+#define	CF_5_SC		(1U << 17)	/* Secondary cache not present */
+#define	CF_5_SS		(3U << 20)	/* Secondary cache size */
 #define	CF_5_SS_AL	20		/* Shift to align */
 
 /*
  *  RM7000 config register bits.
  */
-#define	CF_7_SE		(1 << 3)	/* Secondary cache enable */
-#define	CF_7_SC		(1 << 31)	/* Secondary cache not present */
-#define	CF_7_TE		(1 << 12)	/* Tertiary cache enable */
-#define	CF_7_TC		(1 << 17)	/* Tertiary cache not present */
-#define	CF_7_TS		(3 << 20)	/* Tertiary cache size */
+#define	CF_7_SE		(1U << 3)	/* Secondary cache enable */
+#define	CF_7_SC		(1U << 31)	/* Secondary cache not present */
+#define	CF_7_TE		(1U << 12)	/* Tertiary cache enable */
+#define	CF_7_TC		(1U << 17)	/* Tertiary cache not present */
+#define	CF_7_TS		(3U << 20)	/* Tertiary cache size */
 #define	CF_7_TS_AL	20		/* Shift to align */
 
 
diff --git a/sys/arch/mvme88k/include/m8820x.h b/sys/arch/mvme88k/include/m8820x.h
index 30804b9a6d7..ad1e6269cec 100644
--- a/sys/arch/mvme88k/include/m8820x.h
+++ b/sys/arch/mvme88k/include/m8820x.h
@@ -1,6 +1,6 @@
 #ifndef	_MACHINE_M8820X_H_
 #define	_MACHINE_M8820X_H_
-/*	$OpenBSD: m8820x.h,v 1.16 2011/03/23 16:54:36 pirofti Exp $ */
+/*	$OpenBSD: m8820x.h,v 1.17 2013/11/26 20:33:13 deraadt Exp $ */
 /*
  * Copyright (c) 2004, Miodrag Vallat.
  *
@@ -63,10 +63,10 @@
  * Address masks for MVME188 CMMU configs
  */
 
-#define CMMU_SRAM		(1 << 31)
-#define CMMU_A12_MASK		(1 << 12)
-#define CMMU_A14_MASK		(1 << 14)
-#define CMMU_SRAM_MASK		((1 << 31) | (1 << 30))
+#define CMMU_SRAM		(1U << 31)
+#define CMMU_A12_MASK		(1U << 12)
+#define CMMU_A14_MASK		(1U << 14)
+#define CMMU_SRAM_MASK		((1U << 31) | (1U << 30))
 
 #include <m88k/m8820x.h>
 
diff --git a/sys/arch/sparc/dev/rfx.c b/sys/arch/sparc/dev/rfx.c
index 0e7ac912003..94703fbe316 100644
--- a/sys/arch/sparc/dev/rfx.c
+++ b/sys/arch/sparc/dev/rfx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rfx.c,v 1.15 2013/10/20 20:07:26 miod Exp $	*/
+/*	$OpenBSD: rfx.c,v 1.16 2013/11/26 20:33:14 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2004, Miodrag Vallat.
@@ -490,8 +490,8 @@ rfx_initialize(struct rfx_softc *sc, struct rfx_config *cf)
 			value = letoh32(offset);
 		}
 
-		if (offset & (1 << 31)) {
-			offset = (offset & ~(1 << 31)) - RFX_RAMDAC_ADDR;
+		if (offset & (1U << 31)) {
+			offset = (offset & ~(1U << 31)) - RFX_RAMDAC_ADDR;
 			if (offset < RFX_RAMDAC_SIZE)
 				sc->sc_ramdac[offset] = value >> 24;
 		} else {
diff --git a/sys/arch/sparc/fpu/fpu.c b/sys/arch/sparc/fpu/fpu.c
index 59dd54e7a10..bc7be989315 100644
--- a/sys/arch/sparc/fpu/fpu.c
+++ b/sys/arch/sparc/fpu/fpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu.c,v 1.12 2006/05/14 21:58:05 kettenis Exp $	*/
+/*	$OpenBSD: fpu.c,v 1.13 2013/11/26 20:33:14 deraadt Exp $	*/
 /*	$NetBSD: fpu.c,v 1.6 1997/07/29 10:09:51 fair Exp $	*/
 
 /*
@@ -281,11 +281,11 @@ fpu_execute(fe, instr)
 		goto mov;
 
 	case FNEG >> 2:
-		rs1 = fs->fs_regs[rs2] ^ (1 << 31);
+		rs1 = fs->fs_regs[rs2] ^ (1U << 31);
 		goto mov;
 
 	case FABS >> 2:
-		rs1 = fs->fs_regs[rs2] & ~(1 << 31);
+		rs1 = fs->fs_regs[rs2] & ~(1U << 31);
 	mov:
 		fs->fs_regs[rd] = rs1;
 		fs->fs_fsr = fe->fe_fsr;
diff --git a/sys/arch/sparc/fpu/fpu_div.c b/sys/arch/sparc/fpu/fpu_div.c
index 5afae751aa1..97b67fd0d92 100644
--- a/sys/arch/sparc/fpu/fpu_div.c
+++ b/sys/arch/sparc/fpu/fpu_div.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_div.c,v 1.3 2003/06/02 23:27:54 millert Exp $	*/
+/*	$OpenBSD: fpu_div.c,v 1.4 2013/11/26 20:33:14 deraadt Exp $	*/
 /*	$NetBSD: fpu_div.c,v 1.2 1994/11/20 20:52:38 deraadt Exp $ */
 
 /*
@@ -78,7 +78,7 @@
  *		R *= 2;
  *	for (bit = FP_NMANT; --bit >= 0; R *= 2) {
  *		if (R >= Y) {
- *			Q |= 1 << bit;
+ *			Q |= 1U << bit;
  *			R -= Y;
  *		}
  *	}
@@ -129,7 +129,7 @@
  *	} while ((bit >>= 1) != 0);
  *	Q[0] = q;
  *	for (i = 1; i < 4; i++) {
- *		q = 0, bit = 1 << 31;
+ *		q = 0, bit = 1U << 31;
  *		do {
  *			D = R - Y;
  *			if (D >= 0) {
@@ -228,7 +228,7 @@ fpu_div(fe)
 
 #define	WORD(r, i)			/* calculate r->fp_mant[i] */ \
 	q = 0; \
-	bit = 1 << 31; \
+	bit = 1U << 31; \
 	LOOP; \
 	(x)->fp_mant[i] = q
 
diff --git a/sys/arch/sparc/fpu/fpu_sqrt.c b/sys/arch/sparc/fpu/fpu_sqrt.c
index 53a786e623a..96f4d68caae 100644
--- a/sys/arch/sparc/fpu/fpu_sqrt.c
+++ b/sys/arch/sparc/fpu/fpu_sqrt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_sqrt.c,v 1.3 2003/06/02 23:27:54 millert Exp $	*/
+/*	$OpenBSD: fpu_sqrt.c,v 1.4 2013/11/26 20:33:14 deraadt Exp $	*/
 /*	$NetBSD: fpu_sqrt.c,v 1.2 1994/11/20 20:52:46 deraadt Exp $ */
 
 /*
@@ -254,7 +254,7 @@ fpu_sqrt(fe)
 	 * double x correctly while doing the `known q=1.0'.
 	 *
 	 * We do this one mantissa-word at a time, as noted above, to
-	 * save work.  To avoid `(1 << 31) << 1', we also do the top bit
+	 * save work.  To avoid `(1U << 31) << 1', we also do the top bit
 	 * outside of each per-word loop.
 	 *
 	 * The calculation `t = y + bit' breaks down into `t0 = y0, ...,
@@ -292,7 +292,7 @@ fpu_sqrt(fe)
 #define t1 tt
 	q = 0;
 	y1 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t1 = bit;
 	FPU_SUBS(d1, x1, t1);
@@ -323,7 +323,7 @@ fpu_sqrt(fe)
 #define t2 tt
 	q = 0;
 	y2 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t2 = bit;
 	FPU_SUBS(d2, x2, t2);
@@ -356,7 +356,7 @@ fpu_sqrt(fe)
 #define t3 tt
 	q = 0;
 	y3 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t3 = bit;
 	FPU_SUBS(d3, x3, t3);
diff --git a/sys/arch/sparc64/fpu/fpu.c b/sys/arch/sparc64/fpu/fpu.c
index c82af1be713..2a9b7f10ff8 100644
--- a/sys/arch/sparc64/fpu/fpu.c
+++ b/sys/arch/sparc64/fpu/fpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu.c,v 1.17 2011/07/11 15:40:47 guenther Exp $	*/
+/*	$OpenBSD: fpu.c,v 1.18 2013/11/26 20:33:15 deraadt Exp $	*/
 /*	$NetBSD: fpu.c,v 1.11 2000/12/06 01:47:50 mrg Exp $ */
 
 /*
@@ -499,7 +499,7 @@ fpu_insn_fabs(fs, fe, instr)
 	if ((rd = fpu_regoffset(instr.i_opf.i_rd, rtype)) < 0)
 		return (NOTFPU);
 	fpu_fcopy(fs->fs_regs + rs, fs->fs_regs + rd, rtype);
-	fs->fs_regs[rd] = fs->fs_regs[rd] & ~(1 << 31);
+	fs->fs_regs[rd] = fs->fs_regs[rd] & ~(1U << 31);
 	fs->fs_fsr = fe->fe_fsr;
 	return (0);
 }
@@ -523,7 +523,7 @@ fpu_insn_fneg(fs, fe, instr)
 	if ((rd = fpu_regoffset(instr.i_opf.i_rd, rtype)) < 0)
 		return (NOTFPU);
 	fpu_fcopy(fs->fs_regs + rs, fs->fs_regs + rd, rtype);
-	fs->fs_regs[rd] = fs->fs_regs[rd] ^ (1 << 31);
+	fs->fs_regs[rd] = fs->fs_regs[rd] ^ (1U << 31);
 	fs->fs_fsr = fe->fe_fsr;
 	return (0);
 }
diff --git a/sys/arch/sparc64/fpu/fpu_div.c b/sys/arch/sparc64/fpu/fpu_div.c
index dce066765c5..9e02cb57e03 100644
--- a/sys/arch/sparc64/fpu/fpu_div.c
+++ b/sys/arch/sparc64/fpu/fpu_div.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_div.c,v 1.2 2003/06/02 23:27:55 millert Exp $	*/
+/*	$OpenBSD: fpu_div.c,v 1.3 2013/11/26 20:33:15 deraadt Exp $	*/
 /*	$NetBSD: fpu_div.c,v 1.2 1994/11/20 20:52:38 deraadt Exp $ */
 
 /*
@@ -129,7 +129,7 @@
  *	} while ((bit >>= 1) != 0);
  *	Q[0] = q;
  *	for (i = 1; i < 4; i++) {
- *		q = 0, bit = 1 << 31;
+ *		q = 0, bit = 1U << 31;
  *		do {
  *			D = R - Y;
  *			if (D >= 0) {
@@ -228,7 +228,7 @@ fpu_div(fe)
 
 #define	WORD(r, i)			/* calculate r->fp_mant[i] */ \
 	q = 0; \
-	bit = 1 << 31; \
+	bit = 1U << 31; \
 	LOOP; \
 	(x)->fp_mant[i] = q
 
diff --git a/sys/arch/sparc64/fpu/fpu_sqrt.c b/sys/arch/sparc64/fpu/fpu_sqrt.c
index c8c1df9d876..720759b78de 100644
--- a/sys/arch/sparc64/fpu/fpu_sqrt.c
+++ b/sys/arch/sparc64/fpu/fpu_sqrt.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: fpu_sqrt.c,v 1.2 2003/06/02 23:27:55 millert Exp $	*/
+/*	$OpenBSD: fpu_sqrt.c,v 1.3 2013/11/26 20:33:15 deraadt Exp $	*/
 /*	$NetBSD: fpu_sqrt.c,v 1.2 1994/11/20 20:52:46 deraadt Exp $ */
 
 /*
@@ -254,7 +254,7 @@ fpu_sqrt(fe)
 	 * double x correctly while doing the `known q=1.0'.
 	 *
 	 * We do this one mantissa-word at a time, as noted above, to
-	 * save work.  To avoid `(1 << 31) << 1', we also do the top bit
+	 * save work.  To avoid `(1U << 31) << 1', we also do the top bit
 	 * outside of each per-word loop.
 	 *
 	 * The calculation `t = y + bit' breaks down into `t0 = y0, ...,
@@ -292,7 +292,7 @@ fpu_sqrt(fe)
 #define t1 tt
 	q = 0;
 	y1 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t1 = bit;
 	FPU_SUBS(d1, x1, t1);
@@ -323,7 +323,7 @@ fpu_sqrt(fe)
 #define t2 tt
 	q = 0;
 	y2 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t2 = bit;
 	FPU_SUBS(d2, x2, t2);
@@ -356,7 +356,7 @@ fpu_sqrt(fe)
 #define t3 tt
 	q = 0;
 	y3 = 0;
-	bit = 1 << 31;
+	bit = 1U << 31;
 	EVEN_DOUBLE;
 	t3 = bit;
 	FPU_SUBS(d3, x3, t3);
diff --git a/sys/dev/ic/bwireg.h b/sys/dev/ic/bwireg.h
index dd0682bdaf9..b14304450c4 100644
--- a/sys/dev/ic/bwireg.h
+++ b/sys/dev/ic/bwireg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bwireg.h,v 1.7 2007/11/17 16:50:02 mglocker Exp $	*/
+/*	$OpenBSD: bwireg.h,v 1.8 2013/11/26 20:33:15 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
@@ -150,23 +150,23 @@
 #define BWI_TXRX_INTR_MASK(i)		(BWI_TXRX_INTR_MASK_BASE + ((i) * 8))
 
 #define BWI_MAC_STATUS			0x00000120
-#define BWI_MAC_STATUS_ENABLE		(1 << 0)
-#define BWI_MAC_STATUS_UCODE_START	(1 << 1)
-#define BWI_MAC_STATUS_UCODE_JUMP0	(1 << 2)
-#define BWI_MAC_STATUS_IHREN		(1 << 10)
-#define BWI_MAC_STATUS_GPOSEL_MASK	(3 << 14)
-#define BWI_MAC_STATUS_BSWAP		(1 << 16)
-#define BWI_MAC_STATUS_INFRA		(1 << 17)
-#define BWI_MAC_STATUS_OPMODE_HOSTAP	(1 << 18)
-#define BWI_MAC_STATUS_RFLOCK		(1 << 19)
-#define BWI_MAC_STATUS_PASS_BCN		(1 << 20)
-#define BWI_MAC_STATUS_PASS_BADPLCP	(1 << 21)
-#define BWI_MAC_STATUS_PASS_CTL		(1 << 22)
-#define BWI_MAC_STATUS_PASS_BADFCS	(1 << 23)
-#define BWI_MAC_STATUS_PROMISC		(1 << 24)
-#define BWI_MAC_STATUS_HW_PS		(1 << 25)
-#define BWI_MAC_STATUS_WAKEUP		(1 << 26)
-#define BWI_MAC_STATUS_PHYLNK		(1 << 31)
+#define BWI_MAC_STATUS_ENABLE		(1U << 0)
+#define BWI_MAC_STATUS_UCODE_START	(1U << 1)
+#define BWI_MAC_STATUS_UCODE_JUMP0	(1U << 2)
+#define BWI_MAC_STATUS_IHREN		(1U << 10)
+#define BWI_MAC_STATUS_GPOSEL_MASK	(3U << 14)
+#define BWI_MAC_STATUS_BSWAP		(1U << 16)
+#define BWI_MAC_STATUS_INFRA		(1U << 17)
+#define BWI_MAC_STATUS_OPMODE_HOSTAP	(1U << 18)
+#define BWI_MAC_STATUS_RFLOCK		(1U << 19)
+#define BWI_MAC_STATUS_PASS_BCN		(1U << 20)
+#define BWI_MAC_STATUS_PASS_BADPLCP	(1U << 21)
+#define BWI_MAC_STATUS_PASS_CTL		(1U << 22)
+#define BWI_MAC_STATUS_PASS_BADFCS	(1U << 23)
+#define BWI_MAC_STATUS_PROMISC		(1U << 24)
+#define BWI_MAC_STATUS_HW_PS		(1U << 25)
+#define BWI_MAC_STATUS_WAKEUP		(1U << 26)
+#define BWI_MAC_STATUS_PHYLNK		(1U << 31)
 
 #define BWI_MAC_INTR_STATUS		0x00000128
 #define BWI_MAC_INTR_MASK		0x0000012c
diff --git a/sys/dev/ic/bwivar.h b/sys/dev/ic/bwivar.h
index d00a147dbc7..aa77d03f780 100644
--- a/sys/dev/ic/bwivar.h
+++ b/sys/dev/ic/bwivar.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bwivar.h,v 1.27 2013/11/14 12:10:05 dlg Exp $	*/
+/*	$OpenBSD: bwivar.h,v 1.28 2013/11/26 20:33:15 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
@@ -111,7 +111,7 @@ struct bwi_desc32 {
 #define BWI_DESC32_C_EOR		(1 << 28)
 #define BWI_DESC32_C_INTR		(1 << 29)
 #define BWI_DESC32_C_FRAME_END		(1 << 30)
-#define BWI_DESC32_C_FRAME_START	(1 << 31)
+#define BWI_DESC32_C_FRAME_START	(1U << 31)
 
 struct bwi_desc64 {
 	/* Little endian */
diff --git a/sys/dev/ic/rt2560reg.h b/sys/dev/ic/rt2560reg.h
index faf478e0ca0..3a11d165537 100644
--- a/sys/dev/ic/rt2560reg.h
+++ b/sys/dev/ic/rt2560reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rt2560reg.h,v 1.5 2006/11/13 20:06:38 damien Exp $  */
+/*	$OpenBSD: rt2560reg.h,v 1.6 2013/11/26 20:33:16 deraadt Exp $  */
 
 /*-
  * Copyright (c) 2005, 2006
@@ -260,10 +260,10 @@ struct rt2560_rx_desc {
 #define RT2560_RF1_AUTOTUNE	0x08000
 #define RT2560_RF3_AUTOTUNE	0x00040
 
-#define RT2560_BBP_BUSY		(1 << 15)
-#define RT2560_BBP_WRITE	(1 << 16)
-#define RT2560_RF_20BIT		(20 << 24)
-#define RT2560_RF_BUSY		(1 << 31)
+#define RT2560_BBP_BUSY		(1U << 15)
+#define RT2560_BBP_WRITE	(1U << 16)
+#define RT2560_RF_20BIT		(20U << 24)
+#define RT2560_RF_BUSY		(1U << 31)
 
 #define RT2560_RF_2522	0x00
 #define RT2560_RF_2523	0x01
diff --git a/sys/dev/ic/rt2661reg.h b/sys/dev/ic/rt2661reg.h
index 8822fc5e5cf..43de6b2fc4a 100644
--- a/sys/dev/ic/rt2661reg.h
+++ b/sys/dev/ic/rt2661reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rt2661reg.h,v 1.12 2012/08/23 10:34:25 stsp Exp $	*/
+/*	$OpenBSD: rt2661reg.h,v 1.13 2013/11/26 20:33:16 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2006
@@ -182,8 +182,8 @@
 #define RT2661_BBP_BUSY	(1 << 16)
 
 /* possible flags for register PHY_CSR4 */
-#define RT2661_RF_21BIT	(21 << 24)
-#define RT2661_RF_BUSY	(1 << 31)
+#define RT2661_RF_21BIT	(21U << 24)
+#define RT2661_RF_BUSY	(1U << 31)
 
 /* possible values for register STA_CSR4 */
 #define RT2661_TX_STAT_VALID	(1 << 0)
diff --git a/sys/dev/ic/rt2860reg.h b/sys/dev/ic/rt2860reg.h
index dec490802c7..2d38db24155 100644
--- a/sys/dev/ic/rt2860reg.h
+++ b/sys/dev/ic/rt2860reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rt2860reg.h,v 1.30 2010/05/10 18:17:10 damien Exp $	*/
+/*	$OpenBSD: rt2860reg.h,v 1.31 2013/11/26 20:33:16 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2007
@@ -255,10 +255,10 @@
 #define RT2860_TX_DMA_EN		(1 << 0)
 
 /* possible flags for register DELAY_INT_CFG */
-#define RT2860_TXDLY_INT_EN		(1 << 31)
+#define RT2860_TXDLY_INT_EN		(1U << 31)
 #define RT2860_TXMAX_PINT_SHIFT		24
 #define RT2860_TXMAX_PTIME_SHIFT	16
-#define RT2860_RXDLY_INT_EN		(1 << 15)
+#define RT2860_RXDLY_INT_EN		(1U << 15)
 #define RT2860_RXMAX_PINT_SHIFT		8
 #define RT2860_RXMAX_PTIME_SHIFT	0
 
@@ -267,16 +267,16 @@
 #define RT2860_GPIO_O_SHIFT	0
 
 /* possible flags for register USB_DMA_CFG */
-#define RT2860_USB_TX_BUSY		(1 << 31)
-#define RT2860_USB_RX_BUSY		(1 << 30)
+#define RT2860_USB_TX_BUSY		(1U << 31)
+#define RT2860_USB_RX_BUSY		(1U << 30)
 #define RT2860_USB_EPOUT_VLD_SHIFT	24
-#define RT2860_USB_TX_EN		(1 << 23)
-#define RT2860_USB_RX_EN		(1 << 22)
-#define RT2860_USB_RX_AGG_EN		(1 << 21)
-#define RT2860_USB_TXOP_HALT		(1 << 20)
-#define RT2860_USB_TX_CLEAR		(1 << 19)
-#define RT2860_USB_PHY_WD_EN		(1 << 16)
-#define RT2860_USB_PHY_MAN_RST		(1 << 15)
+#define RT2860_USB_TX_EN		(1U << 23)
+#define RT2860_USB_RX_EN		(1U << 22)
+#define RT2860_USB_RX_AGG_EN		(1U << 21)
+#define RT2860_USB_TXOP_HALT		(1U << 20)
+#define RT2860_USB_TX_CLEAR		(1U << 19)
+#define RT2860_USB_PHY_WD_EN		(1U << 16)
+#define RT2860_USB_PHY_MAN_RST		(1U << 15)
 #define RT2860_USB_RX_AGG_LMT(x)	((x) << 8)	/* in unit of 1KB */
 #define RT2860_USB_RX_AGG_TO(x)		((x) & 0xff)	/* in unit of 33ns */
 
@@ -367,9 +367,9 @@
 #define RT2860_TX0Q_PCNT_MASK	0x000000ff
 
 /* possible flags for register CAP_CTRL */
-#define RT2860_CAP_ADC_FEQ		(1 << 31)
-#define RT2860_CAP_START		(1 << 30)
-#define RT2860_MAN_TRIG			(1 << 29)
+#define RT2860_CAP_ADC_FEQ		(1U << 31)
+#define RT2860_CAP_START		(1U << 30)
+#define RT2860_MAN_TRIG			(1U << 29)
 #define RT2860_TRIG_OFFSET_SHIFT	16
 #define RT2860_START_ADDR_SHIFT		0
 
@@ -378,8 +378,8 @@
 #define RT3070_RF_WRITE		(1 << 16)
 
 /* possible flags for register EFUSE_CTRL */
-#define RT3070_SEL_EFUSE	(1 << 31)
-#define RT3070_EFSROM_KICK	(1 << 30)
+#define RT3070_SEL_EFUSE	(1U << 31)
+#define RT3070_EFSROM_KICK	(1U << 30)
 #define RT3070_EFSROM_AIN_MASK	0x03ff0000
 #define RT3070_EFSROM_AIN_SHIFT	16
 #define RT3070_EFSROM_MODE_MASK	0x000000c0
@@ -417,9 +417,9 @@
 #define RT2860_BBP_DATA_SHIFT		0
 
 /* possible flags for register RF_CSR_CFG0 */
-#define RT2860_RF_REG_CTRL		(1 << 31)
-#define RT2860_RF_LE_SEL1		(1 << 30)
-#define RT2860_RF_LE_STBY		(1 << 29)
+#define RT2860_RF_REG_CTRL		(1U << 31)
+#define RT2860_RF_LE_SEL1		(1U << 30)
+#define RT2860_RF_LE_STBY		(1U << 29)
 #define RT2860_RF_REG_WIDTH_SHIFT	24
 #define RT2860_RF_REG_0_SHIFT		0
 
@@ -452,9 +452,9 @@
 #define RT2860_SLOT_TIME		0
 
 /* possible flags for register NAV_TIME_CFG */
-#define RT2860_NAV_UPD			(1 << 31)
+#define RT2860_NAV_UPD			(1U << 31)
 #define RT2860_NAV_UPD_VAL_SHIFT	16
-#define RT2860_NAV_CLR_EN		(1 << 15)
+#define RT2860_NAV_CLR_EN		(1U << 15)
 #define RT2860_NAV_TIMER_SHIFT		0
 
 /* possible flags for register CH_TIME_CFG */
@@ -506,37 +506,37 @@
 #define RT2860_WAKEUP_LEAD_TIME_SHIFT	0
 
 /* possible flags for register TX_PIN_CFG */
-#define RT3593_LNA_PE_G2_POL	(1 << 31)
-#define RT3593_LNA_PE_A2_POL	(1 << 30)
-#define RT3593_LNA_PE_G2_EN	(1 << 29)
-#define RT3593_LNA_PE_A2_EN	(1 << 28)
+#define RT3593_LNA_PE_G2_POL	(1U << 31)
+#define RT3593_LNA_PE_A2_POL	(1U << 30)
+#define RT3593_LNA_PE_G2_EN	(1U << 29)
+#define RT3593_LNA_PE_A2_EN	(1U << 28)
 #define RT3593_LNA_PE2_EN	(RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN)
-#define RT3593_PA_PE_G2_POL	(1 << 27)
-#define RT3593_PA_PE_A2_POL	(1 << 26)
-#define RT3593_PA_PE_G2_EN	(1 << 25)
-#define RT3593_PA_PE_A2_EN	(1 << 24)
-#define RT2860_TRSW_POL		(1 << 19)
-#define RT2860_TRSW_EN		(1 << 18)
-#define RT2860_RFTR_POL		(1 << 17)
-#define RT2860_RFTR_EN		(1 << 16)
-#define RT2860_LNA_PE_G1_POL	(1 << 15)
-#define RT2860_LNA_PE_A1_POL	(1 << 14)
-#define RT2860_LNA_PE_G0_POL	(1 << 13)
-#define RT2860_LNA_PE_A0_POL	(1 << 12)
-#define RT2860_LNA_PE_G1_EN	(1 << 11)
-#define RT2860_LNA_PE_A1_EN	(1 << 10)
+#define RT3593_PA_PE_G2_POL	(1U << 27)
+#define RT3593_PA_PE_A2_POL	(1U << 26)
+#define RT3593_PA_PE_G2_EN	(1U << 25)
+#define RT3593_PA_PE_A2_EN	(1U << 24)
+#define RT2860_TRSW_POL		(1U << 19)
+#define RT2860_TRSW_EN		(1U << 18)
+#define RT2860_RFTR_POL		(1U << 17)
+#define RT2860_RFTR_EN		(1U << 16)
+#define RT2860_LNA_PE_G1_POL	(1U << 15)
+#define RT2860_LNA_PE_A1_POL	(1U << 14)
+#define RT2860_LNA_PE_G0_POL	(1U << 13)
+#define RT2860_LNA_PE_A0_POL	(1U << 12)
+#define RT2860_LNA_PE_G1_EN	(1U << 11)
+#define RT2860_LNA_PE_A1_EN	(1U << 10)
 #define RT2860_LNA_PE1_EN	(RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN)
-#define RT2860_LNA_PE_G0_EN	(1 <<  9)
-#define RT2860_LNA_PE_A0_EN	(1 <<  8)
+#define RT2860_LNA_PE_G0_EN	(1U <<  9)
+#define RT2860_LNA_PE_A0_EN	(1U <<  8)
 #define RT2860_LNA_PE0_EN	(RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN)
-#define RT2860_PA_PE_G1_POL	(1 <<  7)
-#define RT2860_PA_PE_A1_POL	(1 <<  6)
-#define RT2860_PA_PE_G0_POL	(1 <<  5)
-#define RT2860_PA_PE_A0_POL	(1 <<  4)
-#define RT2860_PA_PE_G1_EN	(1 <<  3)
-#define RT2860_PA_PE_A1_EN	(1 <<  2)
-#define RT2860_PA_PE_G0_EN	(1 <<  1)
-#define RT2860_PA_PE_A0_EN	(1 <<  0)
+#define RT2860_PA_PE_G1_POL	(1U <<  7)
+#define RT2860_PA_PE_A1_POL	(1U <<  6)
+#define RT2860_PA_PE_G0_POL	(1U <<  5)
+#define RT2860_PA_PE_A0_POL	(1U <<  4)
+#define RT2860_PA_PE_G1_EN	(1U <<  3)
+#define RT2860_PA_PE_A1_EN	(1U <<  2)
+#define RT2860_PA_PE_G0_EN	(1U <<  1)
+#define RT2860_PA_PE_A0_EN	(1U <<  0)
 
 /* possible flags for register TX_BAND_CFG */
 #define RT2860_5G_BAND_SEL_N	(1 << 2)
diff --git a/sys/dev/ic/rtsxreg.h b/sys/dev/ic/rtsxreg.h
index d2260c328a8..d0f232386d3 100644
--- a/sys/dev/ic/rtsxreg.h
+++ b/sys/dev/ic/rtsxreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rtsxreg.h,v 1.2 2013/11/06 13:51:02 stsp Exp $	*/
+/*	$OpenBSD: rtsxreg.h,v 1.3 2013/11/26 20:33:16 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2006 Uwe Stuehler <uwe@openbsd.org>
@@ -23,31 +23,31 @@
 /* Host command buffer control register. */
 #define	RTSX_HCBAR		0x00
 #define	RTSX_HCBCTLR		0x04
-#define	RTSX_START_CMD		(1 << 31)
-#define	RTSX_HW_AUTO_RSP	(1 << 30)
-#define	RTSX_STOP_CMD		(1 << 28)
+#define	RTSX_START_CMD		(1U << 31)
+#define	RTSX_HW_AUTO_RSP	(1U << 30)
+#define	RTSX_STOP_CMD		(1U << 28)
 
 /* Host data buffer control register. */
 #define	RTSX_HDBAR		0x08
 #define	RTSX_HDBCTLR		0x0C
-#define	RTSX_TRIG_DMA		(1 << 31)
-#define	RTSX_DMA_READ		(1 << 29)
-#define	RTSX_STOP_DMA		(1 << 28)
-#define	RTSX_ADMA_MODE		(2 << 26)
+#define	RTSX_TRIG_DMA		(1U << 31)
+#define	RTSX_DMA_READ		(1U << 29)
+#define	RTSX_STOP_DMA		(1U << 28)
+#define	RTSX_ADMA_MODE		(2U << 26)
 
 /* Interrupt pending register. */
 #define	RTSX_BIPR		0x14
-#define	RTSX_CMD_DONE_INT	(1 << 31)
-#define	RTSX_DATA_DONE_INT	(1 << 30)
-#define	RTSX_TRANS_OK_INT	(1 << 29)
-#define	RTSX_TRANS_FAIL_INT	(1 << 28)
-#define	RTSX_XD_INT		(1 << 27)
-#define	RTSX_MS_INT		(1 << 26)
-#define	RTSX_SD_INT		(1 << 25)
-#define	RTSX_SD_WRITE_PROTECT	(1 << 19)
-#define	RTSX_XD_EXIST		(1 << 18)
-#define	RTSX_MS_EXIST		(1 << 17)
-#define	RTSX_SD_EXIST		(1 << 16)
+#define	RTSX_CMD_DONE_INT	(1U << 31)
+#define	RTSX_DATA_DONE_INT	(1U << 30)
+#define	RTSX_TRANS_OK_INT	(1U << 29)
+#define	RTSX_TRANS_FAIL_INT	(1U << 28)
+#define	RTSX_XD_INT		(1U << 27)
+#define	RTSX_MS_INT		(1U << 26)
+#define	RTSX_SD_INT		(1U << 25)
+#define	RTSX_SD_WRITE_PROTECT	(1U << 19)
+#define	RTSX_XD_EXIST		(1U << 18)
+#define	RTSX_MS_EXIST		(1U << 17)
+#define	RTSX_SD_EXIST		(1U << 16)
 #define	RTSX_CARD_EXIST		(RTSX_XD_EXIST|RTSX_MS_EXIST|RTSX_SD_EXIST)
 #define	RTSX_CARD_INT		(RTSX_XD_INT|RTSX_MS_INT|RTSX_SD_INT)
 
@@ -58,16 +58,16 @@
 
 /* Interrupt enable register. */
 #define	RTSX_BIER		0x18
-#define	RTSX_CMD_DONE_INT_EN	(1 << 31)
-#define	RTSX_DATA_DONE_INT_EN	(1 << 30)
-#define	RTSX_TRANS_OK_INT_EN	(1 << 29)
-#define	RTSX_TRANS_FAIL_INT_EN	(1 << 28)
-#define	RTSX_XD_INT_EN		(1 << 27)
-#define	RTSX_MS_INT_EN		(1 << 26)
-#define	RTSX_SD_INT_EN		(1 << 25)
-#define	RTSX_GPIO0_INT_EN	(1 << 24)
-#define	RTSX_MS_OC_INT_EN	(1 << 23)
-#define	RTSX_SD_OC_INT_EN	(1 << 22)
+#define	RTSX_CMD_DONE_INT_EN	(1U << 31)
+#define	RTSX_DATA_DONE_INT_EN	(1U << 30)
+#define	RTSX_TRANS_OK_INT_EN	(1U << 29)
+#define	RTSX_TRANS_FAIL_INT_EN	(1U << 28)
+#define	RTSX_XD_INT_EN		(1U << 27)
+#define	RTSX_MS_INT_EN		(1U << 26)
+#define	RTSX_SD_INT_EN		(1U << 25)
+#define	RTSX_GPIO0_INT_EN	(1U << 24)
+#define	RTSX_MS_OC_INT_EN	(1U << 23)
+#define	RTSX_SD_OC_INT_EN	(1U << 22)
 
 /* Power on/off. */
 #define	RTSX_FPDCTL	0xFC00
diff --git a/sys/dev/ic/silireg.h b/sys/dev/ic/silireg.h
index 23f616298d5..e7f53d4bd1e 100644
--- a/sys/dev/ic/silireg.h
+++ b/sys/dev/ic/silireg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: silireg.h,v 1.21 2011/01/26 21:41:00 drahn Exp $ */
+/*	$OpenBSD: silireg.h,v 1.22 2013/11/26 20:33:16 deraadt Exp $ */
 
 /*
  * Copyright (c) 2007 David Gwynne <dlg@openbsd.org>
@@ -167,7 +167,7 @@
 #define SILI_PREG_HEC		0x1048 /* Handshake Error Counter */
 #define SILI_PREG_PHYCONF	0x1050 /* Port PHY Configuration */
 #define SILI_PREG_PSS		0x1800 /* Port Slot Status */
-#define SILI_PREG_PSS_ATTENTION		(1 << 31)
+#define SILI_PREG_PSS_ATTENTION		(1U << 31)
 #define SILI_PREG_PSS_ALL_SLOTS		0x7fffffff
 #define SILI_PREG_CAR_LO(_s)	(0x1c00 + ((_s) * 0x8)) /* Cmd Activate Reg */
 #define SILI_PREG_CAR_HI(_s)	(0x1c00 + ((_s) * 0x8) + 0x4)
diff --git a/sys/dev/ic/tcic2reg.h b/sys/dev/ic/tcic2reg.h
index de1aa918684..759211e79ea 100644
--- a/sys/dev/ic/tcic2reg.h
+++ b/sys/dev/ic/tcic2reg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tcic2reg.h,v 1.3 2008/06/26 05:42:16 ray Exp $	*/
+/*	$OpenBSD: tcic2reg.h,v 1.4 2013/11/26 20:33:16 deraadt Exp $	*/
 /*	$NetBSD: tcic2reg.h,v 1.1 1999/03/23 20:04:14 bad Exp $	*/
 
 /*-
@@ -124,12 +124,12 @@
 #define	TCIC_ADDR_MASK	(ADDR_SPACE_SIZE - 1)
 
 /* The following bits are defined in diagnostic mode */
-#define	TCIC_ADDR_DIAG_NREG	((u_int32_t) 1 << 31)	/* inverted! */
-#define	TCIC_ADDR_DIAG_NCEH	((u_int32_t) 1 << 30)
-#define	TCIC_ADDR_DIAG_NCEL	((u_int32_t) 1 << 29)
-#define	TCIC_ADDR_DIAG_NCWR	((u_int32_t) 1 << 28)
-#define	TCIC_ADDR_DIAG_NCRD	((u_int32_t) 1 << 27)
-#define	TCIC_ADDR_DIAG_CRESET	((u_int32_t) 1 << 26)
+#define	TCIC_ADDR_DIAG_NREG	((u_int32_t) 1U << 31)	/* inverted! */
+#define	TCIC_ADDR_DIAG_NCEH	((u_int32_t) 1U << 30)
+#define	TCIC_ADDR_DIAG_NCEL	((u_int32_t) 1U << 29)
+#define	TCIC_ADDR_DIAG_NCWR	((u_int32_t) 1U << 28)
+#define	TCIC_ADDR_DIAG_NCRD	((u_int32_t) 1U << 27)
+#define	TCIC_ADDR_DIAG_CRESET	((u_int32_t) 1U << 26)
 
 /* Bits in socket control register */
 #define	TCIC_SCTRL_ENA		(1 << 0)	/* enable access to card */
diff --git a/sys/dev/pci/bktr/bktr_core.c b/sys/dev/pci/bktr/bktr_core.c
index bbd3087ade2..58cee989a0a 100644
--- a/sys/dev/pci/bktr/bktr_core.c
+++ b/sys/dev/pci/bktr/bktr_core.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: bktr_core.c,v 1.31 2013/10/04 07:27:36 brad Exp $	*/
+/*	$OpenBSD: bktr_core.c,v 1.32 2013/11/26 20:33:18 deraadt Exp $	*/
 /* $FreeBSD: src/sys/dev/bktr/bktr_core.c,v 1.114 2000/10/31 13:09:56 roger Exp $ */
 
 /*
@@ -2362,10 +2362,10 @@ dump_bt848( bktr_ptr_t bktr )
 #define BKTR_CLEAR_RISC_STATUS_BIT2 (1 << 22)
 #define BKTR_CLEAR_RISC_STATUS_BIT3 (1 << 23)
 
-#define BKTR_TEST_RISC_STATUS_BIT0 (1 << 28)
-#define BKTR_TEST_RISC_STATUS_BIT1 (1 << 29)
-#define BKTR_TEST_RISC_STATUS_BIT2 (1 << 30)
-#define BKTR_TEST_RISC_STATUS_BIT3 (1 << 31)
+#define BKTR_TEST_RISC_STATUS_BIT0 (1U << 28)
+#define BKTR_TEST_RISC_STATUS_BIT1 (1U << 29)
+#define BKTR_TEST_RISC_STATUS_BIT2 (1U << 30)
+#define BKTR_TEST_RISC_STATUS_BIT3 (1U << 31)
 
 static bool_t
 notclipped (bktr_reg_t * bktr, int x, int width) {
diff --git a/sys/dev/pci/if_etreg.h b/sys/dev/pci/if_etreg.h
index 3d72e6879d7..5fb12b1ddbf 100644
--- a/sys/dev/pci/if_etreg.h
+++ b/sys/dev/pci/if_etreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_etreg.h,v 1.4 2008/07/21 04:12:21 kevlo Exp $	*/
+/*	$OpenBSD: if_etreg.h,v 1.5 2013/11/26 20:33:17 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2007 The DragonFly Project.  All rights reserved.
@@ -99,14 +99,14 @@
 #define ET_INTR_MASK			0x001c
 
 #define ET_SWRST			0x0028
-#define ET_SWRST_TXDMA			(1 << 0)
-#define ET_SWRST_RXDMA			(1 << 1)
-#define ET_SWRST_TXMAC			(1 << 2)
-#define ET_SWRST_RXMAC			(1 << 3)
-#define ET_SWRST_MAC			(1 << 4)
-#define ET_SWRST_MAC_STAT		(1 << 5)
-#define ET_SWRST_MMC			(1 << 6)
-#define ET_SWRST_SELFCLR_DISABLE	(1 << 31)
+#define ET_SWRST_TXDMA			(1U << 0)
+#define ET_SWRST_RXDMA			(1U << 1)
+#define ET_SWRST_TXMAC			(1U << 2)
+#define ET_SWRST_RXMAC			(1U << 3)
+#define ET_SWRST_MAC			(1U << 4)
+#define ET_SWRST_MAC_STAT		(1U << 5)
+#define ET_SWRST_MMC			(1U << 6)
+#define ET_SWRST_SELFCLR_DISABLE	(1U << 31)
 
 #define ET_MSI_CFG			0x0030
 
@@ -222,19 +222,19 @@
 #define ET_RXMAC_MGT_CHECK_PKT		(1 << 17)
 
 #define ET_MAC_CFG1			0x5000
-#define ET_MAC_CFG1_TXEN		(1 << 0)
-#define ET_MAC_CFG1_SYNC_TXEN		(1 << 1)
-#define ET_MAC_CFG1_RXEN		(1 << 2)
-#define ET_MAC_CFG1_SYNC_RXEN		(1 << 3)
-#define ET_MAC_CFG1_TXFLOW		(1 << 4)
-#define ET_MAC_CFG1_RXFLOW		(1 << 5)
-#define ET_MAC_CFG1_LOOPBACK		(1 << 8)
-#define ET_MAC_CFG1_RST_TXFUNC		(1 << 16)
-#define ET_MAC_CFG1_RST_RXFUNC		(1 << 17)
-#define ET_MAC_CFG1_RST_TXMC		(1 << 18)
-#define ET_MAC_CFG1_RST_RXMC		(1 << 19)
-#define ET_MAC_CFG1_SIM_RST		(1 << 30)
-#define ET_MAC_CFG1_SOFT_RST		(1 << 31)
+#define ET_MAC_CFG1_TXEN		(1U << 0)
+#define ET_MAC_CFG1_SYNC_TXEN		(1U << 1)
+#define ET_MAC_CFG1_RXEN		(1U << 2)
+#define ET_MAC_CFG1_SYNC_RXEN		(1U << 3)
+#define ET_MAC_CFG1_TXFLOW		(1U << 4)
+#define ET_MAC_CFG1_RXFLOW		(1U << 5)
+#define ET_MAC_CFG1_LOOPBACK		(1U << 8)
+#define ET_MAC_CFG1_RST_TXFUNC		(1U << 16)
+#define ET_MAC_CFG1_RST_RXFUNC		(1U << 17)
+#define ET_MAC_CFG1_RST_TXMC		(1U << 18)
+#define ET_MAC_CFG1_RST_RXMC		(1U << 19)
+#define ET_MAC_CFG1_SIM_RST		(1U << 30)
+#define ET_MAC_CFG1_SOFT_RST		(1U << 31)
 
 #define ET_MAC_CFG2			0x5004
 #define ET_MAC_CFG2_FDX			(1 << 0)
@@ -265,10 +265,10 @@
 #define ET_MAX_FRMLEN			0x5010
 
 #define ET_MII_CFG			0x5020
-#define ET_MII_CFG_CLKRST		(7 << 0)
-#define ET_MII_CFG_PREAMBLE_SUP		(1 << 4)
-#define ET_MII_CFG_SCAN_AUTOINC		(1 << 5)
-#define ET_MII_CFG_RST			(1 << 31)
+#define ET_MII_CFG_CLKRST		(7U << 0)
+#define ET_MII_CFG_PREAMBLE_SUP		(1U << 4)
+#define ET_MII_CFG_SCAN_AUTOINC		(1U << 5)
+#define ET_MII_CFG_RST			(1U << 31)
 
 #define ET_MII_CMD			0x5024
 #define ET_MII_CMD_READ			(1 << 0)
diff --git a/sys/dev/pci/if_iwnreg.h b/sys/dev/pci/if_iwnreg.h
index 12a345bcd1f..005efd8622c 100644
--- a/sys/dev/pci/if_iwnreg.h
+++ b/sys/dev/pci/if_iwnreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_iwnreg.h,v 1.44 2013/08/29 19:06:40 syl Exp $	*/
+/*	$OpenBSD: if_iwnreg.h,v 1.45 2013/11/26 20:33:17 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2007, 2008
@@ -179,11 +179,11 @@
 #define IWN_FW_DATA_BASE	0x00800000
 
 /* Possible flags for register IWN_RESET. */
-#define IWN_RESET_NEVO			(1 << 0)
-#define IWN_RESET_SW			(1 << 7)
-#define IWN_RESET_MASTER_DISABLED	(1 << 8)
-#define IWN_RESET_STOP_MASTER		(1 << 9)
-#define IWN_RESET_LINK_PWR_MGMT_DIS	(1 << 31)
+#define IWN_RESET_NEVO			(1U << 0)
+#define IWN_RESET_SW			(1U << 7)
+#define IWN_RESET_MASTER_DISABLED	(1U << 8)
+#define IWN_RESET_STOP_MASTER		(1U << 9)
+#define IWN_RESET_LINK_PWR_MGMT_DIS	(1U << 31)
 
 /* Possible flags for register IWN_GP_CNTRL. */
 #define IWN_GP_CNTRL_MAC_ACCESS_ENA	(1 << 0)
@@ -231,8 +231,8 @@
 #define IWN_LED_ON		0x00000078
 
 /* Possible flags for register IWN_DRAM_INT_TBL. */
-#define IWN_DRAM_INT_TBL_WRAP_CHECK	(1 << 27)
-#define IWN_DRAM_INT_TBL_ENABLE		(1 << 31)
+#define IWN_DRAM_INT_TBL_WRAP_CHECK	(1U << 27)
+#define IWN_DRAM_INT_TBL_ENABLE		(1U << 31)
 
 /* Possible values for register IWN_ANA_PLL. */
 #define IWN_ANA_PLL_INIT	0x00880300
@@ -241,21 +241,21 @@
 #define	IWN_FH_RX_STATUS_IDLE	(1 << 24)
 
 /* Possible flags for register IWN_BSM_WR_CTRL. */
-#define IWN_BSM_WR_CTRL_START_EN	(1 << 30)
-#define IWN_BSM_WR_CTRL_START		(1 << 31)
+#define IWN_BSM_WR_CTRL_START_EN	(1U << 30)
+#define IWN_BSM_WR_CTRL_START		(1U << 31)
 
 /* Possible flags for register IWN_INT. */
-#define IWN_INT_ALIVE		(1 <<  0)
-#define IWN_INT_WAKEUP		(1 <<  1)
-#define IWN_INT_SW_RX		(1 <<  3)
-#define IWN_INT_CT_REACHED	(1 <<  6)
-#define IWN_INT_RF_TOGGLED	(1 <<  7)
-#define IWN_INT_SW_ERR		(1 << 25)
-#define IWN_INT_SCHED		(1 << 26)
-#define IWN_INT_FH_TX		(1 << 27)
-#define IWN_INT_RX_PERIODIC	(1 << 28)
-#define IWN_INT_HW_ERR		(1 << 29)
-#define IWN_INT_FH_RX		(1 << 31)
+#define IWN_INT_ALIVE		(1U <<  0)
+#define IWN_INT_WAKEUP		(1U <<  1)
+#define IWN_INT_SW_RX		(1U <<  3)
+#define IWN_INT_CT_REACHED	(1U <<  6)
+#define IWN_INT_RF_TOGGLED	(1U <<  7)
+#define IWN_INT_SW_ERR		(1U << 25)
+#define IWN_INT_SCHED		(1U << 26)
+#define IWN_INT_FH_TX		(1U << 27)
+#define IWN_INT_RX_PERIODIC	(1U << 28)
+#define IWN_INT_HW_ERR		(1U << 29)
+#define IWN_INT_FH_RX		(1U << 31)
 
 /* Shortcut. */
 #define IWN_INT_MASK_DEF						\
@@ -275,8 +275,8 @@
 
 /* Possible flags/values for register IWN_FH_TX_CONFIG. */
 #define IWN_FH_TX_CONFIG_DMA_PAUSE		0
-#define IWN_FH_TX_CONFIG_DMA_ENA		(1 << 31)
-#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD	(1 << 20)
+#define IWN_FH_TX_CONFIG_DMA_ENA		(1U << 31)
+#define IWN_FH_TX_CONFIG_CIRQ_HOST_ENDTFD	(1U << 20)
 
 /* Possible flags/values for register IWN_FH_TXBUF_STATUS. */
 #define IWN_FH_TXBUF_STATUS_TBNUM(x)	((x) << 20)
@@ -290,17 +290,17 @@
 #define IWN_FH_TX_STATUS_IDLE(chnl)	(1 << ((chnl) + 16))
 
 /* Possible flags for register IWN_FH_RX_CONFIG. */
-#define IWN_FH_RX_CONFIG_ENA		(1 << 31)
+#define IWN_FH_RX_CONFIG_ENA		(1U << 31)
 #define IWN_FH_RX_CONFIG_NRBD(x)	((x) << 20)
-#define IWN_FH_RX_CONFIG_RB_SIZE_8K	(1 << 16)
-#define IWN_FH_RX_CONFIG_SINGLE_FRAME	(1 << 15)
-#define IWN_FH_RX_CONFIG_IRQ_DST_HOST	(1 << 12)
+#define IWN_FH_RX_CONFIG_RB_SIZE_8K	(1U << 16)
+#define IWN_FH_RX_CONFIG_SINGLE_FRAME	(1U << 15)
+#define IWN_FH_RX_CONFIG_IRQ_DST_HOST	(1U << 12)
 #define IWN_FH_RX_CONFIG_RB_TIMEOUT(x)	((x) << 4)
-#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY	(1 <<  2)
+#define IWN_FH_RX_CONFIG_IGN_RXF_EMPTY	(1U <<  2)
 
 /* Possible flags for register IWN_FH_TX_CONFIG. */
-#define IWN_FH_TX_CONFIG_DMA_ENA	(1 << 31)
-#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA	(1 <<  3)
+#define IWN_FH_TX_CONFIG_DMA_ENA	(1U << 31)
+#define IWN_FH_TX_CONFIG_DMA_CREDIT_ENA	(1U <<  3)
 
 /* Possible flags for register IWN_EEPROM. */
 #define IWN_EEPROM_READ_VALID	(1 << 0)
@@ -347,7 +347,7 @@
 #define IWN_APMG_PCI_STT_L1A_DIS	(1 << 11)
 
 /* Possible flags for register IWN_BSM_DRAM_TEXT_SIZE. */
-#define IWN_FW_UPDATED	(1 << 31)
+#define IWN_FW_UPDATED	(1U << 31)
 
 #define IWN_SCHED_WINSZ		64
 #define IWN_SCHED_LIMIT		64
diff --git a/sys/dev/pci/if_wpireg.h b/sys/dev/pci/if_wpireg.h
index 5f447eab55a..26fa72b88bf 100644
--- a/sys/dev/pci/if_wpireg.h
+++ b/sys/dev/pci/if_wpireg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_wpireg.h,v 1.27 2009/10/24 20:17:17 damien Exp $	*/
+/*	$OpenBSD: if_wpireg.h,v 1.28 2013/11/26 20:33:17 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2006-2008
@@ -137,12 +137,12 @@
 #define WPI_GIO_CHICKEN_L1A_NO_L0S_RX	(1 << 23)
 
 /* Possible flags for register WPI_FH_RX_CONFIG. */
-#define WPI_FH_RX_CONFIG_DMA_ENA		(1 << 31)
-#define WPI_FH_RX_CONFIG_RDRBD_ENA		(1 << 29)
-#define WPI_FH_RX_CONFIG_WRSTATUS_ENA		(1 << 27)
-#define WPI_FH_RX_CONFIG_MAXFRAG		(1 << 24)
+#define WPI_FH_RX_CONFIG_DMA_ENA		(1U << 31)
+#define WPI_FH_RX_CONFIG_RDRBD_ENA		(1U << 29)
+#define WPI_FH_RX_CONFIG_WRSTATUS_ENA		(1U << 27)
+#define WPI_FH_RX_CONFIG_MAXFRAG		(1U << 24)
 #define WPI_FH_RX_CONFIG_NRBD(x)		((x) << 20)
-#define WPI_FH_RX_CONFIG_IRQ_DST_HOST		(1 << 12)
+#define WPI_FH_RX_CONFIG_IRQ_DST_HOST		(1U << 12)
 #define WPI_FH_RX_CONFIG_IRQ_RBTH(x)		((x) << 4)
 
 /* Possible flags for register WPI_ANA_PLL. */
@@ -156,18 +156,18 @@
 #define	WPI_FH_RX_STATUS_IDLE	(1 << 24)
 
 /* Possible flags for register WPI_BSM_WR_CTRL. */
-#define WPI_BSM_WR_CTRL_START_EN	(1 << 30)
-#define WPI_BSM_WR_CTRL_START		(1 << 31)
+#define WPI_BSM_WR_CTRL_START_EN	(1U << 30)
+#define WPI_BSM_WR_CTRL_START		(1U << 31)
 
 /* Possible flags for register WPI_INT. */
-#define WPI_INT_ALIVE		(1 <<  0)
-#define WPI_INT_WAKEUP		(1 <<  1)
-#define WPI_INT_SW_RX		(1 <<  3)
-#define WPI_INT_RF_TOGGLED	(1 <<  7)
-#define WPI_INT_SW_ERR		(1 << 25)
-#define WPI_INT_FH_TX		(1 << 27)
-#define WPI_INT_HW_ERR		(1 << 29)
-#define WPI_INT_FH_RX		(1 << 31)
+#define WPI_INT_ALIVE		(1U <<  0)
+#define WPI_INT_WAKEUP		(1U <<  1)
+#define WPI_INT_SW_RX		(1U <<  3)
+#define WPI_INT_RF_TOGGLED	(1U <<  7)
+#define WPI_INT_SW_ERR		(1U << 25)
+#define WPI_INT_FH_TX		(1U << 27)
+#define WPI_INT_HW_ERR		(1U << 29)
+#define WPI_INT_FH_RX		(1U << 31)
 
 /* Shortcut. */
 #define WPI_INT_MASK							\
@@ -631,7 +631,7 @@ struct wpi_firmware_hdr {
 #define WPI_FW_DATA_MAXSZ	(32 * 1024)
 #define WPI_FW_BOOT_TEXT_MAXSZ	1024
 
-#define WPI_FW_UPDATED	(1 << 31)
+#define WPI_FW_UPDATED	(1U << 31)
 
 /*
  * Offsets into EEPROM.
diff --git a/sys/dev/pci/pciidereg.h b/sys/dev/pci/pciidereg.h
index 317201a3cce..59c3914cc7a 100644
--- a/sys/dev/pci/pciidereg.h
+++ b/sys/dev/pci/pciidereg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: pciidereg.h,v 1.9 2009/10/13 22:05:13 jsg Exp $	*/
+/*	$OpenBSD: pciidereg.h,v 1.10 2013/11/26 20:33:17 deraadt Exp $	*/
 /*	$NetBSD: pciidereg.h,v 1.6 2000/11/14 18:42:58 thorpej Exp $	*/
 
 /*
@@ -126,7 +126,7 @@ struct idedma_table {
 #define SCH_TIM_UDMA	0x70000
 #define SCH_TIM_MDMA	0x00300
 #define SCH_TIM_PIO	0x00007
-#define SCH_TIM_SYNCDMA	(1 << 31)
+#define SCH_TIM_SYNCDMA	(1U << 31)
 
 #define SCH_TIM_MASK	(SCH_TIM_UDMA | SCH_TIM_MDMA | SCH_TIM_PIO)
 
diff --git a/sys/dev/pci/tcpcib.c b/sys/dev/pci/tcpcib.c
index 0b6f93d56a3..5f1be2ec10c 100644
--- a/sys/dev/pci/tcpcib.c
+++ b/sys/dev/pci/tcpcib.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tcpcib.c,v 1.5 2013/05/30 16:15:02 deraadt Exp $	*/
+/*	$OpenBSD: tcpcib.c,v 1.6 2013/11/26 20:33:17 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2012 Matt Dainty <matt@bodgit-n-scarper.com>
@@ -220,7 +220,7 @@ tcpcib_attach(struct device *parent, struct device *self, void *aux)
 	reg = pci_conf_read(pa->pa_pc, pa->pa_tag, E600_LPC_WDTBA);
 	wdtbase = reg & 0xffff;
 	sc->sc_wdt_iot = pa->pa_iot;
-	if (reg & (1 << 31) && wdtbase) {
+	if (reg & (1U << 31) && wdtbase) {
 		if (PCI_MAPREG_IO_ADDR(wdtbase) == 0 ||
 		    bus_space_map(sc->sc_wdt_iot, PCI_MAPREG_IO_ADDR(wdtbase),
 		    E600_WDT_SIZE, 0, &sc->sc_wdt_ioh)) {
diff --git a/sys/dev/sbus/rfx.c b/sys/dev/sbus/rfx.c
index 9542c5bdff3..ac97284a9ea 100644
--- a/sys/dev/sbus/rfx.c
+++ b/sys/dev/sbus/rfx.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: rfx.c,v 1.10 2013/10/20 20:07:31 miod Exp $	*/
+/*	$OpenBSD: rfx.c,v 1.11 2013/11/26 20:33:18 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2004, Miodrag Vallat.
@@ -513,8 +513,8 @@ rfx_initialize(struct rfx_softc *sc, struct sbus_attach_args *sa,
 			value = letoh32(offset);
 		}
 
-		if (offset & (1 << 31)) {
-			offset = (offset & ~(1 << 31)) - RFX_RAMDAC_ADDR;
+		if (offset & (1U << 31)) {
+			offset = (offset & ~(1U << 31)) - RFX_RAMDAC_ADDR;
 			if (offset < RFX_RAMDAC_SIZE)
 				sc->sc_ramdac[offset] = value >> 24;
 		} else {
diff --git a/sys/dev/usb/if_axenreg.h b/sys/dev/usb/if_axenreg.h
index 137830cf43e..966a85253b6 100644
--- a/sys/dev/usb/if_axenreg.h
+++ b/sys/dev/usb/if_axenreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_axenreg.h,v 1.1 2013/10/07 05:37:41 yuo Exp $	*/
+/*	$OpenBSD: if_axenreg.h,v 1.2 2013/11/26 20:33:18 deraadt Exp $	*/
 
 /*
  * Copyright (c) 2013 Yojiro UO <yuo@openbsd.org>. All right reserved.
@@ -52,14 +52,14 @@
  *  0x0850: ipv6 tcp (ssh)		0000 1000 0101 0000
  */
 
-#define	AXEN_RXHDR_CRC_ERR	(1 << 31)
-#define	AXEN_RXHDR_DROP_ERR	(1 << 30)
-#define AXEN_RXHDR_MCAST	(1 << 15)
-#define AXEN_RXHDR_RX_OK	(1 << 11)
-#define	AXEN_RXHDR_L3_ERR	(1 << 9)
-#define	AXEN_RXHDR_L4_ERR	(1 << 8)
-#define AXEN_RXHDR_L3CSUM_ERR 	(1 << 1)
-#define AXEN_RXHDR_L4CSUM_ERR	(1 << 0)
+#define	AXEN_RXHDR_CRC_ERR	(1U << 31)
+#define	AXEN_RXHDR_DROP_ERR	(1U << 30)
+#define AXEN_RXHDR_MCAST	(1U << 15)
+#define AXEN_RXHDR_RX_OK	(1U << 11)
+#define	AXEN_RXHDR_L3_ERR	(1U << 9)
+#define	AXEN_RXHDR_L4_ERR	(1U << 8)
+#define AXEN_RXHDR_L3CSUM_ERR 	(1U << 1)
+#define AXEN_RXHDR_L4CSUM_ERR	(1U << 0)
 
 /* L4 packet type (3bit) */
 #define AXEN_RXHDR_L4_TYPE_MASK	0x0000001c
diff --git a/sys/dev/usb/if_otus.c b/sys/dev/usb/if_otus.c
index 3950d0af1cb..3cc784e99a2 100644
--- a/sys/dev/usb/if_otus.c
+++ b/sys/dev/usb/if_otus.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_otus.c,v 1.36 2013/11/05 10:20:04 mpi Exp $	*/
+/*	$OpenBSD: if_otus.c,v 1.37 2013/11/26 20:33:18 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -1597,7 +1597,7 @@ otus_set_multi(struct otus_softc *sc)
 		ETHER_NEXT_MULTI(step, enm);
 	}
  done:
-	hi |= 1 << 31;	/* Make sure the broadcast bit is set. */
+	hi |= 1U << 31;	/* Make sure the broadcast bit is set. */
 	otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_L, lo);
 	otus_write(sc, AR_MAC_REG_GROUP_HASH_TBL_H, hi);
 	return otus_write_barrier(sc);
diff --git a/sys/dev/usb/if_otusreg.h b/sys/dev/usb/if_otusreg.h
index a230991f7b0..ff507c5dd0c 100644
--- a/sys/dev/usb/if_otusreg.h
+++ b/sys/dev/usb/if_otusreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_otusreg.h,v 1.8 2013/04/15 09:23:01 mglocker Exp $	*/
+/*	$OpenBSD: if_otusreg.h,v 1.9 2013/11/26 20:33:18 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr>
@@ -151,7 +151,7 @@ struct ar_tx_head {
 #define AR_TX_PHY_TPC_SHIFT	9
 #define AR_TX_PHY_ANTMSK(msk)	((msk) << 15)
 #define AR_TX_PHY_MCS(mcs)	((mcs) << 18)
-#define AR_TX_PHY_SHGI		(1 << 31)
+#define AR_TX_PHY_SHGI		(1U << 31)
 } __packed;
 
 /* USB Rx stream mode header. */
diff --git a/sys/dev/usb/if_ralreg.h b/sys/dev/usb/if_ralreg.h
index 4dbe14f3491..34bff016ab6 100644
--- a/sys/dev/usb/if_ralreg.h
+++ b/sys/dev/usb/if_ralreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_ralreg.h,v 1.12 2006/11/13 20:06:38 damien Exp $  */
+/*	$OpenBSD: if_ralreg.h,v 1.13 2013/11/26 20:33:18 deraadt Exp $  */
 
 /*-
  * Copyright (c) 2005, 2006
@@ -192,7 +192,7 @@ struct ural_rx_desc {
 } __packed;
 
 #define RAL_RF_LOBUSY	(1 << 15)
-#define RAL_RF_BUSY	(1 << 31)
+#define RAL_RF_BUSY	(1U << 31)
 #define RAL_RF_20BIT	(20 << 24)
 
 #define RAL_RF1	0
diff --git a/sys/dev/usb/if_rumreg.h b/sys/dev/usb/if_rumreg.h
index fd817a5a508..763fab1d9c6 100644
--- a/sys/dev/usb/if_rumreg.h
+++ b/sys/dev/usb/if_rumreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_rumreg.h,v 1.14 2009/08/10 18:04:56 damien Exp $	*/
+/*	$OpenBSD: if_rumreg.h,v 1.15 2013/11/26 20:33:18 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2005, 2006 Damien Bergamini <damien.bergamini@free.fr>
@@ -140,7 +140,7 @@
 #define RT2573_BBP_BUSY	(1 << 16)
 /* possible flags for register PHY_CSR4 */
 #define RT2573_RF_20BIT	(20 << 24)
-#define RT2573_RF_BUSY	(1 << 31)
+#define RT2573_RF_BUSY	(1U << 31)
 
 /* LED values */
 #define RT2573_LED_RADIO	(1 << 8)
diff --git a/sys/dev/usb/if_urtwreg.h b/sys/dev/usb/if_urtwreg.h
index 53a301689fc..fe1ca1e845d 100644
--- a/sys/dev/usb/if_urtwreg.h
+++ b/sys/dev/usb/if_urtwreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_urtwreg.h,v 1.14 2013/04/15 09:23:01 mglocker Exp $	*/
+/*	$OpenBSD: if_urtwreg.h,v 1.15 2013/11/26 20:33:18 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2009 Martynas Venckus <martynas@openbsd.org>
@@ -77,9 +77,9 @@
 #define	URTW_TX_MXDMA_1024		(6 << URTW_TX_MXDMA_SHIFT)
 #define	URTW_TX_MXDMA_2048		(7 << URTW_TX_MXDMA_SHIFT)
 #define	URTW_TX_MXDMA_SHIFT		(21)
-#define	URTW_TX_CWMIN			(1 << 31)
-#define	URTW_TX_DISCW			(1 << 20)
-#define	URTW_TX_SWPLCPLEN		(1 << 24)
+#define	URTW_TX_CWMIN			(1U << 31)
+#define	URTW_TX_DISCW			(1U << 20)
+#define	URTW_TX_SWPLCPLEN		(1U << 24)
 #define	URTW_TX_NOICV			(0x80000)
 #define	URTW_RX				0x0044		/* 4 byte */
 #define	URTW_RX_9356SEL			(1 << 6)
@@ -113,7 +113,7 @@
 #define	URTW_MAX_RX_DMA_2048		(7 << URTW_MAX_RX_DMA_SHIFT)
 #define	URTW_MAX_RX_DMA_1024		(6)
 #define	URTW_MAX_RX_DMA_SHIFT		(10)
-#define	URTW_RCR_ONLYERLPKT		(1 << 31)
+#define	URTW_RCR_ONLYERLPKT		(1U << 31)
 #define	URTW_INT_TIMEOUT		0x0048		/* 4 byte */
 #define	URTW_EPROM_CMD			0x0050		/* 1 byte */
 #define	URTW_EPROM_CMD_NORMAL		(0x0)
diff --git a/sys/dev/usb/if_zyd.c b/sys/dev/usb/if_zyd.c
index 73c4360b1e6..23fe29f996f 100644
--- a/sys/dev/usb/if_zyd.c
+++ b/sys/dev/usb/if_zyd.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_zyd.c,v 1.93 2013/11/06 15:55:15 jeremy Exp $	*/
+/*	$OpenBSD: if_zyd.c,v 1.94 2013/11/26 20:33:19 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2006 by Damien Bergamini <damien.bergamini@free.fr>
@@ -1661,7 +1661,7 @@ zyd_set_multi(struct zyd_softc *sc)
 	}
 
 done:
-	hi |= 1 << 31;	/* make sure the broadcast bit is set */
+	hi |= 1U << 31;	/* make sure the broadcast bit is set */
 	zyd_write32(sc, ZYD_MAC_GHTBL, lo);
 	zyd_write32(sc, ZYD_MAC_GHTBH, hi);
 }
diff --git a/sys/dev/usb/if_zydreg.h b/sys/dev/usb/if_zydreg.h
index e2eff309211..8368151fdef 100644
--- a/sys/dev/usb/if_zydreg.h
+++ b/sys/dev/usb/if_zydreg.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: if_zydreg.h,v 1.26 2013/04/15 09:23:01 mglocker Exp $	*/
+/*	$OpenBSD: if_zydreg.h,v 1.27 2013/11/26 20:33:19 deraadt Exp $	*/
 
 /*-
  * Copyright (c) 2006 by Damien Bergamini <damien.bergamini@free.fr>
@@ -936,23 +936,23 @@
 #define ZYD_ENC_SNIFFER	8
 
 /* flags for register ZYD_MAC_RXFILTER */
-#define ZYD_FILTER_ASS_REQ	(1 << 0)
-#define ZYD_FILTER_ASS_RSP	(1 << 1)
-#define ZYD_FILTER_REASS_REQ	(1 << 2)
-#define ZYD_FILTER_REASS_RSP	(1 << 3)
-#define ZYD_FILTER_PRB_REQ	(1 << 4)
-#define ZYD_FILTER_PRB_RSP	(1 << 5)
-#define ZYD_FILTER_BCN		(1 << 8)
-#define ZYD_FILTER_ATIM		(1 << 9)
-#define ZYD_FILTER_DEASS	(1 << 10)
-#define ZYD_FILTER_AUTH		(1 << 11)
-#define ZYD_FILTER_DEAUTH	(1 << 12)
-#define ZYD_FILTER_PS_POLL	(1 << 26)
-#define ZYD_FILTER_RTS		(1 << 27)
-#define ZYD_FILTER_CTS		(1 << 28)
-#define ZYD_FILTER_ACK		(1 << 29)
-#define ZYD_FILTER_CFE		(1 << 30)
-#define ZYD_FILTER_CFE_A	(1 << 31)
+#define ZYD_FILTER_ASS_REQ	(1U << 0)
+#define ZYD_FILTER_ASS_RSP	(1U << 1)
+#define ZYD_FILTER_REASS_REQ	(1U << 2)
+#define ZYD_FILTER_REASS_RSP	(1U << 3)
+#define ZYD_FILTER_PRB_REQ	(1U << 4)
+#define ZYD_FILTER_PRB_RSP	(1U << 5)
+#define ZYD_FILTER_BCN		(1U << 8)
+#define ZYD_FILTER_ATIM		(1U << 9)
+#define ZYD_FILTER_DEASS	(1U << 10)
+#define ZYD_FILTER_AUTH		(1U << 11)
+#define ZYD_FILTER_DEAUTH	(1U << 12)
+#define ZYD_FILTER_PS_POLL	(1U << 26)
+#define ZYD_FILTER_RTS		(1U << 27)
+#define ZYD_FILTER_CTS		(1U << 28)
+#define ZYD_FILTER_ACK		(1U << 29)
+#define ZYD_FILTER_CFE		(1U << 30)
+#define ZYD_FILTER_CFE_A	(1U << 31)
 
 /* helpers for register ZYD_MAC_RXFILTER */
 #define ZYD_FILTER_MONITOR	0x000fffff
diff --git a/sys/kern/kern_workq.c b/sys/kern/kern_workq.c
index 24f6d2a3eb4..df3762b80d0 100644
--- a/sys/kern/kern_workq.c
+++ b/sys/kern/kern_workq.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: kern_workq.c,v 1.13 2013/11/18 20:21:51 deraadt Exp $ */
+/*	$OpenBSD: kern_workq.c,v 1.14 2013/11/26 20:33:19 deraadt Exp $ */
 
 /*
  * Copyright (c) 2007 David Gwynne <dlg@openbsd.org>
@@ -49,7 +49,7 @@ struct workq	workq_syswq = {
 };
 
 /* if we allocate the wqt, we need to know we free it too */ 
-#define WQT_F_POOL	(1 << 31)
+#define WQT_F_POOL	(1U << 31)
 
 void			workq_init(void); /* called in init_main.c */
 void			workq_create_thread(void *);
diff --git a/sys/scsi/scsi_disk.h b/sys/scsi/scsi_disk.h
index e55cf85360e..fec5647fae4 100644
--- a/sys/scsi/scsi_disk.h
+++ b/sys/scsi/scsi_disk.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: scsi_disk.h,v 1.33 2013/05/30 18:31:34 tedu Exp $	*/
+/*	$OpenBSD: scsi_disk.h,v 1.34 2013/11/26 20:33:20 deraadt Exp $	*/
 /*	$NetBSD: scsi_disk.h,v 1.10 1996/07/05 16:19:05 christos Exp $	*/
 
 /*
@@ -472,7 +472,7 @@ struct scsi_vpd_disk_limits {
 	u_int8_t		optimal_unmap_granularity[4];
 
 	u_int8_t		unmap_granularity_align[4];
-#define SI_PG_DISK_LIMITS_UGAVALID	(1 << 31)
+#define SI_PG_DISK_LIMITS_UGAVALID	(1U << 31)
 
 	u_int8_t		_reserved2[28];
 };