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author | 2015-05-13 02:39:28 +0000 | |
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committer | 2015-05-13 02:39:28 +0000 | |
commit | 62dc7ecad0d8bfe144547a1efa6ed6e2ead486ff (patch) | |
tree | 03cf2c9fa14cce0280ad0e5b8abfeef5436f960b | |
parent | To replace c0-*, add a high watermark to the pty event, and also backoff (diff) | |
download | wireguard-openbsd-62dc7ecad0d8bfe144547a1efa6ed6e2ead486ff.tar.xz wireguard-openbsd-62dc7ecad0d8bfe144547a1efa6ed6e2ead486ff.zip |
Having the same settings on the same phy across multiple boards is just
asking too much in the arm world.
Translate the fec parameters from the novena dtb to set a different clock
skew to the same micrel phy used on sabre lite. The novena dtb sets
txd[0-3]-skew-ps to 3000, the sabre lite sets them to 0. When run through
the shifting/oring process from the micrel phy driver in FreeBSD this ends
up being a write of 0xffff on the novena and 0x0000 on sabre lite when
writing to TX_DATA_PAD_SKEW.
This change resolves the stability problems djm was seeing with imxenet
on novena.
ok djm@
-rw-r--r-- | sys/arch/armv7/imx/imxenet.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/sys/arch/armv7/imx/imxenet.c b/sys/arch/armv7/imx/imxenet.c index c61eeccb927..4ee88daf842 100644 --- a/sys/arch/armv7/imx/imxenet.c +++ b/sys/arch/armv7/imx/imxenet.c @@ -1,4 +1,4 @@ -/* $OpenBSD: imxenet.c,v 1.13 2015/05/08 03:38:26 jsg Exp $ */ +/* $OpenBSD: imxenet.c,v 1.14 2015/05/13 02:39:28 jsg Exp $ */ /* * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se> * @@ -465,7 +465,6 @@ imxenet_chip_init(struct imxenet_softc *sc) break; case BOARD_ID_IMX6_PHYFLEX: case BOARD_ID_IMX6_SABRELITE: /* Micrel KSZ9021 */ - case BOARD_ID_IMX6_NOVENA: /* Micrel KSZ9021 */ /* prefer master mode */ imxenet_miibus_writereg(dev, phy, 0x9, 0x1f00); @@ -485,6 +484,19 @@ imxenet_chip_init(struct imxenet_softc *sc) /* enable all interrupts */ imxenet_miibus_writereg(dev, phy, 0x1b, 0xff00); break; + case BOARD_ID_IMX6_NOVENA: /* Micrel KSZ9021 */ + /* TXEN_SKEW_PS/TXC_SKEW_PS/RXDV_SKEW_PS/RXC_SKEW_PS */ + imxenet_miibus_writereg(dev, phy, 0x0b, 0x8104); + imxenet_miibus_writereg(dev, phy, 0x0c, 0xf0f0); + + /* RXD0_SKEW_PS/RXD1_SKEW_PS/RXD2_SKEW_PS/RXD3_SKEW_PS */ + imxenet_miibus_writereg(dev, phy, 0x0b, 0x8105); + imxenet_miibus_writereg(dev, phy, 0x0c, 0x0000); + + /* TXD0_SKEW_PS/TXD1_SKEW_PS/TXD2_SKEW_PS/TXD3_SKEW_PS */ + imxenet_miibus_writereg(dev, phy, 0x0b, 0x8106); + imxenet_miibus_writereg(dev, phy, 0x0c, 0xffff); + break; case BOARD_ID_IMX6_CUBOXI: /* AR8035 */ case BOARD_ID_IMX6_HUMMINGBOARD: /* AR8035 */ case BOARD_ID_IMX6_SABRESD: /* AR8031 */ |