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authoraaron <aaron@openbsd.org>2000-11-29 22:57:16 +0000
committeraaron <aaron@openbsd.org>2000-11-29 22:57:16 +0000
commit659c4932d882d6c7daef64f280542993a8fc8f03 (patch)
tree304245dd485aa8bc7835ee93b235eadc44a8c67a
parentCorrect PCI interrupt setup routine for Texas Instruments PCI113X CardBus (diff)
downloadwireguard-openbsd-659c4932d882d6c7daef64f280542993a8fc8f03.tar.xz
wireguard-openbsd-659c4932d882d6c7daef64f280542993a8fc8f03.zip
Bugfix: reset 16-bit pcmcia in chip initialisation sequence; from NetBSD.
-rw-r--r--sys/dev/pci/pccbb.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/sys/dev/pci/pccbb.c b/sys/dev/pci/pccbb.c
index 84904e7db3d..6474e480912 100644
--- a/sys/dev/pci/pccbb.c
+++ b/sys/dev/pci/pccbb.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pccbb.c,v 1.11 2000/11/29 21:31:27 aaron Exp $ */
+/* $OpenBSD: pccbb.c,v 1.12 2000/11/29 22:57:16 aaron Exp $ */
/* $NetBSD: pccbb.c,v 1.42 2000/06/16 23:41:35 cgd Exp $ */
/*
@@ -749,6 +749,7 @@ pccbb_chipinit(sc)
reg = pci_conf_read(pc, tag, PCI_BCR_INTR);
reg &= ~CB_BCR_INTR_IREQ_ENABLE; /* use PCI Intr */
reg |= CB_BCR_WRITE_POST_ENABLE; /* enable write post */
+ reg |= CB_BCR_RESET_ENABLE; /* assert reset */
pci_conf_write(pc, tag, PCI_BCR_INTR, reg);
switch (sc->sc_chipset) {
@@ -789,6 +790,15 @@ pccbb_chipinit(sc)
pci_conf_write(pc, tag, PCI_CB_IOLIMIT0, 0);
pci_conf_write(pc, tag, PCI_CB_IOBASE1, 0xffffffff);
pci_conf_write(pc, tag, PCI_CB_IOLIMIT1, 0);
+
+ /* reset 16-bit pcmcia bus */
+ bus_space_write_1(sc->sc_base_memt, sc->sc_base_memh,
+ 0x800 + PCIC_INTR,
+ bus_space_read_1(sc->sc_base_memt, sc->sc_base_memh,
+ 0x800 + PCIC_INTR) & ~PCIC_INTR_RESET);
+
+ /* turn off power */
+ pccbb_power((cardbus_chipset_tag_t)sc, CARDBUS_VCC_0V | CARDBUS_VPP_0V);
}