Add support for the i.MX8MM PCIe clocks. These behave exactly like

the i.MX8MQ variant and sit in the same places.

2 files changed, 69 insertions, 2 deletions

diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index 7fe69d26e82..61a501ca02e 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.18 2020/03/21 12:53:24 patrick Exp $ */
+/* $OpenBSD: imxccm.c,v 1.19 2020/04/23 14:56:28 patrick Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -1175,7 +1175,22 @@ imxccm_enable(void *cookie, uint32_t *cells, int on)
 	if (idx == 0)
 		return;
 
-	if (sc->sc_gates == imx8mq_gates) {
+	if (sc->sc_gates == imx8mm_gates) {
+		switch (idx) {
+		case IMX8MM_CLK_PCIE1_CTRL:
+		case IMX8MM_CLK_PCIE2_CTRL:
+			pcells[0] = sc->sc_phandle;
+			pcells[1] = IMX8MM_SYS_PLL2_250M;
+			imxccm_set_parent(cookie, &idx, pcells);
+			break;
+		case IMX8MM_CLK_PCIE1_PHY:
+		case IMX8MM_CLK_PCIE2_PHY:
+			pcells[0] = sc->sc_phandle;
+			pcells[1] = IMX8MM_SYS_PLL2_100M;
+			imxccm_set_parent(cookie, &idx, pcells);
+			break;
+		}
+	} else if (sc->sc_gates == imx8mq_gates) {
 		switch (idx) {
 		case IMX8MQ_CLK_32K:
 			/* always on */
@@ -1622,6 +1637,24 @@ imxccm_set_parent(void *cookie, uint32_t *cells, uint32_t *pcells)
 				mux |= (0x4 << sc->sc_muxs[idx].shift);
 			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
 			return 0;
+		case IMX8MM_CLK_PCIE1_CTRL:
+		case IMX8MM_CLK_PCIE2_CTRL:
+			if (pidx != IMX8MM_SYS_PLL2_250M)
+				break;
+			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+			mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);
+			mux |= (0x1 << sc->sc_muxs[idx].shift);
+			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
+			return 0;
+		case IMX8MM_CLK_PCIE1_PHY:
+		case IMX8MM_CLK_PCIE2_PHY:
+			if (pidx != IMX8MM_SYS_PLL2_100M)
+				break;
+			mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+			mux &= ~(sc->sc_muxs[idx].mask << sc->sc_muxs[idx].shift);
+			mux |= (0x1 << sc->sc_muxs[idx].shift);
+			HWRITE4(sc, sc->sc_muxs[idx].reg, mux);
+			return 0;
 		}
 	} else if (sc->sc_muxs == imx8mq_muxs) {
 		switch (idx) {
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index 1d98ebd930f..2b202883845 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -293,11 +293,16 @@ struct imxccm_mux imx7d_muxs[] = {
 
 #define IMX8MM_ARM_PLL			0x18
 #define IMX8MM_SYS_PLL1_800M		0x38
+#define IMX8MM_SYS_PLL2_100M		0x3a
+#define IMX8MM_SYS_PLL2_250M		0x3e
 #define IMX8MM_CLK_A53_SRC		0x42
 #define IMX8MM_ARM_PLL_OUT		0x2c
 #define IMX8MM_CLK_A53_CG		0x47
 #define IMX8MM_CLK_A53_DIV		0x4c
 #define IMX8MM_CLK_ENET_AXI		0x52
+#define IMX8MM_CLK_PCIE1_CTRL		0x67
+#define IMX8MM_CLK_PCIE1_PHY		0x68
+#define IMX8MM_CLK_PCIE1_AUX		0x69
 #define IMX8MM_CLK_ENET_REF		0x74
 #define IMX8MM_CLK_ENET_TIMER		0x75
 #define IMX8MM_CLK_ENET_PHY_REF		0x76
@@ -312,12 +317,16 @@ struct imxccm_mux imx7d_muxs[] = {
 #define IMX8MM_CLK_UART3		0x81
 #define IMX8MM_CLK_UART4		0x82
 #define IMX8MM_CLK_USDHC3		0x91
+#define IMX8MM_CLK_PCIE2_CTRL		0x98
+#define IMX8MM_CLK_PCIE2_PHY		0x99
+#define IMX8MM_CLK_PCIE2_AUX		0x9a
 #define IMX8MM_CLK_ENET1_ROOT		0xa2
 #define IMX8MM_CLK_I2C1_ROOT		0xa4
 #define IMX8MM_CLK_I2C2_ROOT		0xa5
 #define IMX8MM_CLK_I2C3_ROOT		0xa6
 #define IMX8MM_CLK_I2C4_ROOT		0xa7
 #define IMX8MM_CLK_OCOTP_ROOT		0xa8
+#define IMX8MM_CLK_PCIE1_ROOT		0xa9
 #define IMX8MM_CLK_UART1_ROOT		0xbc
 #define IMX8MM_CLK_UART2_ROOT		0xbd
 #define IMX8MM_CLK_UART3_ROOT		0xbe
@@ -331,6 +340,9 @@ struct imxccm_mux imx7d_muxs[] = {
 struct imxccm_gate imx8mm_gates[] = {
 	[IMX8MM_CLK_A53_CG] = { 0x8000, 14 },
 	[IMX8MM_CLK_ENET_AXI] = { 0x8880, 14 },
+	[IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 14 },
+	[IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 14 },
+	[IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 14 },
 	[IMX8MM_CLK_ENET_REF] = { 0xa980, 14 },
 	[IMX8MM_CLK_ENET_TIMER] = { 0xaa00, 14 },
 	[IMX8MM_CLK_ENET_PHY_REF] = { 0xaa80, 14 },
@@ -345,12 +357,16 @@ struct imxccm_gate imx8mm_gates[] = {
 	[IMX8MM_CLK_UART3] = { 0xb000, 14 },
 	[IMX8MM_CLK_UART4] = { 0xb080, 14 },
 	[IMX8MM_CLK_USDHC3] = { 0xbc80, 14 },
+	[IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 },
+	[IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 },
+	[IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 },
 	[IMX8MM_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MM_CLK_ENET_AXI },
 	[IMX8MM_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MM_CLK_I2C1 },
 	[IMX8MM_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MM_CLK_I2C2 },
 	[IMX8MM_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MM_CLK_I2C3 },
 	[IMX8MM_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MM_CLK_I2C4 },
 	[IMX8MM_CLK_OCOTP_ROOT] = { 0x4220, 0 },
+	[IMX8MM_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MM_CLK_PCIE1_CTRL },
 	[IMX8MM_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MM_CLK_UART1 },
 	[IMX8MM_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MM_CLK_UART2 },
 	[IMX8MM_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MM_CLK_UART3 },
@@ -364,6 +380,9 @@ struct imxccm_gate imx8mm_gates[] = {
 struct imxccm_divider imx8mm_divs[] = {
 	[IMX8MM_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MM_CLK_A53_CG },
 	[IMX8MM_CLK_ENET_AXI] = { 0x8880, 0, 0x3f },
+	[IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 0, 0x3f },
+	[IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 0, 0x3f },
+	[IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 0, 0x3f },
 	[IMX8MM_CLK_USDHC1] = { 0xac00, 0, 0x3f },
 	[IMX8MM_CLK_USDHC2] = { 0xac80, 0, 0x3f },
 	[IMX8MM_CLK_I2C1] = { 0xad00, 0, 0x3f },
@@ -375,10 +394,16 @@ struct imxccm_divider imx8mm_divs[] = {
 	[IMX8MM_CLK_UART3] = { 0xb000, 0, 0x3f },
 	[IMX8MM_CLK_UART4] = { 0xb080, 0, 0x3f },
 	[IMX8MM_CLK_USDHC3] = { 0xbc80, 0, 0x3f },
+	[IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 0, 0x3f },
+	[IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 0, 0x3f },
+	[IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 0, 0x3f },
 };
 
 struct imxccm_divider imx8mm_predivs[] = {
 	[IMX8MM_CLK_ENET_AXI] = { 0x8880, 16, 0x7 },
+	[IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 16, 0x7 },
+	[IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 16, 0x7 },
+	[IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 16, 0x7 },
 	[IMX8MM_CLK_USDHC1] = { 0xac00, 16, 0x7 },
 	[IMX8MM_CLK_USDHC2] = { 0xac80, 16, 0x7 },
 	[IMX8MM_CLK_I2C1] = { 0xad00, 16, 0x7 },
@@ -390,11 +415,17 @@ struct imxccm_divider imx8mm_predivs[] = {
 	[IMX8MM_CLK_UART3] = { 0xb000, 16, 0x7 },
 	[IMX8MM_CLK_UART4] = { 0xb080, 16, 0x7 },
 	[IMX8MM_CLK_USDHC3] = { 0xbc80, 16, 0x7 },
+	[IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 16, 0x7 },
+	[IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 16, 0x7 },
+	[IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 16, 0x7 },
 };
 
 struct imxccm_mux imx8mm_muxs[] = {
 	[IMX8MM_CLK_A53_SRC] = { 0x8000, 24, 0x7 },
 	[IMX8MM_CLK_ENET_AXI] = { 0x8880, 24, 0x7 },
+	[IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 24, 0x7 },
+	[IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 24, 0x7 },
+	[IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 24, 0x7 },
 	[IMX8MM_CLK_USDHC1] = { 0xac00, 24, 0x7 },
 	[IMX8MM_CLK_USDHC2] = { 0xac80, 24, 0x7 },
 	[IMX8MM_CLK_I2C1] = { 0xad00, 24, 0x7 },
@@ -406,6 +437,9 @@ struct imxccm_mux imx8mm_muxs[] = {
 	[IMX8MM_CLK_UART3] = { 0xb000, 24, 0x7 },
 	[IMX8MM_CLK_UART4] = { 0xb080, 24, 0x7 },
 	[IMX8MM_CLK_USDHC3] = { 0xbc80, 24, 0x7 },
+	[IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 },
+	[IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 },
+	[IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 },
 };
 
 /*