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author | 2010-01-09 23:43:17 +0000 | |
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committer | 2010-01-09 23:43:17 +0000 | |
commit | 701c846665753a40619f0e794a1aca20522509d4 (patch) | |
tree | 64329fc89d64a9b5d1dafea8c34f9a1fd4931d3e | |
parent | Move cache information from global variables to per-cpu_info fields; this (diff) | |
download | wireguard-openbsd-701c846665753a40619f0e794a1aca20522509d4.tar.xz wireguard-openbsd-701c846665753a40619f0e794a1aca20522509d4.zip |
Move more R5000 code behind proper #ifdef stanzas.
-rw-r--r-- | sys/arch/mips64/mips64/tlbhandler.S | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S index 5db098abca8..7119a62d1a7 100644 --- a/sys/arch/mips64/mips64/tlbhandler.S +++ b/sys/arch/mips64/mips64/tlbhandler.S @@ -1,4 +1,4 @@ -/* $OpenBSD: tlbhandler.S,v 1.25 2009/12/12 20:07:10 miod Exp $ */ +/* $OpenBSD: tlbhandler.S,v 1.26 2010/01/09 23:43:17 miod Exp $ */ /* * Copyright (c) 1995-2004 Opsycon AB (www.opsycon.se / www.opsycon.com) @@ -124,6 +124,7 @@ tlb_load: /*---------------------------------------------------------------- xtlb_miss * Low level XTLB exception handler. */ +#if defined(CPU_R5000) || defined(CPU_RM7000) .globl xtlb_miss_err_r5k .ent xtlb_miss_err_r5k, 0 xtlb_miss_err_r5k: @@ -135,6 +136,7 @@ xtlb_miss_err_r5k: j k_tlb_inv nop .end xtlb_miss_err_r5k +#endif /* CPU_R5000 || CPU_RM7000 */ .globl xtlb_miss .ent xtlb_miss, 0 |