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authorpatrick <patrick@openbsd.org>2019-04-01 08:43:04 +0000
committerpatrick <patrick@openbsd.org>2019-04-01 08:43:04 +0000
commit7628bda1bd6e1024054716dcde7b457626a23cde (patch)
tree7978fc46f09b03e67e438bd236bd4526729fcfde
parentIn the upstreamed and official device tree for i.MX8MQ the power domains are (diff)
downloadwireguard-openbsd-7628bda1bd6e1024054716dcde7b457626a23cde.tar.xz
wireguard-openbsd-7628bda1bd6e1024054716dcde7b457626a23cde.zip
In the upstreamed and official device tree for i.MX8MQ the USB phys
use only one address and size cells. Also set the assigned clocks and enable them. ok kettenis@
-rw-r--r--sys/dev/fdt/xhci_fdt.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/sys/dev/fdt/xhci_fdt.c b/sys/dev/fdt/xhci_fdt.c
index 2105e0cb3b2..705f6e6e372 100644
--- a/sys/dev/fdt/xhci_fdt.c
+++ b/sys/dev/fdt/xhci_fdt.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: xhci_fdt.c,v 1.12 2018/08/06 10:52:30 patrick Exp $ */
+/* $OpenBSD: xhci_fdt.c,v 1.13 2019/04/01 08:43:04 patrick Exp $ */
/*
* Copyright (c) 2017 Mark kettenis <kettenis@openbsd.org>
*
@@ -95,8 +95,10 @@ xhci_fdt_attach(struct device *parent, struct device *self, void *aux)
goto unmap;
}
- /* Set up power domain */
+ /* Set up power and clocks */
power_domain_enable(sc->sc_node);
+ clock_set_assigned(sc->sc_node);
+ clock_enable_all(sc->sc_node);
/*
* Synopsys Designware USB3 controller needs some extra
@@ -381,7 +383,7 @@ exynos5_usbdrd_init(struct xhci_fdt_softc *sc, uint32_t *cells)
void
imx8mq_usb_init(struct xhci_fdt_softc *sc, uint32_t *cells)
{
- uint32_t phy_reg[4], reg;
+ uint32_t phy_reg[2], reg;
int node;
node = OF_getnodebyphandle(cells[0]);
@@ -391,8 +393,8 @@ imx8mq_usb_init(struct xhci_fdt_softc *sc, uint32_t *cells)
sizeof(phy_reg)) != sizeof(phy_reg))
return;
- if (bus_space_map(sc->sc.iot, phy_reg[1],
- phy_reg[3], 0, &sc->ph_ioh)) {
+ if (bus_space_map(sc->sc.iot, phy_reg[0],
+ phy_reg[1], 0, &sc->ph_ioh)) {
printf("%s: can't map PHY registers\n",
sc->sc.sc_bus.bdev.dv_xname);
return;