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author | 2020-10-12 17:36:06 +0000 | |
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committer | 2020-10-12 17:36:06 +0000 | |
commit | 783aabe87f92d0974b9d3015addcf36e62076090 (patch) | |
tree | 7f89594cbe28402e0b36d2f7dcce6db0fcfe18e0 | |
parent | Disable retguard for clang build. (diff) | |
download | wireguard-openbsd-783aabe87f92d0974b9d3015addcf36e62076090.tar.xz wireguard-openbsd-783aabe87f92d0974b9d3015addcf36e62076090.zip |
OCOTP's parent clock is the IPG clock on i.MX8M.
-rw-r--r-- | sys/dev/fdt/imxccm_clocks.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h index 1bed8bc7251..b149b8e68f5 100644 --- a/sys/dev/fdt/imxccm_clocks.h +++ b/sys/dev/fdt/imxccm_clocks.h @@ -379,7 +379,7 @@ struct imxccm_gate imx8mm_gates[] = { [IMX8MM_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MM_CLK_I2C2 }, [IMX8MM_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MM_CLK_I2C3 }, [IMX8MM_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MM_CLK_I2C4 }, - [IMX8MM_CLK_OCOTP_ROOT] = { 0x4220, 0 }, + [IMX8MM_CLK_OCOTP_ROOT] = { 0x4220, 0, IMX8MM_CLK_IPG_ROOT }, [IMX8MM_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MM_CLK_PCIE1_CTRL }, [IMX8MM_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MM_CLK_UART1 }, [IMX8MM_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MM_CLK_UART2 }, @@ -610,7 +610,7 @@ struct imxccm_gate imx8mq_gates[] = { [IMX8MQ_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MQ_CLK_USDHC1 }, [IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2 }, [IMX8MQ_CLK_TMU_ROOT] = { 0x4620, 0 }, - [IMX8MQ_CLK_OCOTP_ROOT] = { 0x4220, 0 }, + [IMX8MQ_CLK_OCOTP_ROOT] = { 0x4220, 0, IMX8MQ_CLK_IPG_ROOT }, }; struct imxccm_divider imx8mq_divs[] = { |