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author | 1996-01-10 16:26:16 +0000 | |
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committer | 1996-01-10 16:26:16 +0000 | |
commit | 78d65776c7586651d654d138d05c8b435bfcccbe (patch) | |
tree | 8336aafccb009fe122b394dc83883f3cf3c53475 | |
parent | original rfork(2) manpage from plan9. This will be modified to describe (diff) | |
download | wireguard-openbsd-78d65776c7586651d654d138d05c8b435bfcccbe.tar.xz wireguard-openbsd-78d65776c7586651d654d138d05c8b435bfcccbe.zip |
Imported from FreeBSD:
Add support for the SMC8416 (EtherEZ) ISA ethernet card.
The 8416 has an 8K shared mem (the old driver assumed 16K
and failed at attach time).
-rw-r--r-- | sys/dev/isa/if_ed.c | 31 | ||||
-rw-r--r-- | sys/dev/isa/if_edreg.h | 20 |
2 files changed, 44 insertions, 7 deletions
diff --git a/sys/dev/isa/if_ed.c b/sys/dev/isa/if_ed.c index 8b3db662650..a3617cd6685 100644 --- a/sys/dev/isa/if_ed.c +++ b/sys/dev/isa/if_ed.c @@ -310,14 +310,31 @@ ed_probe_WD80x3(sc, cf, ia) isa16bit = 1; break; case ED_TYPE_SMC8216C: - sc->type_str = "SMC8216/SMC8216C"; - memsize = 16384; - isa16bit = 1; - sc->is790 = 1; - break; case ED_TYPE_SMC8216T: - sc->type_str = "SMC8216T"; - memsize = 16384; + sc->type_str = (sc->type == ED_TYPE_SMC8216C) ? + "SMC8216/SMC8216C" : "SMC8216T"; + outb(sc->asic_addr + ED_WD790_HWR, + inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); + switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { + case ED_WD790_RAR_SZ64: + memsize = 65536; + break; + case ED_WD790_RAR_SZ32: + memsize = 32768; + break; + case ED_WD790_RAR_SZ16: + memsize = 16384; + break; + case ED_WD790_RAR_SZ8: + /* 8216 has 16K shared mem -- 8416 has 8K */ + sc->type_str = (sc->type == ED_TYPE_SMC8216C) ? + "SMC8416C/SMC8416BT" : "SMC8416T"; + memsize = 8192; + break; + } + outb(sc->asic_addr + ED_WD790_HWR, + inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); + isa16bit = 1; sc->is790 = 1; break; diff --git a/sys/dev/isa/if_edreg.h b/sys/dev/isa/if_edreg.h index a27a3940e46..9a2bd122b58 100644 --- a/sys/dev/isa/if_edreg.h +++ b/sys/dev/isa/if_edreg.h @@ -153,6 +153,26 @@ #define ED_WD790_ICR_EIL 0x01 /* enable interrupts */ /* + * REV/IOPA Revision / I/O Pipe register for the 83C79X + */ +#define ED_WD790_REV 7 + +#define ED_WD790 0x20 +#define ED_WD795 0x40 + +/* + * 79X RAM Address Register (RAR) + * Enabled with SWH bit=1 in HWR register + */ + +#define ED_WD790_RAR 0x0b + +#define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */ +#define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */ +#define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */ +#define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */ + +/* * General Control Register (GCR) * Eanbled with SWH bit == 1 in HWR register */ |