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| author |   miod <miod@openbsd.org> | 2012-06-24 20:25:58 +0000 |
|---|---|---|
| committer | miod <miod@openbsd.org> | 2012-06-24 20:25:58 +0000 |
| commit | 7ea10db56bb957d39bafd417aa80f6fdea43333d (patch) | |
| tree | 58a0624358fe911ee5fbbcb9a179b23f9dcef240 | |
| parent | Since the RM7000 cache behaves as a physically-indexed cache due to the set (diff) | |
| download | wireguard-openbsd-7ea10db56bb957d39bafd417aa80f6fdea43333d.tar.xz wireguard-openbsd-7ea10db56bb957d39bafd417aa80f6fdea43333d.zip | |
Bring in line with current cache_r{5,10}k.c style, and optimize slightly the
handling of a partial last line in IOSyncDCache. No functional change.
| -rw-r--r-- | sys/arch/mips64/mips64/cache_r4k.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/sys/arch/mips64/mips64/cache_r4k.c b/sys/arch/mips64/mips64/cache_r4k.c index d32439d72d5..d9955e7bc96 100644 --- a/sys/arch/mips64/mips64/cache_r4k.c +++ b/sys/arch/mips64/mips64/cache_r4k.c @@ -1,4 +1,4 @@ -/* $OpenBSD: cache_r4k.c,v 1.6 2012/06/24 16:26:04 miod Exp $ */ +/* $OpenBSD: cache_r4k.c,v 1.7 2012/06/24 20:25:58 miod Exp $ */ /* * Copyright (c) 2012 Miodrag Vallat. @@ -37,7 +37,7 @@ #define cache(op,addr) \ __asm__ __volatile__ ("cache %0, 0(%1)" :: "i"(op), "r"(addr) : "memory") #define sync() \ - __asm__ __volatile__ ("sync" ::: "memory"); + __asm__ __volatile__ ("sync" ::: "memory") static __inline__ void mips4k_hitinv_primary(vaddr_t, vsize_t, vsize_t); static __inline__ void mips4k_hitinv_secondary(vaddr_t, vsize_t, vsize_t); @@ -74,9 +74,10 @@ Mips4k_ConfigCache(struct cpu_info *ci) if ((cfg & (1 << 17)) == 0) { /* SC */ /* - * We expect the setup code to have set up ci->ci_l2size for - * us. Unfortunately we aren't allowed to panic() there, - * because the console is not available. + * We expect the setup code to have set up ci->ci_l2size and + * ci->ci_l2line for us. Unfortunately we aren't allowed to + * panic() there if it didn't, because the console is not + * available. */ /* fixed 32KB aliasing to avoid VCE */ @@ -382,10 +383,11 @@ Mips4k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how) sz -= line; } if (sz != 0 && partial_end) { - cache(HitWBInvalidate_D, va + sz - line); sz -= line; + cache(HitWBInvalidate_D, va + sz); } - mips4k_hitinv_primary(va, sz, line); + if (sz != 0) + mips4k_hitinv_primary(va, sz, line); break; case CACHE_SYNC_X: case CACHE_SYNC_W: @@ -418,10 +420,11 @@ Mips4k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how) sz -= line; } if (sz != 0 && partial_end) { - cache(HitWBInvalidate_S, va + sz - line); sz -= line; + cache(HitWBInvalidate_S, va + sz); } - mips4k_hitinv_secondary(va, sz, line); + if (sz != 0) + mips4k_hitinv_secondary(va, sz, line); break; case CACHE_SYNC_X: case CACHE_SYNC_W: |