diff options
| author |   miod <miod@openbsd.org> | 2010-05-09 18:36:07 +0000 |
|---|---|---|
| committer | miod <miod@openbsd.org> | 2010-05-09 18:36:07 +0000 |
| commit | a7e49e9dbc83346ea261fb46c83b068fbdbc2db5 (patch) | |
| tree | 666964037e424cc6f4aa9a518af7a81f169b8261 | |
| parent | if the sample rate the hardware will use is different than the (diff) | |
| download | wireguard-openbsd-a7e49e9dbc83346ea261fb46c83b068fbdbc2db5.tar.xz wireguard-openbsd-a7e49e9dbc83346ea261fb46c83b068fbdbc2db5.zip | |
Program a larger PCI retry hold interval if there is a Lucent USB controller
on the bus, to workaround timeout problems, according to IRIX knowledge which
made its way to Linux.
| -rw-r--r-- | sys/arch/sgi/xbow/xbridge.c | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/sys/arch/sgi/xbow/xbridge.c b/sys/arch/sgi/xbow/xbridge.c index d380c55925f..4f879563e0b 100644 --- a/sys/arch/sgi/xbow/xbridge.c +++ b/sys/arch/sgi/xbow/xbridge.c @@ -1,4 +1,4 @@ -/* $OpenBSD: xbridge.c,v 1.71 2010/04/21 03:03:26 deraadt Exp $ */ +/* $OpenBSD: xbridge.c,v 1.72 2010/05/09 18:36:07 miod Exp $ */ /* * Copyright (c) 2008, 2009 Miodrag Vallat. @@ -2251,6 +2251,25 @@ xbridge_setup(struct xbpci_softc *xb) } /* + * AT&T/Lucent USS-302 and USS-312 USB controllers require + * a larger PCI retry hold interval for proper operation. + */ + + for (dev = 0; dev < xb->xb_nslots; dev++) { + if (xb->xb_devices[dev].id == + PCI_ID_CODE(PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_USBHC) || + xb->xb_devices[dev].id == + PCI_ID_CODE(PCI_VENDOR_LUCENT, PCI_PRODUCT_LUCENT_USBHC2)) { + ctrl = xbridge_read_reg(xb, BRIDGE_BUS_TIMEOUT); + ctrl &= ~BRIDGE_BUS_PCI_RETRY_HOLD_MASK; + ctrl |= (4 << BRIDGE_BUS_PCI_RETRY_HOLD_SHIFT); + xbridge_write_reg(xb, BRIDGE_BUS_TIMEOUT, ctrl); + + break; + } + } + + /* * Setup interrupt handling. * * Note that, on PIC, the `lower address' register is a 64 bit |