Add code to print CPU features.

ok naddy@

2 files changed, 186 insertions, 10 deletions

diff --git a/sys/arch/arm64/arm64/cpu.c b/sys/arch/arm64/arm64/cpu.c
index e7059b81813..092bf6d882b 100644
--- a/sys/arch/arm64/arm64/cpu.c
+++ b/sys/arch/arm64/arm64/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.40 2020/10/16 17:28:59 kettenis Exp $	*/
+/*	$OpenBSD: cpu.c,v 1.41 2020/10/18 12:03:50 kettenis Exp $	*/
 
 /*
  * Copyright (c) 2016 Dale Rahn <drahn@dalerahn.com>
@@ -156,7 +156,7 @@ void
 cpu_identify(struct cpu_info *ci)
 {
 	uint64_t midr, impl, part;
-	uint64_t clidr, id_aa64pfr0;
+	uint64_t clidr, id;
 	uint32_t ctr, ccsidr, sets, ways, line;
 	const char *impl_name = NULL;
 	const char *part_name = NULL;
@@ -289,9 +289,140 @@ cpu_identify(struct cpu_info *ci)
 	 * The architecture has been updated to explicitly tell us if
 	 * we're not vulnerable.
 	 */
-	id_aa64pfr0 = READ_SPECIALREG(id_aa64pfr0_el1);
-	if (ID_AA64PFR0_CSV2(id_aa64pfr0) >= ID_AA64PFR0_CSV2_IMPL)
+
+	id = READ_SPECIALREG(id_aa64pfr0_el1);
+	if (ID_AA64PFR0_CSV2(id) >= ID_AA64PFR0_CSV2_IMPL)
 		ci->ci_flush_bp = cpu_flush_bp_noop;
+
+	/*
+	 * Print CPU features encoded in the ID registers.
+	 */
+
+	printf("\n%s: ", ci->ci_dev->dv_xname);
+
+	/*
+	 * ID_AA64ISAR0
+	 */
+	id = READ_SPECIALREG(id_aa64isar0_el1);
+	sep = "";
+
+	if (ID_AA64ISAR0_DP(id) >= ID_AA64ISAR0_DP_IMPL) {
+		printf("%sDP", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_SM4(id) >= ID_AA64ISAR0_SM4_IMPL) {
+		printf("%sSM4", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_SM3(id) >= ID_AA64ISAR0_SM3_IMPL) {
+		printf("%sSM3", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_SHA3(id) >= ID_AA64ISAR0_SHA3_IMPL) {
+		printf("%sSHA3", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_RDM(id) >= ID_AA64ISAR0_RDM_IMPL) {
+		printf("%sRDM", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_ATOMIC(id) >= ID_AA64ISAR0_ATOMIC_IMPL) {
+		printf("%sAtomic", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_CRC32(id) >= ID_AA64ISAR0_CRC32_BASE) {
+		printf("%sCRC32", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_SHA2(id) >= ID_AA64ISAR0_SHA2_BASE) {
+		printf("%sSHA2", sep);
+		sep = ",";
+	}
+	if (ID_AA64ISAR0_SHA2(id) >= ID_AA64ISAR0_SHA2_512)
+		printf("+SHA512");
+
+	if (ID_AA64ISAR0_SHA1(id) >= ID_AA64ISAR0_SHA1_BASE) {
+		printf("%sSHA1", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64ISAR0_AES(id) >= ID_AA64ISAR0_AES_BASE) {
+		printf("%sAES", sep);
+		sep = ",";
+	}
+	if (ID_AA64ISAR0_AES(id) >= ID_AA64ISAR0_AES_PMULL)
+		printf("+PMULL");
+
+	/*
+	 * ID_AA64ISAR1
+	 */
+	id = READ_SPECIALREG(id_aa64isar1_el1);
+
+	if (ID_AA64ISAR1_DPB(id) >= ID_AA64ISAR1_DPB_IMPL) {
+		printf("%sDPB", sep);
+		sep = ",";
+	}
+
+	/*
+	 * ID_AA64MMFR1
+	 *
+	 * We omit printing virtualization related fields like XNX, VH
+	 * and VMIDBits as they are not reakky relevant for us.
+	 */
+	id = READ_SPECIALREG(id_aa64mmfr1_el1);
+
+	if (ID_AA64MMFR1_SPECSEI(id) >= ID_AA64MMFR1_SPECSEI_IMPL) {
+		printf("%sSpecSEI", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64MMFR1_PAN(id) >= ID_AA64MMFR1_PAN_IMPL) {
+		printf("%sPAN", sep);
+		sep = ",";
+	}
+	if (ID_AA64MMFR1_PAN(id) >= ID_AA64MMFR1_PAN_ATS1E1)
+		printf("+ATS1E1");
+
+	if (ID_AA64MMFR1_LO(id) >= ID_AA64MMFR1_LO_IMPL) {
+		printf("%sLO", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64MMFR1_HPDS(id) >= ID_AA64MMFR1_HPDS_IMPL) {
+		printf("%sHPDS", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64MMFR1_HAFDBS(id) >= ID_AA64MMFR1_HAFDBS_AF) {
+		printf("%sHAF", sep);
+		sep = ",";
+	}
+	if (ID_AA64MMFR1_HAFDBS(id) >= ID_AA64MMFR1_HAFDBS_AF_DBS)
+		printf("DBS");
+
+	/*
+	 * ID_AA64PFR0
+	 */
+	id = READ_SPECIALREG(id_aa64pfr0_el1);
+
+	if (ID_AA64PFR0_CSV3(id) >= ID_AA64PFR0_CSV3_IMPL) {
+		printf("%sCSV3", sep);
+		sep = ",";
+	}
+
+	if (ID_AA64PFR0_CSV2(id) >= ID_AA64PFR0_CSV2_IMPL) {
+		printf("%sCSV2", sep);
+		sep = ",";
+	}
+	if (ID_AA64PFR0_CSV2(id) >= ID_AA64PFR0_CSV2_SCXT)
+		printf("+SCTX");
 }
 
 int	cpu_hatch_secondary(struct cpu_info *ci, int, uint64_t);
diff --git a/sys/arch/arm64/include/armreg.h b/sys/arch/arm64/include/armreg.h
index 05a5a37f9d1..d94ea7af4b8 100644
--- a/sys/arch/arm64/include/armreg.h
+++ b/sys/arch/arm64/include/armreg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: armreg.h,v 1.12 2020/08/17 08:12:18 kettenis Exp $ */
+/* $OpenBSD: armreg.h,v 1.13 2020/10/18 12:03:51 kettenis Exp $ */
 /*-
  * Copyright (c) 2013, 2014 Andrew Turner
  * Copyright (c) 2015 The FreeBSD Foundation
@@ -209,7 +209,7 @@
 #define	ICC_SRE_EL2_EN		(1U << 3)
 
 /* ID_AA64DFR0_EL1 */
-#define	ID_AA64DFR0_MASK		0xf0f0ffff
+#define	ID_AA64DFR0_MASK		0x00000000f0f0ffffUL
 #define	ID_AA64DFR0_DEBUG_VER_SHIFT	0
 #define	ID_AA64DFR0_DEBUG_VER_MASK	(0xf << ID_AA64DFR0_DEBUG_VER_SHIFT)
 #define	ID_AA64DFR0_DEBUG_VER(x)	((x) & ID_AA64DFR0_DEBUG_VER_MASK)
@@ -241,7 +241,7 @@
     ((((x) >> ID_AA64DFR0_CTX_CMPS_SHIFT) & 0xf) + 1)
 
 /* ID_AA64ISAR0_EL1 */
-#define	ID_AA64ISAR0_MASK		0xf0fffff0
+#define	ID_AA64ISAR0_MASK		0x0000fffff0fffff0ULL
 #define	ID_AA64ISAR0_AES_SHIFT		4
 #define	ID_AA64ISAR0_AES_MASK		(0xf << ID_AA64ISAR0_AES_SHIFT)
 #define	ID_AA64ISAR0_AES(x)		((x) & ID_AA64ISAR0_AES_MASK)
@@ -258,6 +258,7 @@
 #define	ID_AA64ISAR0_SHA2(x)		((x) & ID_AA64ISAR0_SHA2_MASK)
 #define	 ID_AA64ISAR0_SHA2_NONE		(0x0 << ID_AA64ISAR0_SHA2_SHIFT)
 #define	 ID_AA64ISAR0_SHA2_BASE		(0x1 << ID_AA64ISAR0_SHA2_SHIFT)
+#define	 ID_AA64ISAR0_SHA2_512		(0x2 << ID_AA64ISAR0_SHA2_SHIFT)
 #define	ID_AA64ISAR0_CRC32_SHIFT	16
 #define	ID_AA64ISAR0_CRC32_MASK		(0xf << ID_AA64ISAR0_CRC32_SHIFT)
 #define	ID_AA64ISAR0_CRC32(x)		((x) & ID_AA64ISAR0_CRC32_MASK)
@@ -273,9 +274,37 @@
 #define	ID_AA64ISAR0_RDM(x)		((x) & ID_AA64ISAR0_RDM_MASK)
 #define	 ID_AA64ISAR0_RDM_NONE		(0x0 << ID_AA64ISAR0_RDM_SHIFT)
 #define	 ID_AA64ISAR0_RDM_IMPL		(0x1 << ID_AA64ISAR0_RDM_SHIFT)
+#define	ID_AA64ISAR0_SHA3_SHIFT		32
+#define	ID_AA64ISAR0_SHA3_MASK		(0xfULL << ID_AA64ISAR0_SHA3_SHIFT)
+#define	ID_AA64ISAR0_SHA3(x)		((x) & ID_AA64ISAR0_SHA3_MASK)
+#define	 ID_AA64ISAR0_SHA3_NONE		(0x0ULL << ID_AA64ISAR0_SHA3_SHIFT)
+#define	 ID_AA64ISAR0_SHA3_IMPL		(0x1ULL << ID_AA64ISAR0_SHA3_SHIFT)
+#define	ID_AA64ISAR0_SM3_SHIFT		36
+#define	ID_AA64ISAR0_SM3_MASK		(0xfULL << ID_AA64ISAR0_SM3_SHIFT)
+#define	ID_AA64ISAR0_SM3(x)		((x) & ID_AA64ISAR0_SM3_MASK)
+#define	 ID_AA64ISAR0_SM3_NONE		(0x0ULL << ID_AA64ISAR0_SM3_SHIFT)
+#define	 ID_AA64ISAR0_SM3_IMPL		(0x1ULL << ID_AA64ISAR0_SM3_SHIFT)
+#define	ID_AA64ISAR0_SM4_SHIFT		40
+#define	ID_AA64ISAR0_SM4_MASK		(0xfULL << ID_AA64ISAR0_SM4_SHIFT)
+#define	ID_AA64ISAR0_SM4(x)		((x) & ID_AA64ISAR0_SM4_MASK)
+#define	 ID_AA64ISAR0_SM4_NONE		(0x0ULL << ID_AA64ISAR0_SM4_SHIFT)
+#define	 ID_AA64ISAR0_SM4_IMPL		(0x1ULL << ID_AA64ISAR0_SM4_SHIFT)
+#define	ID_AA64ISAR0_DP_SHIFT		44
+#define	ID_AA64ISAR0_DP_MASK		(0xfULL << ID_AA64ISAR0_DP_SHIFT)
+#define	ID_AA64ISAR0_DP(x)		((x) & ID_AA64ISAR0_DP_MASK)
+#define	 ID_AA64ISAR0_DP_NONE		(0x0ULL << ID_AA64ISAR0_DP_SHIFT)
+#define	 ID_AA64ISAR0_DP_IMPL		(0x1ULL << ID_AA64ISAR0_DP_SHIFT)
+
+/* ID_AA64ISAR1_EL1 */
+#define	ID_AA64ISAR1_MASK		0x000000000000000fULL
+#define	ID_AA64ISAR1_DPB_SHIFT		0
+#define	ID_AA64ISAR1_DPB_MASK		(0xf << ID_AA64ISAR1_DPB_SHIFT)
+#define	ID_AA64ISAR1_DPB(x)		((x) & ID_AA64ISAR1_DPB_MASK)
+#define	 ID_AA64ISAR1_DPB_NONE		(0x0 << ID_AA64ISAR1_DPB_SHIFT)
+#define	 ID_AA64ISAR1_DPB_IMPL		(0x1 << ID_AA64ISAR1_DPB_SHIFT)
 
 /* ID_AA64MMFR0_EL1 */
-#define	ID_AA64MMFR0_MASK		0xffffffff
+#define	ID_AA64MMFR0_MASK		0x00000000ffffffffULL
 #define	ID_AA64MMFR0_PA_RANGE_SHIFT	0
 #define	ID_AA64MMFR0_PA_RANGE_MASK	(0xf << ID_AA64MMFR0_PA_RANGE_SHIFT)
 #define	ID_AA64MMFR0_PA_RANGE(x)	((x) & ID_AA64MMFR0_PA_RANGE_MASK)
@@ -322,7 +351,7 @@
 #define	 ID_AA64MMFR0_TGRAN4_NONE	(0xf << ID_AA64MMFR0_TGRAN4_SHIFT)
 
 /* ID_AA64MMFR1_EL1 */
-#define	ID_AA64MMFR1_MASK		0x00ffffff
+#define	ID_AA64MMFR1_MASK		0x00000000ffffffffULL
 #define	ID_AA64MMFR1_HAFDBS_SHIFT	0
 #define	ID_AA64MMFR1_HAFDBS_MASK	(0xf << ID_AA64MMFR1_HAFDBS_SHIFT)
 #define	ID_AA64MMFR1_HAFDBS(x)		((x) & ID_AA64MMFR1_HAFDBS_MASK)
@@ -354,9 +383,20 @@
 #define	ID_AA64MMFR1_PAN(x)		((x) & ID_AA64MMFR1_PAN_MASK)
 #define	 ID_AA64MMFR1_PAN_NONE		(0x0 << ID_AA64MMFR1_PAN_SHIFT)
 #define	 ID_AA64MMFR1_PAN_IMPL		(0x1 << ID_AA64MMFR1_PAN_SHIFT)
+#define	 ID_AA64MMFR1_PAN_ATS1E1	(0x2 << ID_AA64MMFR1_PAN_SHIFT)
+#define	ID_AA64MMFR1_SPECSEI_SHIFT	24
+#define	ID_AA64MMFR1_SPECSEI_MASK	(0xf << ID_AA64MMFR1_SPECSEI_SHIFT)
+#define	ID_AA64MMFR1_SPECSEI(x)		((x) & ID_AA64MMFR1_SPECSEI_MASK)
+#define	 ID_AA64MMFR1_SPECSEI_NONE	(0x0 << ID_AA64MMFR1_SPECSEI_SHIFT)
+#define	 ID_AA64MMFR1_SPECSEI_IMPL	(0x1 << ID_AA64MMFR1_SPECSEI_SHIFT)
+#define	ID_AA64MMFR1_XNX_SHIFT		28
+#define	ID_AA64MMFR1_XNX_MASK		(0xf << ID_AA64MMFR1_XNX_SHIFT)
+#define	ID_AA64MMFR1_XNX(x)		((x) & ID_AA64MMFR1_XNX_MASK)
+#define	 ID_AA64MMFR1_XNX_NONE		(0x0 << ID_AA64MMFR1_XNX_SHIFT)
+#define	 ID_AA64MMFR1_XNX_IMPL		(0x1 << ID_AA64MMFR1_XNX_SHIFT)
 
 /* ID_AA64PFR0_EL1 */
-#define	ID_AA64PFR0_MASK		0x0fffffff
+#define	ID_AA64PFR0_MASK		0xff0000000fffffffULL
 #define	ID_AA64PFR0_EL0_SHIFT		0
 #define	ID_AA64PFR0_EL0_MASK		(0xf << ID_AA64PFR0_EL0_SHIFT)
 #define	ID_AA64PFR0_EL0(x)		((x) & ID_AA64PFR0_EL0_MASK)
@@ -401,6 +441,11 @@
 #define	 ID_AA64PFR0_CSV2_UNKNOWN	(0x0ULL << ID_AA64PFR0_CSV2_SHIFT)
 #define	 ID_AA64PFR0_CSV2_IMPL		(0x1ULL << ID_AA64PFR0_CSV2_SHIFT)
 #define	 ID_AA64PFR0_CSV2_SCXT		(0x2ULL << ID_AA64PFR0_CSV2_SHIFT)
+#define	ID_AA64PFR0_CSV3_SHIFT		60
+#define	ID_AA64PFR0_CSV3_MASK		(0xfULL << ID_AA64PFR0_CSV3_SHIFT)
+#define	ID_AA64PFR0_CSV3(x)		((x) & ID_AA64PFR0_CSV3_MASK)
+#define	 ID_AA64PFR0_CSV3_UNKNOWN	(0x0ULL << ID_AA64PFR0_CSV3_SHIFT)
+#define	 ID_AA64PFR0_CSV3_IMPL		(0x1ULL << ID_AA64PFR0_CSV3_SHIFT)
 
 /* MAIR_EL1 - Memory Attribute Indirection Register */
 #define	MAIR_ATTR_MASK(idx)	(0xff << ((n)* 8))