Add clock support for i.MX7D.

ok patrick@

2 files changed, 287 insertions, 15 deletions

diff --git a/sys/dev/fdt/imxccm.c b/sys/dev/fdt/imxccm.c
index 5ffe426656b..de062871f4e 100644
--- a/sys/dev/fdt/imxccm.c
+++ b/sys/dev/fdt/imxccm.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: imxccm.c,v 1.4 2018/06/03 18:17:27 kettenis Exp $ */
+/* $OpenBSD: imxccm.c,v 1.5 2018/06/11 09:20:46 kettenis Exp $ */
 /*
  * Copyright (c) 2012-2013 Patrick Wildt <patrick@blueri.se>
  *
@@ -183,6 +183,7 @@ imxccm_match(struct device *parent, void *match, void *aux)
 	    OF_is_compatible(faa->fa_node, "fsl,imx6sl-ccm") ||
 	    OF_is_compatible(faa->fa_node, "fsl,imx6sx-ccm") ||
 	    OF_is_compatible(faa->fa_node, "fsl,imx6ul-ccm") ||
+	    OF_is_compatible(faa->fa_node, "fsl,imx7d-ccm") ||
 	    OF_is_compatible(faa->fa_node, "fsl,imx8mq-ccm"));
 }
 
@@ -209,6 +210,13 @@ imxccm_attach(struct device *parent, struct device *self, void *aux)
 		sc->sc_ndivs = nitems(imx8mq_divs);
 		sc->sc_muxs = imx8mq_muxs;
 		sc->sc_nmuxs = nitems(imx8mq_muxs);
+	} else if (OF_is_compatible(sc->sc_node, "fsl,imx7d-ccm")) {
+		sc->sc_gates = imx7d_gates;
+		sc->sc_ngates = nitems(imx7d_gates);
+		sc->sc_divs = imx7d_divs;
+		sc->sc_ndivs = nitems(imx7d_divs);
+		sc->sc_muxs = imx7d_muxs;
+		sc->sc_nmuxs = nitems(imx7d_muxs);
 	} else if (OF_is_compatible(sc->sc_node, "fsl,imx6ul-ccm")) {
 		sc->sc_gates = imx6ul_gates;
 		sc->sc_ngates = nitems(imx6ul_gates);
@@ -369,6 +377,73 @@ imxccm_get_ipg_perclk(struct imxccm_softc *sc)
 }
 
 uint32_t
+imxccm_imx7d_i2c(struct imxccm_softc *sc, uint32_t idx)
+{
+	uint32_t mux;
+
+	if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+		return 0;
+
+	mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+	mux >>= sc->sc_muxs[idx].shift;
+	mux &= sc->sc_muxs[idx].mask;
+
+	switch (mux) {
+	case 0:
+		return clock_get_frequency(sc->sc_node, "osc");
+	case 1:
+		return 120000000; /* pll_sys_main_120m_clk */
+	default:
+		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+		return 0;
+	}
+}
+
+uint32_t
+imxccm_imx7d_uart(struct imxccm_softc *sc, uint32_t idx)
+{
+	uint32_t mux;
+
+	if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+		return 0;
+
+	mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+	mux >>= sc->sc_muxs[idx].shift;
+	mux &= sc->sc_muxs[idx].mask;
+
+	switch (mux) {
+	case 0:
+		return clock_get_frequency(sc->sc_node, "osc");
+	default:
+		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+		return 0;
+	}
+}
+
+uint32_t
+imxccm_imx7d_usdhc(struct imxccm_softc *sc, uint32_t idx)
+{
+	uint32_t mux;
+
+	if (idx >= sc->sc_nmuxs || sc->sc_muxs[idx].reg == 0)
+		return 0;
+
+	mux = HREAD4(sc, sc->sc_muxs[idx].reg);
+	mux >>= sc->sc_muxs[idx].shift;
+	mux &= sc->sc_muxs[idx].mask;
+
+	switch (mux) {
+	case 0:
+		return clock_get_frequency(sc->sc_node, "osc");
+	case 1:
+		return 392000000; /* pll_sys_pfd0_392m_clk */
+	default:
+		printf("%s: 0x%08x 0x%08x\n", __func__, idx, mux);
+		return 0;
+	}
+}
+
+uint32_t
 imxccm_imx8mq_enet(struct imxccm_softc *sc, uint32_t idx)
 {
 	uint32_t mux;
@@ -598,6 +673,26 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 		case IMX8MQ_CLK_USB_PHY_REF_SRC:
 			return imxccm_imx8mq_usb(sc, idx);
 		}
+	} else if (sc->sc_gates == imx7d_gates) {
+		switch (idx) {
+		case IMX7D_I2C1_ROOT_SRC:
+		case IMX7D_I2C2_ROOT_SRC:
+		case IMX7D_I2C3_ROOT_SRC:
+		case IMX7D_I2C4_ROOT_SRC:
+			return imxccm_imx7d_i2c(sc, idx);
+		case IMX7D_UART1_ROOT_SRC:
+		case IMX7D_UART2_ROOT_SRC:
+		case IMX7D_UART3_ROOT_SRC:
+		case IMX7D_UART4_ROOT_SRC:
+		case IMX7D_UART5_ROOT_SRC:
+		case IMX7D_UART6_ROOT_SRC:
+		case IMX7D_UART7_ROOT_SRC:
+			return imxccm_imx7d_uart(sc, idx);
+		case IMX7D_USDHC1_ROOT_SRC:
+		case IMX7D_USDHC2_ROOT_SRC:
+		case IMX7D_USDHC3_ROOT_SRC:
+			return imxccm_imx7d_usdhc(sc, idx);
+		}
 	} else if (sc->sc_gates == imx6ul_gates) {
 		switch (idx) {
 		case IMX6UL_CLK_ARM:
@@ -612,7 +707,7 @@ imxccm_get_frequency(void *cookie, uint32_t *cells)
 		case IMX6UL_CLK_USDHC2:
 			return imxccm_get_usdhx(sc, idx - IMX6UL_CLK_USDHC1 + 1);
 		}
-	} else {
+	} else if (sc->sc_gates == imx6_gates) {
 		switch (idx) {
 		case IMX6_CLK_AHB:
 			return imxccm_get_ahbclk(sc);
@@ -641,7 +736,7 @@ imxccm_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)
 {
 	struct imxccm_softc *sc = cookie;
 	uint32_t idx = cells[0];
-	uint32_t div, parent;
+	uint32_t reg, div, parent, parent_freq;
 
 	if (sc->sc_divs == imx8mq_divs) {
 		switch (idx) {
@@ -656,10 +751,31 @@ imxccm_set_frequency(void *cookie, uint32_t *cells, uint32_t freq)
 			if (imxccm_get_frequency(sc, &parent) != freq)
 				break;
 			imxccm_enable(cookie, &parent, 1);
-			div = HREAD4(sc, sc->sc_divs[idx].reg);
-			div &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);
-			div |= (0x0 << sc->sc_divs[idx].shift);
-			HWRITE4(sc, sc->sc_divs[idx].reg, div);
+			reg = HREAD4(sc, sc->sc_divs[idx].reg);
+			reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);
+			reg |= (0x0 << sc->sc_divs[idx].shift);
+			HWRITE4(sc, sc->sc_divs[idx].reg, reg);
+			return 0;
+		}
+	} else if (sc->sc_divs == imx7d_divs) {
+		switch (idx) {
+		case IMX7D_USDHC1_ROOT_CLK:
+		case IMX7D_USDHC2_ROOT_CLK:
+		case IMX7D_USDHC3_ROOT_CLK:
+			parent = sc->sc_gates[idx].parent;
+			return imxccm_set_frequency(sc, &parent, freq);
+		case IMX7D_USDHC1_ROOT_DIV:
+		case IMX7D_USDHC2_ROOT_DIV:
+		case IMX7D_USDHC3_ROOT_DIV:
+			parent = sc->sc_divs[idx].parent;
+			parent_freq = imxccm_get_frequency(sc, &parent);
+			div = 0;
+			while (parent_freq / (div + 1) > freq)
+				div++;
+			reg = HREAD4(sc, sc->sc_divs[idx].reg);
+			reg &= ~(sc->sc_divs[idx].mask << sc->sc_divs[idx].shift);
+			reg |= (div << sc->sc_divs[idx].shift);
+			HWRITE4(sc, sc->sc_divs[idx].reg, reg);
 			return 0;
 		}
 	}
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h
index c6fdd524ccf..5cb0db871c8 100644
--- a/sys/dev/fdt/imxccm_clocks.h
+++ b/sys/dev/fdt/imxccm_clocks.h
@@ -60,8 +60,7 @@ struct imxccm_gate imx6_gates[] = {
 #define IMX6UL_CLK_USDHC1	0xce
 #define IMX6UL_CLK_USDHC2	0xcf
 
-struct imxccm_gate imx6ul_gates[] =
-{
+struct imxccm_gate imx6ul_gates[] = {
 	[IMX6UL_CLK_GPT1_BUS] = { CCM_CCGR1, 10, IMX6UL_CLK_PERCLK },
 	[IMX6UL_CLK_GPT1_SERIAL] = { CCM_CCGR1, 11, IMX6UL_CLK_PERCLK },
 	[IMX6UL_CLK_I2C1] = { CCM_CCGR2, 3, IMX6UL_CLK_PERCLK },
@@ -76,6 +75,166 @@ struct imxccm_gate imx6ul_gates[] =
 };
 
 /*
+ * i.MX7D clocks.
+ */
+
+#define IMX7D_USDHC1_ROOT_CLK		0xbe
+#define IMX7D_USDHC1_ROOT_SRC		0xbf
+#define IMX7D_USDHC1_ROOT_CG		0xc0
+#define IMX7D_USDHC1_ROOT_DIV		0xc1
+#define IMX7D_USDHC2_ROOT_CLK		0xc2
+#define IMX7D_USDHC2_ROOT_SRC		0xc3
+#define IMX7D_USDHC2_ROOT_CG		0xc4
+#define IMX7D_USDHC2_ROOT_DIV		0xc5
+#define IMX7D_USDHC3_ROOT_CLK		0xc6
+#define IMX7D_USDHC3_ROOT_SRC		0xc7
+#define IMX7D_USDHC3_ROOT_CG		0xc8
+#define IMX7D_USDHC3_ROOT_DIV		0xc9
+#define IMX7D_I2C1_ROOT_CLK		0xd2
+#define IMX7D_I2C1_ROOT_SRC		0xd3
+#define IMX7D_I2C1_ROOT_CG		0xd4
+#define IMX7D_I2C1_ROOT_DIV		0xd5
+#define IMX7D_I2C2_ROOT_CLK		0xd6
+#define IMX7D_I2C2_ROOT_SRC		0xd7
+#define IMX7D_I2C2_ROOT_CG		0xd8
+#define IMX7D_I2C2_ROOT_DIV		0xd9
+#define IMX7D_I2C3_ROOT_CLK		0xda
+#define IMX7D_I2C3_ROOT_SRC		0xdb
+#define IMX7D_I2C3_ROOT_CG		0xdc
+#define IMX7D_I2C3_ROOT_DIV		0xdd
+#define IMX7D_I2C4_ROOT_CLK		0xde
+#define IMX7D_I2C4_ROOT_SRC		0xdf
+#define IMX7D_I2C4_ROOT_CG		0xe0
+#define IMX7D_I2C4_ROOT_DIV		0xe1
+#define IMX7D_UART1_ROOT_CLK		0xe2
+#define IMX7D_UART1_ROOT_SRC		0xe3
+#define IMX7D_UART1_ROOT_CG		0xe4
+#define IMX7D_UART1_ROOT_DIV		0xe5
+#define IMX7D_UART2_ROOT_CLK		0xe6
+#define IMX7D_UART2_ROOT_SRC		0xe7
+#define IMX7D_UART2_ROOT_CG		0xe8
+#define IMX7D_UART2_ROOT_DIV		0xe9
+#define IMX7D_UART3_ROOT_CLK		0xea
+#define IMX7D_UART3_ROOT_SRC		0xeb
+#define IMX7D_UART3_ROOT_CG		0xec
+#define IMX7D_UART3_ROOT_DIV		0xed
+#define IMX7D_UART4_ROOT_CLK		0xee
+#define IMX7D_UART4_ROOT_SRC		0xef
+#define IMX7D_UART4_ROOT_CG		0xf0
+#define IMX7D_UART4_ROOT_DIV		0xf1
+#define IMX7D_UART5_ROOT_CLK		0xf2
+#define IMX7D_UART5_ROOT_SRC		0xf3
+#define IMX7D_UART5_ROOT_CG		0xf4
+#define IMX7D_UART5_ROOT_DIV		0xf5
+#define IMX7D_UART6_ROOT_CLK		0xf6
+#define IMX7D_UART6_ROOT_SRC		0xf7
+#define IMX7D_UART6_ROOT_CG		0xf8
+#define IMX7D_UART6_ROOT_DIV		0xf9
+#define IMX7D_UART7_ROOT_CLK		0xfa
+#define IMX7D_UART7_ROOT_SRC		0xfb
+#define IMX7D_UART7_ROOT_CG		0xfc
+#define IMX7D_UART7_ROOT_DIV		0xfd
+#define IMX7D_USDHC1_ROOT_PRE_DIV	0x171
+#define IMX7D_USDHC2_ROOT_PRE_DIV	0x172
+#define IMX7D_USDHC3_ROOT_PRE_DIV	0x173
+#define IMX7D_I2C1_ROOT_PRE_DIV		0x176
+#define IMX7D_I2C2_ROOT_PRE_DIV		0x177
+#define IMX7D_I2C3_ROOT_PRE_DIV		0x178
+#define IMX7D_I2C4_ROOT_PRE_DIV		0x179
+#define IMX7D_UART1_ROOT_PRE_DIV	0x17a
+#define IMX7D_UART2_ROOT_PRE_DIV	0x17b
+#define IMX7D_UART3_ROOT_PRE_DIV	0x17c
+#define IMX7D_UART4_ROOT_PRE_DIV	0x17d
+#define IMX7D_UART5_ROOT_PRE_DIV	0x17e
+#define IMX7D_UART6_ROOT_PRE_DIV	0x17f
+#define IMX7D_UART7_ROOT_PRE_DIV	0x180
+#define IMX7D_USB_CTRL_CLK		0x1a6
+#define IMX7D_USB_PHY1_CLK		0x1a7
+#define IMX7D_USB_PHY2_CLK		0x1a8
+
+struct imxccm_gate imx7d_gates[] = {
+	[IMX7D_USDHC1_ROOT_CG] = { 0xab00, 28, IMX7D_USDHC1_ROOT_SRC },
+	[IMX7D_USDHC2_ROOT_CG] = { 0xab80, 28, IMX7D_USDHC2_ROOT_SRC },
+	[IMX7D_USDHC3_ROOT_CG] = { 0xabc0, 28, IMX7D_USDHC3_ROOT_SRC },
+	[IMX7D_I2C1_ROOT_CG] = { 0xad80, 28, IMX7D_I2C1_ROOT_SRC },
+	[IMX7D_I2C2_ROOT_CG] = { 0xae00, 28, IMX7D_I2C2_ROOT_SRC },
+	[IMX7D_I2C3_ROOT_CG] = { 0xae80, 28, IMX7D_I2C3_ROOT_SRC },
+	[IMX7D_I2C4_ROOT_CG] = { 0xaf00, 28, IMX7D_I2C4_ROOT_SRC },
+	[IMX7D_UART1_ROOT_CG] = { 0xaf80, 28, IMX7D_UART1_ROOT_SRC },
+	[IMX7D_UART2_ROOT_CG] = { 0xb000, 28, IMX7D_UART2_ROOT_SRC },
+	[IMX7D_UART3_ROOT_CG] = { 0xb080, 28, IMX7D_UART3_ROOT_SRC },
+	[IMX7D_UART4_ROOT_CG] = { 0xb100, 28, IMX7D_UART4_ROOT_SRC },
+	[IMX7D_UART5_ROOT_CG] = { 0xb180, 28, IMX7D_UART5_ROOT_SRC },
+	[IMX7D_UART6_ROOT_CG] = { 0xb200, 28, IMX7D_UART6_ROOT_SRC },
+	[IMX7D_UART7_ROOT_CG] = { 0xb280, 28, IMX7D_UART7_ROOT_SRC },
+	[IMX7D_USB_CTRL_CLK] = { 0x4680, 0 },
+	[IMX7D_USB_PHY1_CLK] = { 0x46a0, 0 },
+	[IMX7D_USB_PHY2_CLK] = { 0x46b0, 0 },
+	[IMX7D_USDHC1_ROOT_CLK] = { 0x46c0, 0, IMX7D_USDHC1_ROOT_DIV },
+	[IMX7D_USDHC2_ROOT_CLK] = { 0x46d0, 0, IMX7D_USDHC2_ROOT_DIV },
+	[IMX7D_USDHC3_ROOT_CLK] = { 0x46e0, 0, IMX7D_USDHC3_ROOT_DIV },
+	[IMX7D_I2C1_ROOT_CLK] = { 0x4880, 0, IMX7D_I2C1_ROOT_DIV },
+	[IMX7D_I2C2_ROOT_CLK] = { 0x4890, 0, IMX7D_I2C2_ROOT_DIV },
+	[IMX7D_I2C3_ROOT_CLK] = { 0x48a0, 0, IMX7D_I2C3_ROOT_DIV },
+	[IMX7D_I2C4_ROOT_CLK] = { 0x48b0, 0, IMX7D_I2C4_ROOT_DIV },
+	[IMX7D_UART1_ROOT_CLK] = { 0x4940, 0, IMX7D_UART1_ROOT_DIV },
+	[IMX7D_UART2_ROOT_CLK] = { 0x4950, 0, IMX7D_UART2_ROOT_DIV },
+	[IMX7D_UART3_ROOT_CLK] = { 0x4960, 0, IMX7D_UART3_ROOT_DIV },
+	[IMX7D_UART4_ROOT_CLK] = { 0x4970, 0, IMX7D_UART4_ROOT_DIV },
+	[IMX7D_UART5_ROOT_CLK] = { 0x4980, 0, IMX7D_UART5_ROOT_DIV },
+	[IMX7D_UART6_ROOT_CLK] = { 0x4990, 0, IMX7D_UART6_ROOT_DIV },
+	[IMX7D_UART7_ROOT_CLK] = { 0x49a0, 0, IMX7D_UART7_ROOT_DIV },
+};
+
+struct imxccm_divider imx7d_divs[] = {
+	[IMX7D_USDHC1_ROOT_PRE_DIV] = { 0xab00, 16, 0x7, IMX7D_USDHC1_ROOT_CG },
+	[IMX7D_USDHC2_ROOT_PRE_DIV] = { 0xab80, 16, 0x7, IMX7D_USDHC2_ROOT_CG },
+	[IMX7D_USDHC3_ROOT_PRE_DIV] = { 0xac00, 16, 0x7, IMX7D_USDHC3_ROOT_CG },
+	[IMX7D_I2C1_ROOT_PRE_DIV] = { 0xad80, 16, 0x7, IMX7D_I2C1_ROOT_CG },
+	[IMX7D_I2C2_ROOT_PRE_DIV] = { 0xae00, 16, 0x7, IMX7D_I2C2_ROOT_CG },
+	[IMX7D_I2C3_ROOT_PRE_DIV] = { 0xae80, 16, 0x7, IMX7D_I2C3_ROOT_CG },
+	[IMX7D_I2C4_ROOT_PRE_DIV] = { 0xaf00, 16, 0x7, IMX7D_I2C4_ROOT_CG },
+	[IMX7D_UART1_ROOT_PRE_DIV] = { 0xaf80, 16, 0x7, IMX7D_UART1_ROOT_CG },
+	[IMX7D_UART2_ROOT_PRE_DIV] = { 0xb000, 16, 0x7, IMX7D_UART2_ROOT_CG },
+	[IMX7D_UART3_ROOT_PRE_DIV] = { 0xb080, 16, 0x7, IMX7D_UART3_ROOT_CG },
+	[IMX7D_UART4_ROOT_PRE_DIV] = { 0xb100, 16, 0x7, IMX7D_UART4_ROOT_CG },
+	[IMX7D_UART5_ROOT_PRE_DIV] = { 0xb180, 16, 0x7, IMX7D_UART5_ROOT_CG },
+	[IMX7D_UART6_ROOT_PRE_DIV] = { 0xb200, 16, 0x7, IMX7D_UART6_ROOT_CG },
+	[IMX7D_UART7_ROOT_PRE_DIV] = { 0xb280, 16, 0x7, IMX7D_UART7_ROOT_CG },
+	[IMX7D_USDHC1_ROOT_DIV] = { 0xab00, 0, 0x3f, IMX7D_USDHC1_ROOT_PRE_DIV },
+	[IMX7D_USDHC2_ROOT_DIV] = { 0xab80, 0, 0x3f, IMX7D_USDHC2_ROOT_PRE_DIV },
+	[IMX7D_USDHC3_ROOT_DIV] = { 0xac00, 0, 0x3f, IMX7D_USDHC3_ROOT_PRE_DIV },
+	[IMX7D_I2C1_ROOT_DIV] = { 0xad80, 0, 0x3f, IMX7D_I2C1_ROOT_PRE_DIV },
+	[IMX7D_I2C2_ROOT_DIV] = { 0xae00, 0, 0x3f, IMX7D_I2C2_ROOT_PRE_DIV },
+	[IMX7D_I2C3_ROOT_DIV] = { 0xae80, 0, 0x3f, IMX7D_I2C3_ROOT_PRE_DIV },
+	[IMX7D_I2C4_ROOT_DIV] = { 0xaf00, 0, 0x3f, IMX7D_I2C4_ROOT_PRE_DIV },
+	[IMX7D_UART1_ROOT_DIV] = { 0xaf80, 0, 0x3f, IMX7D_UART1_ROOT_PRE_DIV },
+	[IMX7D_UART2_ROOT_DIV] = { 0xb000, 0, 0x3f, IMX7D_UART2_ROOT_PRE_DIV },
+	[IMX7D_UART3_ROOT_DIV] = { 0xb080, 0, 0x3f, IMX7D_UART3_ROOT_PRE_DIV },
+	[IMX7D_UART4_ROOT_DIV] = { 0xb100, 0, 0x3f, IMX7D_UART4_ROOT_PRE_DIV },
+	[IMX7D_UART5_ROOT_DIV] = { 0xb180, 0, 0x3f, IMX7D_UART5_ROOT_PRE_DIV },
+	[IMX7D_UART6_ROOT_DIV] = { 0xb200, 0, 0x3f, IMX7D_UART6_ROOT_PRE_DIV },
+	[IMX7D_UART7_ROOT_DIV] = { 0xb280, 0, 0x3f, IMX7D_UART7_ROOT_PRE_DIV },
+};
+
+struct imxccm_mux imx7d_muxs[] = {
+	[IMX7D_USDHC1_ROOT_SRC] = { 0xab00, 24, 0x7 },
+	[IMX7D_USDHC2_ROOT_SRC] = { 0xab80, 24, 0x7 },
+	[IMX7D_USDHC3_ROOT_SRC] = { 0xac00, 24, 0x7 },
+	[IMX7D_I2C1_ROOT_SRC] = { 0xad80, 24, 0x7 },
+	[IMX7D_I2C2_ROOT_SRC] = { 0xae00, 24, 0x7 },
+	[IMX7D_I2C3_ROOT_SRC] = { 0xae80, 24, 0x7 },
+	[IMX7D_I2C4_ROOT_SRC] = { 0xaf00, 24, 0x7 },
+	[IMX7D_UART1_ROOT_SRC] = { 0xaf80, 24, 0x7 },
+	[IMX7D_UART2_ROOT_SRC] = { 0xb000, 24, 0x7 },
+	[IMX7D_UART3_ROOT_SRC] = { 0xb080, 24, 0x7 },
+	[IMX7D_UART4_ROOT_SRC] = { 0xb100, 24, 0x7 },
+	[IMX7D_UART5_ROOT_SRC] = { 0xb180, 24, 0x7 },
+	[IMX7D_UART6_ROOT_SRC] = { 0xb200, 24, 0x7 },
+	[IMX7D_UART7_ROOT_SRC] = { 0xb280, 24, 0x7 },
+};
+
+/*
  * i.MX8MQ clocks.
  */
 
@@ -196,8 +355,7 @@ struct imxccm_gate imx6ul_gates[] =
 #define IMX8MQ_CLK_USDHC1_ROOT		0x1ac
 #define IMX8MQ_CLK_USDHC2_ROOT		0x1ad
 
-struct imxccm_gate imx8mq_gates[] =
-{
+struct imxccm_gate imx8mq_gates[] = {
 	[IMX8MQ_CLK_A53_CG] = { 0x8000, 14, IMX8MQ_CLK_A53_SRC },
 	[IMX8MQ_CLK_ENET_AXI_CG] = { 0x8880, 14, IMX8MQ_CLK_ENET_AXI_SRC },
 	[IMX8MQ_CLK_USB_BUS_CG] = { 0x8b80, 14, IMX8MQ_CLK_USB_BUS_SRC },
@@ -241,8 +399,7 @@ struct imxccm_gate imx8mq_gates[] =
 	[IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2_DIV },
 };
 
-struct imxccm_divider imx8mq_divs[] =
-{
+struct imxccm_divider imx8mq_divs[] = {
 	[IMX8MQ_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MQ_CLK_A53_CG },
 	[IMX8MQ_CLK_ENET_AXI_PRE_DIV] = { 0x8880, 16, 0x7, IMX8MQ_CLK_ENET_AXI_CG },
 	[IMX8MQ_CLK_ENET_AXI_DIV] = { 0x8880, 0, 0x3f, IMX8MQ_CLK_ENET_AXI_PRE_DIV },
@@ -292,8 +449,7 @@ struct imxccm_divider imx8mq_divs[] =
 	[IMX8MQ_CLK_PCIE2_AUX_DIV] = { 0xc100, 0, 0x3f, IMX8MQ_CLK_PCIE2_AUX_PRE_DIV },
 };
 
-struct imxccm_mux imx8mq_muxs[] =
-{
+struct imxccm_mux imx8mq_muxs[] = {
 	[IMX8MQ_CLK_A53_SRC] = { 0x8000, 24, 0x7 },
 	[IMX8MQ_CLK_ENET_AXI_SRC] = { 0x8880, 24, 0x7 },
 	[IMX8MQ_CLK_USB_BUS_SRC] = { 0x8b80, 24, 0x7 },