diff options
| author |   jsg <jsg@openbsd.org> | 2016-05-07 00:18:23 +0000 |
|---|---|---|
| committer | jsg <jsg@openbsd.org> | 2016-05-07 00:18:23 +0000 |
| commit | ba3fe1deddb49fd357db2b9cc4c46e800ba505a1 (patch) | |
| tree | 81f762543841812cb6c36e0fb1b6cb76fdb55f76 | |
| parent | add support for changing the bus width and set the 4-bit mode capability (diff) | |
| download | wireguard-openbsd-ba3fe1deddb49fd357db2b9cc4c46e800ba505a1.tar.xz wireguard-openbsd-ba3fe1deddb49fd357db2b9cc4c46e800ba505a1.zip | |
set the high speed enable bit if the timing isn't SDMMC_TIMING_LEGACY
ok patrick@ kettenis@
| -rw-r--r-- | sys/arch/armv7/omap/ommmc.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/sys/arch/armv7/omap/ommmc.c b/sys/arch/armv7/omap/ommmc.c index 1e7329375e5..a38fa89d358 100644 --- a/sys/arch/armv7/omap/ommmc.c +++ b/sys/arch/armv7/omap/ommmc.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ommmc.c,v 1.19 2016/05/05 11:01:08 kettenis Exp $ */ +/* $OpenBSD: ommmc.c,v 1.20 2016/05/07 00:18:23 jsg Exp $ */ /* * Copyright (c) 2009 Dale Rahn <drahn@openbsd.org> @@ -674,6 +674,11 @@ ommmc_bus_clock(sdmmc_chipset_handle_t sch, int freq, int timing) reg |= div << MMCHS_SYSCTL_CLKD_SH; HWRITE4(sc, MMCHS_SYSCTL, reg); + if (timing == SDMMC_TIMING_LEGACY) + HCLR4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); + else + HSET4(sc, MMCHS_HCTL, MMCHS_HCTL_HSPE); + /* * Start internal clock. Wait 10ms for stabilization. */ |