diff options
| author |   jsg <jsg@openbsd.org> | 2014-02-15 14:28:13 +0000 |
|---|---|---|
| committer | jsg <jsg@openbsd.org> | 2014-02-15 14:28:13 +0000 |
| commit | bc26ceb111af78b4b0757a0d05897daf4a2cce2b (patch) | |
| tree | b0ef50872d202697bd1594f78389067de6ecbcf1 | |
| parent | drm/radeon: disable ss on DP for DCE3.x (diff) | |
| download | wireguard-openbsd-bc26ceb111af78b4b0757a0d05897daf4a2cce2b.tar.xz wireguard-openbsd-bc26ceb111af78b4b0757a0d05897daf4a2cce2b.zip | |
drm/radeon: fix surface sync in fence on cayman (v2)
From Alex Deucher
5dd953fd70af5ef1bd605b93f87f55bc663be6a8 in ubuntu 3.8
10e9ffae463396c5a25fdfe8a48d7c98a87f6b85 in mainline linux
| -rw-r--r-- | sys/dev/pci/drm/radeon/ni.c | 18 | ||||
| -rw-r--r-- | sys/dev/pci/drm/radeon/nid.h | 3 |
2 files changed, 10 insertions, 11 deletions
diff --git a/sys/dev/pci/drm/radeon/ni.c b/sys/dev/pci/drm/radeon/ni.c index 03f035015df..335ccc05910 100644 --- a/sys/dev/pci/drm/radeon/ni.c +++ b/sys/dev/pci/drm/radeon/ni.c @@ -1,4 +1,4 @@ -/* $OpenBSD: ni.c,v 1.5 2014/02/09 12:33:44 jsg Exp $ */ +/* $OpenBSD: ni.c,v 1.6 2014/02/15 14:28:13 jsg Exp $ */ /* * Copyright 2010 Advanced Micro Devices, Inc. * @@ -888,13 +888,12 @@ void cayman_fence_ring_emit(struct radeon_device *rdev, { struct radeon_ring *ring = &rdev->ring[fence->ring]; u64 addr = rdev->fence_drv[fence->ring].gpu_addr; + u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | + PACKET3_SH_ACTION_ENA; /* flush read cache over gart for this vmid */ - radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); - radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); - radeon_ring_write(ring, 0); radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); - radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); + radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write(ring, 0); radeon_ring_write(ring, 10); /* poll interval */ @@ -910,6 +909,8 @@ void cayman_fence_ring_emit(struct radeon_device *rdev, void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) { struct radeon_ring *ring = &rdev->ring[ib->ring]; + u32 cp_coher_cntl = PACKET3_FULL_CACHE_ENA | PACKET3_TC_ACTION_ENA | + PACKET3_SH_ACTION_ENA; /* set to DX10/11 mode */ radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0)); @@ -934,14 +935,11 @@ void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) (ib->vm ? (ib->vm->id << 24) : 0)); /* flush read cache over gart for this vmid */ - radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); - radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2); - radeon_ring_write(ring, ib->vm ? ib->vm->id : 0); radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3)); - radeon_ring_write(ring, PACKET3_TC_ACTION_ENA | PACKET3_SH_ACTION_ENA); + radeon_ring_write(ring, PACKET3_ENGINE_ME | cp_coher_cntl); radeon_ring_write(ring, 0xFFFFFFFF); radeon_ring_write(ring, 0); - radeon_ring_write(ring, 10); /* poll interval */ + radeon_ring_write(ring, ((ib->vm ? ib->vm->id : 0) << 24) | 10); /* poll interval */ } static void cayman_cp_enable(struct radeon_device *rdev, bool enable) diff --git a/sys/dev/pci/drm/radeon/nid.h b/sys/dev/pci/drm/radeon/nid.h index 10a937eca0c..8b89e5de807 100644 --- a/sys/dev/pci/drm/radeon/nid.h +++ b/sys/dev/pci/drm/radeon/nid.h @@ -1,4 +1,4 @@ -/* $OpenBSD: nid.h,v 1.1 2013/08/12 04:11:53 jsg Exp $ */ +/* $OpenBSD: nid.h,v 1.2 2014/02/15 14:28:13 jsg Exp $ */ /* * Copyright 2010 Advanced Micro Devices, Inc. * @@ -557,6 +557,7 @@ # define PACKET3_DB_ACTION_ENA (1 << 26) # define PACKET3_SH_ACTION_ENA (1 << 27) # define PACKET3_SX_ACTION_ENA (1 << 28) +# define PACKET3_ENGINE_ME (1 << 31) #define PACKET3_ME_INITIALIZE 0x44 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) #define PACKET3_COND_WRITE 0x45 |