diff options
| author |   patrick <patrick@openbsd.org> | 2016-09-20 16:31:56 +0000 |
|---|---|---|
| committer | patrick <patrick@openbsd.org> | 2016-09-20 16:31:56 +0000 |
| commit | bd87487f7a2377b0b0eca210ea8f3c109f7bd78e (patch) | |
| tree | 5542cac5f760a1a2b617885d8fbdbf1868560bed | |
| parent | Create and destroy cloneable interfaces under splsoftnet (diff) | |
| download | wireguard-openbsd-bd87487f7a2377b0b0eca210ea8f3c109f7bd78e.tar.xz wireguard-openbsd-bd87487f7a2377b0b0eca210ea8f3c109f7bd78e.zip | |
Complete bus_dmamap_load_raw(9) implementation for ARM. My initial
commit did not copy the vaddr information to the map's segments. This
means non-coherent bus dma raw mappings could not be synced.
As only agp(4) and radeondrm(4) seem to make use of non-coherent raw
mappings at the moment, this bug did not cause any visible effects.
From Marius Strobl.
ok kettenis@
| -rw-r--r-- | sys/arch/arm/arm/bus_dma.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/sys/arch/arm/arm/bus_dma.c b/sys/arch/arm/arm/bus_dma.c index ad64afdded0..12332d1a90d 100644 --- a/sys/arch/arm/arm/bus_dma.c +++ b/sys/arch/arm/arm/bus_dma.c @@ -1,4 +1,4 @@ -/* $OpenBSD: bus_dma.c,v 1.34 2016/08/26 21:50:42 patrick Exp $ */ +/* $OpenBSD: bus_dma.c,v 1.35 2016/09/20 16:31:56 patrick Exp $ */ /* $NetBSD: bus_dma.c,v 1.38 2003/10/30 08:44:13 scw Exp $ */ /*- @@ -345,6 +345,7 @@ _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, struct arm32_dma_range *dr; bus_addr_t paddr, baddr, bmask, lastaddr = 0; bus_size_t plen, sgsize, mapsize; + vaddr_t vaddr; int first = 1; int i, seg = 0; @@ -368,6 +369,7 @@ _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, for (i = 0; i < nsegs && size > 0; i++) { paddr = segs[i].ds_addr; + vaddr = segs[i]._ds_vaddr; plen = MIN(segs[i].ds_len, size); if (!segs[i]._ds_coherent) @@ -414,6 +416,7 @@ _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, if (first) { map->dm_segs[seg].ds_addr = paddr; map->dm_segs[seg].ds_len = sgsize; + map->dm_segs[seg]._ds_vaddr = vaddr; first = 0; } else { if (paddr == lastaddr && @@ -428,10 +431,12 @@ _bus_dmamap_load_raw(bus_dma_tag_t t, bus_dmamap_t map, return (EINVAL); map->dm_segs[seg].ds_addr = paddr; map->dm_segs[seg].ds_len = sgsize; + map->dm_segs[seg]._ds_vaddr = vaddr; } } paddr += sgsize; + vaddr += sgsize; plen -= sgsize; size -= sgsize; |