Use a faster, more reliable way to figure out how many TLB entries are

available on RM7000 processors.

From miod@

2 files changed, 34 insertions, 27 deletions

diff --git a/sys/arch/mips64/mips64/tlbhandler.S b/sys/arch/mips64/mips64/tlbhandler.S
index 4c726a75db4..481e24a17d8 100644
--- a/sys/arch/mips64/mips64/tlbhandler.S
+++ b/sys/arch/mips64/mips64/tlbhandler.S
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tlbhandler.S,v 1.47 2016/12/22 15:33:36 visa Exp $ */
+/*	$OpenBSD: tlbhandler.S,v 1.48 2018/12/13 16:35:07 visa Exp $ */
 
 /*
  * Copyright (c) 1995-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -686,6 +686,18 @@ LEAF(tlb_set_wired, 0)
 	nop
 END(tlb_set_wired)
 
+#ifdef CPU_RM7000
+/*
+ * Similar to tlb_set_wired() above, but returns the value of the random
+ * register.
+ */
+LEAF(tlb_set_wired_get_random, 0)
+	mtc0	a0, COP_0_TLB_WIRED
+	j	ra
+	 mfc0	v0, COP_0_TLB_RANDOM
+END(tlb_set_wired_get_random)
+#endif
+
 /*
  *	Initialize the TLB page mask.
  */
diff --git a/sys/arch/sgi/sgi/ip32_machdep.c b/sys/arch/sgi/sgi/ip32_machdep.c
index 7e0e6fbc578..0fd4cbf682e 100644
--- a/sys/arch/sgi/sgi/ip32_machdep.c
+++ b/sys/arch/sgi/sgi/ip32_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip32_machdep.c,v 1.22 2014/02/08 22:20:15 miod Exp $ */
+/*	$OpenBSD: ip32_machdep.c,v 1.23 2018/12/13 16:35:07 visa Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -50,6 +50,7 @@
 #include <dev/ic/comvar.h>
 
 extern char *hw_prod;
+extern int tlb_set_wired_get_random(int);	/* tlbhandler.S */
 
 void crime_configure_memory(void);
 
@@ -181,34 +182,28 @@ ip32_setup()
 		 * If they are disabled, they are nevertheless
 		 * writable, but random TLB insert operations
 		 * will never use any of them. This can be
-		 * checked by inserting dummy entries and check
-		 * if any of the last 16 entries have been used.
-		 *
-		 * Of course, due to the way the random replacement
-		 * works (hashing various parts of the TLB data,
-		 * such as address bits and ASID), not all the
-		 * available TLB will be used; we simply check
-		 * the highest valid TLB entry we can find and
-		 * see if it is in the upper 16 entries or not.
+		 * checked by writing to the wired register, which
+		 * sets the random register to the number of available
+		 * TLB entries.
+		 * As its value decreases with every instruction
+		 * executed, we use a combined write-then-read routine
+		 * which will return a number close enough to the
+		 * number of entries, so that any value larger than 48
+		 * means that there are 64 entries available
+		 * (in the current state of that code, the value will
+		 * be the number of entries, minus 2).
 		 */
 		bootcpu_hwinfo.tlbsize = 48;
-		if (((bootcpu_hwinfo.c0prid >> 4) & 0x0f) >= 2) {
-			struct tlb_entry te;
-			int e, lastvalid;
-
-			tlb_set_wired(0);
-			tlb_flush(64);
-			for (e = 0; e < 64 * 8; e++)
-				tlb_update(XKSSEG_BASE + ptoa(2 * e),
-				    pfn_to_pad(0) | PG_ROPAGE);
-			lastvalid = 0;
-			for (e = 0; e < 64; e++) {
-				tlb_read(e, &te);
-				if ((te.tlb_lo0 & PG_V) != 0)
-					lastvalid = e;
-			}
+		if ((bootcpu_hwinfo.c0prid & 0xf0) >= 0x20) {
+			/*
+			 * The whole 64 entries exist, although the last
+			 * 16 may not be used by the random placement
+			 * operations, as we are about to check; but we
+			 * need to make them invalid anyway.
+			 */
+			tlb_set_wired(48);
 			tlb_flush(64);
-			if (lastvalid >= 48)
+			if (tlb_set_wired_get_random(0) > 48)
 				bootcpu_hwinfo.tlbsize = 64;
 		}
 		break;