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authorgrange <grange@openbsd.org>2005-01-12 18:19:05 +0000
committergrange <grange@openbsd.org>2005-01-12 18:19:05 +0000
commitd02e7fa8266a34dcf50e0b33c5b9e61a38956e85 (patch)
tree8c2ea2543d91c0d944f54dab416be050a2462e23
parentupdate to sendmail 8.13.3 (diff)
downloadwireguard-openbsd-d02e7fa8266a34dcf50e0b33c5b9e61a38956e85.tar.xz
wireguard-openbsd-d02e7fa8266a34dcf50e0b33c5b9e61a38956e85.zip
Intel 82443BX DRAM address errata seems to be fixed in the latest revisions
of the chipset. Inspired from netbsd pr by scottr@NetBSD.org. ok theo
-rw-r--r--sys/arch/i386/pci/pchb.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/sys/arch/i386/pci/pchb.c b/sys/arch/i386/pci/pchb.c
index 3c48c32d40b..f096a35354d 100644
--- a/sys/arch/i386/pci/pchb.c
+++ b/sys/arch/i386/pci/pchb.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: pchb.c,v 1.42 2004/11/23 13:33:14 grange Exp $ */
+/* $OpenBSD: pchb.c,v 1.43 2005/01/12 18:19:05 grange Exp $ */
/* $NetBSD: pchb.c,v 1.6 1997/06/06 23:29:16 thorpej Exp $ */
/*
@@ -230,11 +230,13 @@ pchbattach(parent, self, aux)
* fetched from the wrong location. This is
* the workaround.
*/
- bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
- PCISET_INTEL_SDRAMC_REG);
- bcreg |= PCISET_INTEL_SDRAMC_IPDLT;
- pci_conf_write(pa->pa_pc, pa->pa_tag,
- PCISET_INTEL_SDRAMC_REG, bcreg);
+ if (PCI_REVISION(pa->pa_class) < 0x3) {
+ bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,
+ PCISET_INTEL_SDRAMC_REG);
+ bcreg |= PCISET_INTEL_SDRAMC_IPDLT;
+ pci_conf_write(pa->pa_pc, pa->pa_tag,
+ PCISET_INTEL_SDRAMC_REG, bcreg);
+ }
break;
case PCI_PRODUCT_INTEL_PCI450_PB:
bcreg = pci_conf_read(pa->pa_pc, pa->pa_tag,