Rework the per-cpu cache information. Use a common struct to store the line

size, the number of sets, and the total size (and the set size, for convenience)
per cache (I$, D$, L2, L3).
This allows cpu.c to print the number of ways (sets) of L2 and L3 caches from
the cache information, rather than hardcoding this from the processor type.

16 files changed, 260 insertions, 248 deletions

diff --git a/sys/arch/mips64/include/cpu.h b/sys/arch/mips64/include/cpu.h
index ab6cae2eca6..138675e4528 100644
--- a/sys/arch/mips64/include/cpu.h
+++ b/sys/arch/mips64/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.95 2013/12/19 09:37:13 jasper Exp $	*/
+/*	$OpenBSD: cpu.h,v 1.96 2014/03/09 10:12:17 miod Exp $	*/
 
 /*-
  * Copyright (c) 1992, 1993
@@ -134,6 +134,16 @@ struct cpu_hwinfo {
 	uint32_t	l2size;
 };
 
+/*
+ * Cache memory configuration. One struct per cache.
+ */
+struct cache_info {
+	uint		size;		/* total cache size */
+	uint		linesize;	/* line size */
+	uint		setsize;	/* set size */
+	uint		sets;		/* number of sets */
+};
+
 struct cpu_info {
 	struct device	*ci_dev;	/* our device */
 	struct cpu_info	*ci_self;	/* pointer to this structure */
@@ -147,16 +157,11 @@ struct cpu_info {
 
 	/* cache information */
 	uint		ci_cacheconfiguration;
-	uint		ci_cacheways;
-	uint		ci_l1instcachesize;
-	uint		ci_l1instcacheline;
-	uint		ci_l1instcacheset;
-	uint		ci_l1datacachesize;
-	uint		ci_l1datacacheline;
-	uint		ci_l1datacacheset;
-	uint		ci_l2size;
-	uint		ci_l2line;
-	uint		ci_l3size;
+	struct cache_info
+			ci_l1inst,
+			ci_l1data,
+			ci_l2,
+			ci_l3;
 
 	/* function pointers for the cache handling routines */
 	void		(*ci_SyncCache)(struct cpu_info *);
diff --git a/sys/arch/mips64/mips64/cache_loongson2.c b/sys/arch/mips64/mips64/cache_loongson2.c
index 9c2a172d6aa..892ffb22645 100644
--- a/sys/arch/mips64/mips64/cache_loongson2.c
+++ b/sys/arch/mips64/mips64/cache_loongson2.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_loongson2.c,v 1.3 2012/09/29 18:54:38 miod Exp $	*/
+/*	$OpenBSD: cache_loongson2.c,v 1.4 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2009, 2012 Miodrag Vallat.
@@ -71,17 +71,24 @@ static __inline__ void	ls2f_hitwbinv_secondary(vaddr_t, vsize_t);
 void
 Loongson2_ConfigCache(struct cpu_info *ci)
 {
-	ci->ci_l1instcacheline = LS2F_CACHE_LINE;
-	ci->ci_l1instcachesize = LS2F_L1_SIZE;
-	ci->ci_l1datacacheline = LS2F_CACHE_LINE;
-	ci->ci_l1datacachesize = LS2F_L1_SIZE;
-	ci->ci_cacheways = LS2F_CACHE_WAYS;
-	ci->ci_l1instcacheset = LS2F_L1_SIZE / LS2F_CACHE_WAYS;
-	ci->ci_l1datacacheset = LS2F_L1_SIZE / LS2F_CACHE_WAYS;
-	ci->ci_l2size = LS2F_L2_SIZE;
-	ci->ci_l3size = 0;
-
-	cache_valias_mask = ci->ci_l1instcacheset & ~PAGE_MASK;
+	ci->ci_l1inst.size = LS2F_L1_SIZE;
+	ci->ci_l1inst.linesize = LS2F_CACHE_LINE;
+	ci->ci_l1inst.setsize = LS2F_L1_SIZE / LS2F_CACHE_WAYS;
+	ci->ci_l1inst.sets = LS2F_CACHE_WAYS;
+
+	ci->ci_l1data.size = LS2F_L1_SIZE;
+	ci->ci_l1data.linesize = LS2F_CACHE_LINE;
+	ci->ci_l1data.setsize = LS2F_L1_SIZE / LS2F_CACHE_WAYS;
+	ci->ci_l1data.sets = LS2F_CACHE_WAYS;
+
+	ci->ci_l2.size = LS2F_L2_SIZE;
+	ci->ci_l2.linesize = LS2F_CACHE_LINE;
+	ci->ci_l2.setsize = LS2F_L2_SIZE / LS2F_CACHE_WAYS;
+	ci->ci_l2.sets = LS2F_CACHE_WAYS;
+
+	memset(&ci->ci_l3, 0, sizeof(struct cache_info));
+
+	cache_valias_mask = ci->ci_l1inst.setsize & ~PAGE_MASK;
 
 	/* should not happen as we use 16KB pages */
 	if (cache_valias_mask != 0) {
diff --git a/sys/arch/mips64/mips64/cache_octeon.c b/sys/arch/mips64/mips64/cache_octeon.c
index 5a5b99db62e..e6fa3df8f32 100644
--- a/sys/arch/mips64/mips64/cache_octeon.c
+++ b/sys/arch/mips64/mips64/cache_octeon.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_octeon.c,v 1.6 2012/09/29 18:54:38 miod Exp $	*/
+/*	$OpenBSD: cache_octeon.c,v 1.7 2014/03/09 10:12:17 miod Exp $	*/
 /*
  * Copyright (c) 2010 Takuya ASADA.
  *
@@ -60,14 +60,22 @@
 void 
 Octeon_ConfigCache(struct cpu_info *ci)
 {
-	ci->ci_cacheways = 4;
-	ci->ci_l1instcachesize = 32 * 1024;
-	ci->ci_l1instcacheline = 128;
-	ci->ci_l1datacachesize = 16 * 1024;
-	ci->ci_l1datacacheline = 128;
-	ci->ci_l2size = 128 * 1024;
-	ci->ci_l2line = 128;
-	ci->ci_l3size = 0;
+	ci->ci_l1inst.size = 32 * 1024;
+	ci->ci_l1inst.linesize = 128;
+	ci->ci_l1inst.setsize = 4;
+	ci->ci_l1inst.sets = ci->ci_l1inst.size / ci->ci_l1inst.setsize;
+
+	ci->ci_l1data.size = 16 * 1024;
+	ci->ci_l1data.linesize = 128;
+	ci->ci_l1data.setsize = 4;
+	ci->ci_l1data.sets = ci->ci_l1data.size / ci->ci_l1data.setsize;
+
+	ci->ci_l2.size = 128 * 1024;
+	ci->ci_l2.linesize = 128;
+	ci->ci_l2.setsize = 4;
+	ci->ci_l2.sets = ci->ci_l2.size / ci->ci_l2.setsize;
+
+	memset(&ci->ci_l3, 0, sizeof(struct cache_info));
 
 	ci->ci_SyncCache = Octeon_SyncCache;
 	ci->ci_InvalidateICache = Octeon_InvalidateICache;
diff --git a/sys/arch/mips64/mips64/cache_r10k.c b/sys/arch/mips64/mips64/cache_r10k.c
index 32c231ee66f..acede0b5d0d 100644
--- a/sys/arch/mips64/mips64/cache_r10k.c
+++ b/sys/arch/mips64/mips64/cache_r10k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r10k.c,v 1.3 2012/06/24 20:22:49 miod Exp $	*/
+/*	$OpenBSD: cache_r10k.c,v 1.4 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -65,22 +65,24 @@ Mips10k_ConfigCache(struct cpu_info *ci)
 
 	cfg = cp0_get_config();
 
-	ci->ci_l1instcacheline = R10K_L1I_LINE;
-	ci->ci_l1instcachesize = (1 << 12) << ((cfg >> 29) & 0x07);	/* IC */
+	ci->ci_l1inst.size = (1 << 12) << ((cfg >> 29) & 0x07);	/* IC */
+	ci->ci_l1inst.linesize = R10K_L1I_LINE;
+	ci->ci_l1inst.setsize = ci->ci_l1inst.size / 2;
+	ci->ci_l1inst.sets = 2;
 
-	ci->ci_l1datacacheline = R10K_L1D_LINE;
-	ci->ci_l1datacachesize = (1 << 12) << ((cfg >> 26) & 0x07);	/* DC */
+	ci->ci_l1data.size = (1 << 12) << ((cfg >> 26) & 0x07);	/* DC */
+	ci->ci_l1data.linesize = R10K_L1D_LINE;
+	ci->ci_l1data.setsize = ci->ci_l1data.size / 2;
+	ci->ci_l1data.sets = 2;
 
-	ci->ci_l2line = (cfg & (1 << 13)) ? 128 : 64;
-	ci->ci_l2size = (1 << 19) << ((cfg >> 16) & 0x07);
+	ci->ci_l2.size = (1 << 19) << ((cfg >> 16) & 0x07);
+	ci->ci_l2.linesize = (cfg & (1 << 13)) ? 128 : 64;
+	ci->ci_l2.setsize = ci->ci_l2.size / 2;
+	ci->ci_l2.sets = 2;
 
-	ci->ci_l3size = 0;
+	memset(&ci->ci_l3, 0, sizeof(struct cache_info));
 
-	ci->ci_cacheways = 2;
-	ci->ci_l1instcacheset = ci->ci_l1instcachesize / 2;
-	ci->ci_l1datacacheset = ci->ci_l1datacachesize / 2;
-
-	valias_mask = (max(ci->ci_l1instcacheset, ci->ci_l1datacacheset) - 1) &
+	valias_mask = (max(ci->ci_l1inst.setsize, ci->ci_l1data.setsize) - 1) &
 	    ~PAGE_MASK;
 
 	if (valias_mask != 0) {
@@ -160,7 +162,7 @@ Mips10k_SyncCache(struct cpu_info *ci)
 	vaddr_t sva, eva;
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l1instcacheset;
+	eva = sva + ci->ci_l1inst.setsize;
 	while (sva != eva) {
 		cache(IndexInvalidate_I, 0, sva);
 		cache(IndexInvalidate_I, 1, sva);
@@ -168,7 +170,7 @@ Mips10k_SyncCache(struct cpu_info *ci)
 	}
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l1datacacheset;
+	eva = sva + ci->ci_l1data.setsize;
 	while (sva != eva) {
 		cache(IndexWBInvalidate_D, 0, sva);
 		cache(IndexWBInvalidate_D, 1, sva);
@@ -176,11 +178,11 @@ Mips10k_SyncCache(struct cpu_info *ci)
 	}
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l2size / 2;
+	eva = sva + ci->ci_l2.setsize;
 	while (sva != eva) {
 		cache(IndexWBInvalidate_S, 0, sva);
 		cache(IndexWBInvalidate_S, 1, sva);
-		sva += ci->ci_l2line;
+		sva += ci->ci_l2.linesize;
 	}
 }
 
@@ -291,7 +293,7 @@ Mips10k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 	vsize_t line;
 	int partial_start, partial_end;
 
-	line = ci->ci_l2line;
+	line = ci->ci_l2.linesize;
 	/* extend the range to integral cache lines */
 	if (line == 64) {
 		va = _va & ~(64UL - 1);
diff --git a/sys/arch/mips64/mips64/cache_r4k.c b/sys/arch/mips64/mips64/cache_r4k.c
index 774306d7a5d..21370e1508c 100644
--- a/sys/arch/mips64/mips64/cache_r4k.c
+++ b/sys/arch/mips64/mips64/cache_r4k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r4k.c,v 1.11 2012/10/03 11:18:23 miod Exp $	*/
+/*	$OpenBSD: cache_r4k.c,v 1.12 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -75,42 +75,41 @@ Mips4k_ConfigCache(struct cpu_info *ci)
 
 	cfg = cp0_get_config();
 
+	ci->ci_l1inst.size = (1 << 12) << ((cfg >> 9) & 0x07); /* IC */
 	if (cfg & (1 << 5))	/* IB */
-		ci->ci_l1instcacheline = 32;
+		ci->ci_l1inst.linesize = 32;
 	else
-		ci->ci_l1instcacheline = 16;
-	ci->ci_l1instcachesize = (1 << 12) << ((cfg >> 9) & 0x07); /* IC */
+		ci->ci_l1inst.linesize = 16;
 
+	ci->ci_l1data.size = (1 << 12) << ((cfg >> 6) & 0x07); /* DC */
 	if (cfg & (1 << 4))	/* DB */
-		ci->ci_l1datacacheline = 32;
+		ci->ci_l1data.linesize = 32;
 	else
-		ci->ci_l1datacacheline = 16;
-	ci->ci_l1datacachesize = (1 << 12) << ((cfg >> 6) & 0x07); /* DC */
+		ci->ci_l1data.linesize = 16;
 
 	/* R4000 and R4400 L1 caches are direct */
-	ci->ci_cacheways = 1;
-	ci->ci_l1instcacheset = ci->ci_l1instcachesize;
-	ci->ci_l1datacacheset = ci->ci_l1datacachesize;
+	ci->ci_l1inst.setsize = ci->ci_l1inst.size;
+	ci->ci_l1inst.sets = 1;
+	ci->ci_l1data.setsize = ci->ci_l1data.size;
+	ci->ci_l1data.sets = 1;
 
 	cache_valias_mask =
-	    (max(ci->ci_l1instcachesize, ci->ci_l1datacachesize) - 1) &
+	    (max(ci->ci_l1inst.size, ci->ci_l1data.size) - 1) &
 	    ~PAGE_MASK;
 
 	if ((cfg & (1 << 17)) == 0) {	/* SC */
 		/*
-		 * We expect the setup code to have set up ci->ci_l2size and
-		 * ci->ci_l2line for us. Unfortunately we aren't allowed to
-		 * panic() there if it didn't, because the console is not
-		 * available.
+		 * We expect the setup code to have set up ci->ci_l2 for us.
+		 * Unfortunately we aren't allowed to panic() there if it
+		 * didn't, because the console is not available.
 		 */
 
 		/* fixed 32KB aliasing to avoid VCE */
 		pmap_prefer_mask = ((1 << 15) - 1);
 	} else {
-		ci->ci_l2line = 0;
-		ci->ci_l2size = 0;
+		memset(&ci->ci_l2, 0, sizeof(struct cache_info));
 	}
-	ci->ci_l3size = 0;
+	memset(&ci->ci_l3, 0, sizeof(struct cache_info));
 
 	if (cache_valias_mask != 0) {
 		cache_valias_mask |= PAGE_MASK;
@@ -140,25 +139,25 @@ Mips4k_SyncCache(struct cpu_info *ci)
 	vsize_t line;
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l1instcachesize;
-	line = ci->ci_l1instcacheline;
+	eva = sva + ci->ci_l1inst.size;
+	line = ci->ci_l1inst.linesize;
 	while (sva != eva) {
 		cache(IndexInvalidate_I, sva);
 		sva += line;
 	}
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l1datacachesize;
-	line = ci->ci_l1datacacheline;
+	eva = sva + ci->ci_l1data.size;
+	line = ci->ci_l1data.linesize;
 	while (sva != eva) {
 		cache(IndexWBInvalidate_D, sva);
 		sva += line;
 	}
 
-	if (ci->ci_l2size != 0) {
+	if (ci->ci_l2.size != 0) {
 		sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-		eva = sva + ci->ci_l2size;
-		line = ci->ci_l2line;
+		eva = sva + ci->ci_l2.size;
+		line = ci->ci_l2.linesize;
 		while (sva != eva) {
 			cache(IndexWBInvalidate_S, sva);
 			sva += line;
@@ -178,7 +177,7 @@ Mips4k_InvalidateICache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	vsize_t sz;
 	vsize_t line;
 
-	line = ci->ci_l1instcacheline;
+	line = ci->ci_l1inst.linesize;
 	/* extend the range to integral cache lines */
 	if (line == 16) {
 		va = _va & ~(16UL - 1);
@@ -191,6 +190,8 @@ Mips4k_InvalidateICache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
 	/* keep only the index bits */
 	sva += va & ((1UL << 15) - 1);
+	if (sz > ci->ci_l1inst.size)
+		sz = ci->ci_l1inst.size;
 	eva = sva + sz;
 	while (sva != eva) {
 		cache(IndexInvalidate_I, sva);
@@ -209,18 +210,21 @@ Mips4k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 	vaddr_t sva, eva;
 	vsize_t line;
 
-	line = ci->ci_l1datacacheline;
+	line = ci->ci_l1data.linesize;
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
 	/* keep only the index bits */
 	sva += va & ((1UL << 15) - 1);
-	eva = sva + PAGE_SIZE;
+	if (PAGE_SIZE > ci->ci_l1data.size)
+		eva = sva + ci->ci_l1data.size;
+	else
+		eva = sva + PAGE_SIZE;
 	while (sva != eva) {
 		cache(IndexWBInvalidate_D, sva);
 		sva += line;
 	}
 
-	if (ci->ci_l2size != 0) {
-		line = ci->ci_l2line;
+	if (ci->ci_l2.size != 0) {
+		line = ci->ci_l2.linesize;
 		sva = PHYS_TO_XKPHYS(pa, CCA_CACHED);
 		eva = sva + PAGE_SIZE;
 		while (sva != eva) {
@@ -269,7 +273,7 @@ Mips4k_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	vsize_t sz;
 	vsize_t line;
 
-	line = ci->ci_l1datacacheline;
+	line = ci->ci_l1data.linesize;
 	/* extend the range to integral cache lines */
 	if (line == 16) {
 		va = _va & ~(16UL - 1);
@@ -280,8 +284,8 @@ Mips4k_HitSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	}
 	mips4k_hitwbinv_primary(va, sz, line);
 
-	if (ci->ci_l2size != 0) {
-		line = ci->ci_l2line;
+	if (ci->ci_l2.size != 0) {
+		line = ci->ci_l2.linesize;
 		/* extend the range to integral cache lines */
 		va = _va & ~(line - 1);
 		sz = ((_va + _sz + line - 1) & ~(line - 1)) - va;
@@ -328,7 +332,7 @@ Mips4k_HitInvalidateDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	vsize_t sz;
 	vsize_t line;
 
-	line = ci->ci_l1datacacheline;
+	line = ci->ci_l1data.linesize;
 	/* extend the range to integral cache lines */
 	if (line == 16) {
 		va = _va & ~(16UL - 1);
@@ -339,8 +343,8 @@ Mips4k_HitInvalidateDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	}
 	mips4k_hitinv_primary(va, sz, line);
 
-	if (ci->ci_l2size != 0) {
-		line = ci->ci_l2line;
+	if (ci->ci_l2.size != 0) {
+		line = ci->ci_l2.linesize;
 		/* extend the range to integral cache lines */
 		va = _va & ~(line - 1);
 		sz = ((_va + _sz + line - 1) & ~(line - 1)) - va;
@@ -367,7 +371,7 @@ Mips4k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 	 * L1
 	 */
 
-	line = ci->ci_l1datacacheline;
+	line = ci->ci_l1data.linesize;
 	/* extend the range to integral cache lines */
 	if (line == 16) {
 		va = _va & ~(16UL - 1);
@@ -408,8 +412,8 @@ Mips4k_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 	 * L2
 	 */
 
-	if (ci->ci_l2size != 0) {
-		line = ci->ci_l2line;
+	if (ci->ci_l2.size != 0) {
+		line = ci->ci_l2.linesize;
 		/* extend the range to integral cache lines */
 		va = _va & ~(line - 1);
 		sz = ((_va + _sz + line - 1) & ~(line - 1)) - va;
diff --git a/sys/arch/mips64/mips64/cache_r5k.c b/sys/arch/mips64/mips64/cache_r5k.c
index c9694b3464c..7e56bfcab8a 100644
--- a/sys/arch/mips64/mips64/cache_r5k.c
+++ b/sys/arch/mips64/mips64/cache_r5k.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_r5k.c,v 1.9 2013/11/26 20:33:13 deraadt Exp $	*/
+/*	$OpenBSD: cache_r5k.c,v 1.10 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -285,17 +285,15 @@ Mips5k_ConfigCache(struct cpu_info *ci)
 	cfg = cp0_get_config();
 
 	/* L1 cache */
-	ci->ci_l1instcacheline = R5K_LINE;
-	ci->ci_l1instcachesize = (1 << 12) << ((cfg >> 9) & 0x07); /* IC */
-	ci->ci_l1datacacheline = R5K_LINE;
-	ci->ci_l1datacachesize = (1 << 12) << ((cfg >> 6) & 0x07); /* DC */
+	ci->ci_l1inst.size = (1 << 12) << ((cfg >> 9) & 0x07); /* IC */
+	ci->ci_l1inst.linesize = R5K_LINE;
+	ci->ci_l1data.size = (1 << 12) << ((cfg >> 6) & 0x07); /* DC */
+	ci->ci_l1data.linesize = R5K_LINE;
 
 	/* sane defaults */
-	ci->ci_cacheways = 2;
 	setshift = 1;
-	ci->ci_l2line = 0;
-	ci->ci_l2size = 0;
-	ci->ci_l3size = 0;
+	memset(&ci->ci_l2, 0, sizeof(struct cache_info));
+	memset(&ci->ci_l3, 0, sizeof(struct cache_info));
 	ci->ci_cacheconfiguration = 0;
 
 	switch ((cp0_get_prid() >> 8) & 0xff) {
@@ -311,25 +309,26 @@ Mips5k_ConfigCache(struct cpu_info *ci)
 #ifdef CPU_R5000
 	case MIPS_R5000:
 	case MIPS_RM52X0:
-		/* optional external L2 cache */
+		/* optional external direct L2 cache */
 		if ((cfg & CF_5_SC) == 0) {
-			ci->ci_l2line = R5K_LINE;
-			ci->ci_l2size = (1 << 19) <<
+			ci->ci_l2.size = (1 << 19) <<
 			    ((cfg & CF_5_SS) >> CF_5_SS_AL);
+			ci->ci_l2.linesize = R5K_LINE;
+			ci->ci_l2.setsize = ci->ci_l2.size;
+			ci->ci_l2.sets = 1;
 		}
-		if (ci->ci_l2size != 0) {
+		if (ci->ci_l2.size != 0) {
 			ci->ci_cacheconfiguration |= CTYPE_HAS_XL2;
 			cfg |= CF_5_SE;
-			run_uncached(mips5k_l2_init, ci->ci_l2size);
+			run_uncached(mips5k_l2_init, ci->ci_l2.size);
 		}
 		break;
 #endif	/* CPU_R5000 */
 #ifdef CPU_RM7000
 	case MIPS_RM7000:
 	case MIPS_RM9000:
-		ci->ci_cacheways = 4;
 		setshift = 2;
-		/* optional external L3 cache */
+		/* optional external direct L3 cache */
 		if ((cfg & CF_7_TC) == 0) {
 #ifndef L3SZEXT
 			/*
@@ -339,40 +338,48 @@ Mips5k_ConfigCache(struct cpu_info *ci)
 			 * an upgrade from an R5000/RM52xx processor, such as
 			 * the SGI O2.
 			 */
-			ci->ci_l3size = (1 << 19) <<
+			ci->ci_l3.size = (1 << 19) <<
 			    ((cfg & CF_7_TS) >> CF_7_TS_AL);
+			ci->ci_l3.linesize = R5K_LINE;
+			ci->ci_l3.setsize = ci->ci_l3.size;
+			ci->ci_l3.sets = 1;
 #else
 			/*
-			 * Assume machdep has initialized ci_l3size for us.
+			 * Assume machdep has initialized ci_l3 for us.
 			 */
 #endif
 		}
-		if (ci->ci_l3size != 0) {
+		if (ci->ci_l3.size != 0) {
 			ci->ci_cacheconfiguration |= CTYPE_HAS_XL3;
 			cfg |= CF_7_TE;
-			run_uncached(mips7k_l3_init, ci->ci_l3size);
+			run_uncached(mips7k_l3_init, ci->ci_l3.size);
+
 		}
-		/* internal L2 cache */
+		/* internal 4-way L2 cache */
 		if ((cfg & CF_7_SC) == 0) {
-			ci->ci_l2line = R5K_LINE;
-			ci->ci_l2size = 256 * 1024;	/* fixed size */
+			ci->ci_l2.size = 256 * 1024;	/* fixed size */
+			ci->ci_l2.linesize = R5K_LINE;
+			ci->ci_l2.setsize = ci->ci_l2.size / 4;
+			ci->ci_l2.sets = 4;
 		}
-		if (ci->ci_l2size != 0) {
+		if (ci->ci_l2.size != 0) {
 			ci->ci_cacheconfiguration |= CTYPE_HAS_IL2;
 			if ((cfg & CF_7_SE) == 0) {
 				cfg |= CF_7_SE;
-				run_uncached(mips7k_l2_init, ci->ci_l2size);
+				run_uncached(mips7k_l2_init, ci->ci_l2.size);
 			}
 		}
 		break;
 #endif	/* CPU_RM7000 */
 	}
 
-	ci->ci_l1instcacheset = ci->ci_l1instcachesize >> setshift;
-	ci->ci_l1datacacheset = ci->ci_l1datacachesize >> setshift;
+	ci->ci_l1inst.setsize = ci->ci_l1inst.size >> setshift;
+	ci->ci_l1inst.sets = setshift == 2 ? 4 : 2;
+	ci->ci_l1data.setsize = ci->ci_l1data.size >> setshift;
+	ci->ci_l1data.sets = setshift == 2 ? 4 : 2;
 
 	cache_valias_mask =
-	    (max(ci->ci_l1instcacheset, ci->ci_l1datacacheset) - 1) &
+	    (max(ci->ci_l1inst.setsize, ci->ci_l1data.setsize) - 1) &
 	    ~PAGE_MASK;
 
 	if (cache_valias_mask != 0) {
@@ -408,14 +415,14 @@ Mips5k_SyncCache(struct cpu_info *ci)
 #endif
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l1instcachesize;
+	eva = sva + ci->ci_l1inst.size;
 	while (sva != eva) {
 		cache(IndexInvalidate_I, 0, sva);
 		sva += R5K_LINE;
 	}
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	eva = sva + ci->ci_l1datacachesize;
+	eva = sva + ci->ci_l1data.size;
 	while (sva != eva) {
 		cache(IndexWBInvalidate_D, 0, sva);
 		sva += R5K_LINE;
@@ -428,7 +435,7 @@ Mips5k_SyncCache(struct cpu_info *ci)
 #ifdef CPU_RM7000
 	if (ci->ci_cacheconfiguration & CTYPE_HAS_IL2) {
 		sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-		eva = sva + ci->ci_l2size;
+		eva = sva + ci->ci_l2.size;
 		while (sva != eva) {
 			cache(IndexWBInvalidate_S, 0, sva);
 			sva += R5K_LINE;
@@ -438,7 +445,7 @@ Mips5k_SyncCache(struct cpu_info *ci)
 #ifdef CPU_R5000
 	if (ci->ci_cacheconfiguration & CTYPE_HAS_XL2) {
 		sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-		eva = sva + ci->ci_l2size;
+		eva = sva + ci->ci_l2.size;
 		reset_taglo();
 		while (sva != eva) {
 			cache(InvalidatePage_S, 0, sva);
@@ -452,7 +459,7 @@ Mips5k_SyncCache(struct cpu_info *ci)
 #ifdef CPU_RM7000
 	if (ci->ci_cacheconfiguration & CTYPE_HAS_XL3) {
 		sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-		eva = sva + ci->ci_l3size;
+		eva = sva + ci->ci_l3.size;
 		reset_taglo();
 		while (sva != eva) {
 			cache(InvalidatePage_T, 0, sva);
@@ -485,12 +492,12 @@ Mips5k_InvalidateICache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	sz = ((_va + _sz + R5K_LINE - 1) & ~(R5K_LINE - 1)) - va;
 
 	sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-	offs = ci->ci_l1instcacheset;
+	offs = ci->ci_l1inst.setsize;
 	/* keep only the index bits */
 	sva |= va & (offs - 1);
 	eva = sva + sz;
 
-	switch (ci->ci_cacheways) {
+	switch (ci->ci_l1inst.sets) {
 	default:
 #ifdef CPU_RM7000
 	case 4:
@@ -565,7 +572,7 @@ Mips5k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 	register_t sr = disableintr();
 #endif
 
-	switch (ci->ci_cacheways) {
+	switch (ci->ci_l1data.sets) {
 	default:
 #ifdef CPU_RM7000
 	case 4:
@@ -589,7 +596,7 @@ Mips5k_SyncDCachePage(struct cpu_info *ci, vaddr_t va, paddr_t pa)
 		vsize_t offs;
 
 		sva = PHYS_TO_XKPHYS(0, CCA_CACHED);
-		offs = ci->ci_l1datacacheset;
+		offs = ci->ci_l1data.setsize;
 		/* keep only the index bits */
 		sva |= va & (offs - 1);
 		eva = sva + PAGE_SIZE;
diff --git a/sys/arch/mips64/mips64/cache_tfp.c b/sys/arch/mips64/mips64/cache_tfp.c
index c872a36cc5b..a8ff2ed2901 100644
--- a/sys/arch/mips64/mips64/cache_tfp.c
+++ b/sys/arch/mips64/mips64/cache_tfp.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cache_tfp.c,v 1.2 2013/06/28 18:56:10 miod Exp $	*/
+/*	$OpenBSD: cache_tfp.c,v 1.3 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -53,37 +53,37 @@ tfp_ConfigCache(struct cpu_info *ci)
 	 * XXX then.
 	 */
 #if 0
+	ci->ci_l1inst.size = (1 << 11) << ((cfg >> 9) & 0x07); /* IC */
 	if (cfg & (1 << 5))	/* IB */
-		ci->ci_l1instcacheline = 32;
+		ci->ci_l1inst.linesize = 32;
 	else
-		ci->ci_l1instcacheline = 16;
-	ci->ci_l1instcachesize = (1 << 11) << ((cfg >> 9) & 0x07); /* IC */
+		ci->ci_l1inst.linesize = 16;
 
+	ci->ci_l1data.size = (1 << 12) << ((cfg >> 6) & 0x07); /* DC */
 	if (cfg & (1 << 4))	/* DB */
-		ci->ci_l1datacacheline = 32;
+		ci->ci_l1data.linesize = 32;
 	else
-		ci->ci_l1datacacheline = 16;
-	ci->ci_l1datacachesize = (1 << 12) << ((cfg >> 6) & 0x07); /* DC */
+		ci->ci_l1data.linesize = 16;
 #else
-	ci->ci_l1instcacheline = 32;
-	ci->ci_l1datacacheline = 32;
-	ci->ci_l1instcachesize = 16384;
-	ci->ci_l1datacachesize = 16384;
+	ci->ci_l1inst.size = 16384;
+	ci->ci_l1inst.linesize = 32;
+	ci->ci_l1data.size = 16384;
+	ci->ci_l1data.linesize = 32;
 #endif
 
 	/* R8000 L1 caches are direct */
-	ci->ci_cacheways = 1;
-	ci->ci_l1instcacheset = ci->ci_l1instcachesize;
-	ci->ci_l1datacacheset = ci->ci_l1datacachesize;
+	ci->ci_l1inst.setsize = ci->ci_l1inst.size;
+	ci->ci_l1inst.sets = 1;
+	ci->ci_l1data.setsize = ci->ci_l1data.size;
+	ci->ci_l1data.sets = 1;
 
 	cache_valias_mask =
-	    (max(ci->ci_l1instcachesize, ci->ci_l1datacachesize) - 1) &
+	    (max(ci->ci_l1inst.size, ci->ci_l1data.size) - 1) &
 	    ~PAGE_MASK;
 
 	/* R8000 L2 cache are platform-specific, and not covered here */
-	ci->ci_l2line = 0;
-	ci->ci_l2size = 0;
-	ci->ci_l3size = 0;
+	memset(&ci->ci_l2, 0, sizeof(struct cache_info));
+	memset(&ci->ci_l3, 0, sizeof(struct cache_info));
 
 	ci->ci_SyncCache = tfp_SyncCache;
 	ci->ci_InvalidateICache = tfp_InvalidateICache;
@@ -102,10 +102,10 @@ tfp_SyncCache(struct cpu_info *ci)
 	vaddr_t va, eva;
 	register_t sr;
 
-	tfp_InvalidateICache(ci, 0, ci->ci_l1instcachesize);
+	tfp_InvalidateICache(ci, 0, ci->ci_l1inst.size);
 
 	sr = disableintr();
-	eva = ci->ci_l1datacachesize;
+	eva = ci->ci_l1data.size;
 	for (va = 0; va < eva; va += TFP_DCTW_STEP)
 		tfp_dctw_zero(va);
 	setsr(sr);
@@ -121,15 +121,15 @@ tfp_InvalidateICache(struct cpu_info *ci, vaddr_t _va, size_t _sz)
 	vsize_t sz;
 	void (*inval_subr)(vsize_t);
 
-	if (_sz >= ci->ci_l1instcachesize) {
-		tfp_inval_icache(ci->ci_l1instcachesize);
+	if (_sz >= ci->ci_l1inst.size) {
+		tfp_inval_icache(ci->ci_l1inst.size);
 	} else {
 		/* extend the range to multiple of 32 bytes */
 		va = _va & ~(32UL - 1);
 		sz = ((_va + _sz + 32 - 1) & ~(32UL - 1)) - va;
 
 		/* compute cache offset */
-		va &= (ci->ci_l1instcachesize - 1);
+		va &= (ci->ci_l1inst.size - 1);
 		inval_subr = (void (*)(vsize_t))
 		    ((vaddr_t)tfp_inval_icache + va);
 		(*inval_subr)(sz);
diff --git a/sys/arch/mips64/mips64/cpu.c b/sys/arch/mips64/mips64/cpu.c
index 5e7781503d5..ecc830e14ef 100644
--- a/sys/arch/mips64/mips64/cpu.c
+++ b/sys/arch/mips64/mips64/cpu.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.c,v 1.52 2014/01/19 12:45:35 deraadt Exp $ */
+/*	$OpenBSD: cpu.c,v 1.53 2014/03/09 10:12:17 miod Exp $ */
 
 /*
  * Copyright (c) 1997-2004 Opsycon AB (www.opsycon.se)
@@ -109,8 +109,18 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 	ci->ci_dev = dev;
 	bcopy(ch, &ci->ci_hw, sizeof(struct cpu_hwinfo));
 #ifdef MULTIPROCESSOR
-	if (!ISSET(ci->ci_flags, CPUF_PRIMARY))
-		hw_cpu_init_secondary(ci);
+	/*
+	 * When attaching secondary processors, cache information is not
+	 * available yet.  Copy the cache information from the primary cpu
+	 * instead.
+	 * XXX The MP boot sequence needs to be reworked to avoid this.
+	 */
+	if (!ISSET(ci->ci_flags, CPUF_PRIMARY)) {
+		ci->ci_l1inst = cpu_info_primary.ci_l1inst;
+		ci->ci_l1data = cpu_info_primary.ci_l1data;
+		ci->ci_l2 = cpu_info_primary.ci_l2;
+		ci->ci_l3 = cpu_info_primary.ci_l3;
+	}
 #endif
 
 	printf(": ");
@@ -282,49 +292,49 @@ cpuattach(struct device *parent, struct device *dev, void *aux)
 		printf(" rev %d.%d", vers_maj, vers_min);
 	printf("\n");
 
-	printf("cpu%d: cache L1-I %dKB D %dKB ", cpuno,
-	    ci->ci_l1instcachesize / 1024, ci->ci_l1datacachesize / 1024);
-
-	switch (ci->ci_cacheways) {
-	case 2:
-		printf("2 way");
-		break;
-	case 4:
-		printf("4 way");
-		break;
-	default:
-		printf("direct");
-		break;
+	if (ci->ci_l1inst.sets == ci->ci_l1data.sets) {
+		printf("cpu%d: cache L1-I %dKB D %dKB ", cpuno,
+		    ci->ci_l1inst.size / 1024, ci->ci_l1data.size / 1024);
+		if (ci->ci_l1inst.sets == 1)
+			printf("direct");
+		else
+			printf("%d way", ci->ci_l1inst.sets);
+	} else {
+		printf("cpu%d: cache L1-I %dKB ", cpuno,
+		    ci->ci_l1inst.size / 1024);
+		if (ci->ci_l1inst.sets == 1)
+			printf("direct");
+		else
+			printf("%d way", ci->ci_l1inst.sets);
+		printf(" D %dKB ", ci->ci_l1data.size / 1024);
+		if (ci->ci_l1data.sets == 1)
+			printf("direct");
+		else
+			printf("%d way", ci->ci_l1data.sets);
 	}
 
-	if (ci->ci_l2size != 0) {
-		switch (ch->type) {
-		case MIPS_R10000:
-		case MIPS_R12000:
-		case MIPS_R14000:
-			printf(", L2 %dKB 2 way", ci->ci_l2size / 1024);
-			break;
-		case MIPS_RM7000:
-		case MIPS_R8000:
-		case MIPS_RM9000:
-		case MIPS_LOONGSON2:
-			printf(", L2 %dKB 4 way", ci->ci_l2size / 1024);
-			break;
-		default:
-			printf(", L2 %dKB direct", ci->ci_l2size / 1024);
-			break;
-		}
+	if (ci->ci_l2.size != 0) {
+		printf(", L2 %dKB ", ci->ci_l2.size / 1024);
+		if (ci->ci_l2.sets == 1)
+			printf("direct");
+		else
+			printf("%d way", ci->ci_l2.sets);
+	}
+	if (ci->ci_l3.size != 0) {
+		printf(", L3 %dKB ", ci->ci_l3.size / 1024);
+		if (ci->ci_l3.sets == 1)
+			printf("direct");
+		else
+			printf("%d way", ci->ci_l3.sets);
 	}
-	if (ci->ci_l3size != 0)
-		printf(", L3 %dKB direct", ci->ci_l3size / 1024);
 	printf("\n");
 
 #ifdef DEBUG
 	printf("cpu%d: L1 set size %d:%d\n", cpuno,
-	    ci->ci_l1instcacheset, ci->ci_l1datacacheset);
+	    ci->ci_l1inst.setsize, ci->ci_l1data.setsize);
 	printf("cpu%d: L1 line size %d:%d\n", cpuno,
-	    ci->ci_l1instcacheline, ci->ci_l1datacacheline);
-	printf("cpu%d: L2 line size %d\n", cpuno, ci->ci_l2line);
+	    ci->ci_l1inst.linesize, ci->ci_l1data.linesize);
+	printf("cpu%d: L2 line size %d\n", cpuno, ci->ci_l2.linesize);
 	printf("cpu%d: cache configuration %x\n",
 	    cpuno, ci->ci_cacheconfiguration);
 	printf("cpu%d: virtual alias mask %p\n", cpuno, cache_valias_mask);
diff --git a/sys/arch/mips64/mips64/mips64_machdep.c b/sys/arch/mips64/mips64/mips64_machdep.c
index da5bfc4ac50..138c625a734 100644
--- a/sys/arch/mips64/mips64/mips64_machdep.c
+++ b/sys/arch/mips64/mips64/mips64_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: mips64_machdep.c,v 1.12 2013/04/21 15:43:34 miod Exp $ */
+/*	$OpenBSD: mips64_machdep.c,v 1.13 2014/03/09 10:12:17 miod Exp $ */
 
 /*
  * Copyright (c) 2009, 2010, 2012 Miodrag Vallat.
@@ -231,7 +231,7 @@ tlb_asid_wrap(struct cpu_info *ci)
 {
 	tlb_flush(ci->ci_hw.tlbsize);
 #ifdef CPU_R8000
-	Mips_InvalidateICache(ci, 0, ci->ci_l1instcachesize);
+	Mips_InvalidateICache(ci, 0, ci->ci_l1inst.size);
 #endif
 }
 
diff --git a/sys/arch/octeon/include/cpu.h b/sys/arch/octeon/include/cpu.h
index b8e76774aab..91fcb5dd270 100644
--- a/sys/arch/octeon/include/cpu.h
+++ b/sys/arch/octeon/include/cpu.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cpu.h,v 1.4 2012/04/21 12:20:30 miod Exp $ */
+/* $OpenBSD: cpu.h,v 1.5 2014/03/09 10:12:17 miod Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -55,9 +55,12 @@ void hw_cpu_spinup_trampoline(struct cpu_info *);
 int  hw_ipi_intr_establish(int (*)(void *), u_long);
 void hw_ipi_intr_set(u_long);
 void hw_ipi_intr_clear(u_long);
-void hw_cpu_init_secondary(struct cpu_info *);
 #endif	/* MULTIPROCESSOR && !_LOCORE */
 
+/*
+ * No need to use the per-cpu_info function pointers, as we only support
+ * one processor type.
+ */
 #define	Mips_SyncCache(ci)			\
 	Octeon_SyncCache((ci))
 #define	Mips_InvalidateICache(ci, va, l)	\
diff --git a/sys/arch/octeon/octeon/machdep.c b/sys/arch/octeon/octeon/machdep.c
index 8fa5be06e42..33a9da33443 100644
--- a/sys/arch/octeon/octeon/machdep.c
+++ b/sys/arch/octeon/octeon/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.41 2013/09/28 12:40:31 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.42 2014/03/09 10:12:17 miod Exp $ */
 
 /*
  * Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -893,16 +893,4 @@ hw_ipi_intr_clear(u_long cpuid)
 		bus_space_read_8(&iobus_tag, iobus_h, CIU_MBOX_CLR(cpuid));
 	bus_space_write_8(&iobus_tag, iobus_h, CIU_MBOX_CLR(cpuid), clr);
 }
-
-void
-hw_cpu_init_secondary(struct cpu_info *ci)
-{
-	ci->ci_cacheways = 2;
-	ci->ci_l1instcachesize = 32 * 1024;
-	ci->ci_l1instcacheline = 64;
-	ci->ci_l1datacachesize = 32 * 1024;
-	ci->ci_l1datacacheline = 64;
-	ci->ci_l2size = ci->ci_hw.l2size;
-	ci->ci_l3size = 0;
-}
 #endif
diff --git a/sys/arch/sgi/include/cpu.h b/sys/arch/sgi/include/cpu.h
index 18181df485a..093e917370f 100644
--- a/sys/arch/sgi/include/cpu.h
+++ b/sys/arch/sgi/include/cpu.h
@@ -1,4 +1,4 @@
-/*	$OpenBSD: cpu.h,v 1.14 2012/06/24 16:26:04 miod Exp $ */
+/*	$OpenBSD: cpu.h,v 1.15 2014/03/09 10:12:17 miod Exp $ */
 /*-
  * Copyright (c) 1992, 1993
  *	The Regents of the University of California.  All rights reserved.
@@ -55,7 +55,6 @@ void hw_cpu_spinup_trampoline(struct cpu_info *);
 int  hw_ipi_intr_establish(int (*)(void *), u_long);
 void hw_ipi_intr_set(u_long);
 void hw_ipi_intr_clear(u_long);
-void hw_cpu_init_secondary(struct cpu_info *);
 #endif	/* MULTIPROCESSOR && !_LOCORE */
 
 
diff --git a/sys/arch/sgi/localbus/tcc.c b/sys/arch/sgi/localbus/tcc.c
index e8d3233ffd0..0e6ff894cb8 100644
--- a/sys/arch/sgi/localbus/tcc.c
+++ b/sys/arch/sgi/localbus/tcc.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: tcc.c,v 1.2 2012/10/03 11:18:23 miod Exp $	*/
+/*	$OpenBSD: tcc.c,v 1.3 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -142,16 +142,14 @@ void tcc_virtual(struct cpu_info *, vaddr_t, vsize_t, uint64_t);
 void
 tcc_ConfigCache(struct cpu_info *ci)
 {
-	uint l2line, l2size;
+	struct cache_info l2;
 
-	l2line = ci->ci_l2line;
-	l2size = ci->ci_l2size;
+	l2 = ci->ci_l2;
 
 	tfp_ConfigCache(ci);
 
-	if (l2size != 0) {
-		ci->ci_l2line = l2line;
-		ci->ci_l2size = l2size;
+	if (l2.size != 0) {
+		ci->ci_l2 = l2;
 
 		ci->ci_SyncCache = tcc_SyncCache;
 		ci->ci_SyncDCachePage = tcc_SyncDCachePage;
@@ -167,7 +165,7 @@ tcc_SyncCache(struct cpu_info *ci)
 	uint64_t idx;
 
 	mips_sync();
-	tfp_InvalidateICache(ci, 0, ci->ci_l1instcachesize);
+	tfp_InvalidateICache(ci, 0, ci->ci_l1inst.size);
 
 	/*
 	 * The following relies upon the fact that the (line, set)
@@ -175,7 +173,7 @@ tcc_SyncCache(struct cpu_info *ci)
 	 * a huge number of sets and only one line, we can span the
 	 * whole cache.
 	 */
-	idx = (uint64_t)ci->ci_l2size / TCC_CACHE_LINE;
+	idx = (uint64_t)ci->ci_l2.size / TCC_CACHE_LINE;
 	while (idx != 0) {
 		idx--;
 		tcc_cache_index(idx, 0,
diff --git a/sys/arch/sgi/sgi/ip22_machdep.c b/sys/arch/sgi/sgi/ip22_machdep.c
index 2f398319ba7..909f75146d8 100644
--- a/sys/arch/sgi/sgi/ip22_machdep.c
+++ b/sys/arch/sgi/sgi/ip22_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip22_machdep.c,v 1.14 2012/09/29 21:46:02 miod Exp $	*/
+/*	$OpenBSD: ip22_machdep.c,v 1.15 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2012 Miodrag Vallat.
@@ -115,8 +115,10 @@ ip22_arcbios_walk_component(arc_config_t *cf)
 		 * SS is Log2(cache size in 4KB units)
 		 *   (should be between 0007 and 0009)
 		 */
-		ci->ci_l2size = (1 << 12) << (key & 0x0000ffff);
-		ci->ci_l2line = 1 << ((key >> 16) & 0xff);
+		ci->ci_l2.size = (1 << 12) << (key & 0x0000ffff);
+		ci->ci_l2.linesize = 1 << ((key >> 16) & 0xff);
+		ci->ci_l2.setsize = ci->ci_l2.size;
+		ci->ci_l2.sets = 1;
 
 		ip22_arcwalk_results |= IP22_HAS_L2;
 	}
@@ -752,7 +754,7 @@ ip22_cache_halt(int howto)
 void
 ip22_ConfigCache(struct cpu_info *ci)
 {
-	uint l2line, l2size;
+	struct cache_info l2;
 
 	/*
 	 * Note that we are relying upon machdep.c only invoking us if we
@@ -763,12 +765,11 @@ ip22_ConfigCache(struct cpu_info *ci)
 		return;
 	}
 
-	l2line = ci->ci_l2line;
-	l2size = ci->ci_l2size;
+	l2 = ci->ci_l2;
 
 	Mips5k_ConfigCache(ci);
 
-	if (l2line != IP22_L2_LINE) {
+	if (ci->ci_l2.linesize != IP22_L2_LINE) {
 		/*
 		 * This should not happen. Better not try and tame an
 		 * unknown beast.
@@ -776,8 +777,7 @@ ip22_ConfigCache(struct cpu_info *ci)
 		return;
 	}
 
-	ci->ci_l2line = l2line;
-	ci->ci_l2size = l2size;
+	ci->ci_l2 = l2;
 
 	ci->ci_SyncCache = ip22_SyncCache;
 	ci->ci_IOSyncDCache = ip22_IOSyncDCache;
@@ -794,7 +794,7 @@ ip22_SyncCache(struct cpu_info *ci)
 	Mips5k_SyncCache(ci);
 
 	sva = PHYS_TO_XKPHYS(IP22_CACHE_TAG_ADDRESS, CCA_NC);
-	eva = sva + ci->ci_l2size;
+	eva = sva + ci->ci_l2.size;
 
 	while (sva < eva) {
 		*(volatile uint32_t *)sva = 0;
@@ -833,7 +833,7 @@ ip22_IOSyncDCache(struct cpu_info *ci, vaddr_t _va, size_t _sz, int how)
 #endif
 			}
 
-			pa &= ci->ci_l2size - 1;
+			pa &= ci->ci_l2.size - 1;
 			pa |= PHYS_TO_XKPHYS(IP22_CACHE_TAG_ADDRESS, CCA_NC);
 
 			while (sz != 0) {
diff --git a/sys/arch/sgi/sgi/ip30_machdep.c b/sys/arch/sgi/sgi/ip30_machdep.c
index 501bbf7f3d8..0ab4b9f6297 100644
--- a/sys/arch/sgi/sgi/ip30_machdep.c
+++ b/sys/arch/sgi/sgi/ip30_machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: ip30_machdep.c,v 1.58 2014/01/06 21:41:15 miod Exp $	*/
+/*	$OpenBSD: ip30_machdep.c,v 1.59 2014/03/09 10:12:17 miod Exp $	*/
 
 /*
  * Copyright (c) 2008, 2009 Miodrag Vallat.
@@ -607,23 +607,4 @@ hw_ipi_intr_clear(u_long cpuid)
 {
 	xheart_intr_clear(HEART_ISR_IPI(cpuid));
 }
-
-void
-hw_cpu_init_secondary(struct cpu_info *ci)
-{
-	/*
-	 * When attaching secondary processors, cache information is not
-	 * available yet.  But since the MP-capable systems we run on
-	 * currently all have R10k-style caches, we can quickly compute
-	 * the needed values.
-	 */
-	ci->ci_cacheways = 2;
-	ci->ci_l1instcachesize = 32 * 1024;
-	ci->ci_l1instcacheline = 64;
-	ci->ci_l1datacachesize = 32 * 1024;
-	ci->ci_l1datacacheline = 32;
-	ci->ci_l2size = ci->ci_hw.l2size;
-	ci->ci_l2line = 64;			/* safe default */
-	ci->ci_l3size = 0;
-}
 #endif
diff --git a/sys/arch/sgi/sgi/machdep.c b/sys/arch/sgi/sgi/machdep.c
index 137e553e0b0..96114a5ea23 100644
--- a/sys/arch/sgi/sgi/machdep.c
+++ b/sys/arch/sgi/sgi/machdep.c
@@ -1,4 +1,4 @@
-/*	$OpenBSD: machdep.c,v 1.133 2013/09/28 12:40:31 miod Exp $ */
+/*	$OpenBSD: machdep.c,v 1.134 2014/03/09 10:12:17 miod Exp $ */
 
 /*
  * Copyright (c) 2003-2004 Opsycon AB  (www.opsycon.se / www.opsycon.com)
@@ -532,7 +532,7 @@ mips_init(int argc, void *argv, caddr_t boot_esym)
 		extern void xtlb_miss_err_r4k;
 		extern void xtlb_miss_err_r4000SC;
 
-		if (ci->ci_l2size == 0 ||
+		if (ci->ci_l2.size == 0 ||
 		    ((cp0_get_prid() >> 4) & 0x0f) >= 4) /* R4400 */
 			xtlb_handler = (vaddr_t)&xtlb_miss_err_r4k;
 		else {