diff options
author | 2010-05-16 08:50:58 +0000 | |
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committer | 2010-05-16 08:50:58 +0000 | |
commit | db9f724c7717357cd14381d01150a46b1d34c025 (patch) | |
tree | a22b91a120e279bdaabf0189cfb2245491d327ee | |
parent | cleanup interrupts mask management. (diff) | |
download | wireguard-openbsd-db9f724c7717357cd14381d01150a46b1d34c025.tar.xz wireguard-openbsd-db9f724c7717357cd14381d01150a46b1d34c025.zip |
fix athn_updateslot for fast PLL clock and 40MHz CBW
-rw-r--r-- | sys/dev/ic/athn.c | 19 | ||||
-rw-r--r-- | sys/dev/ic/athnreg.h | 9 |
2 files changed, 17 insertions, 11 deletions
diff --git a/sys/dev/ic/athn.c b/sys/dev/ic/athn.c index 349259879ef..e4fd6e387b3 100644 --- a/sys/dev/ic/athn.c +++ b/sys/dev/ic/athn.c @@ -1,4 +1,4 @@ -/* $OpenBSD: athn.c,v 1.39 2010/05/16 08:45:25 damien Exp $ */ +/* $OpenBSD: athn.c,v 1.40 2010/05/16 08:50:58 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -2300,16 +2300,21 @@ athn_updateslot(struct ieee80211com *ic) struct athn_softc *sc = ic->ic_softc; uint32_t clks; - if (ic->ic_curmode == IEEE80211_MODE_11B) + if (ic->ic_curmode == IEEE80211_MODE_11A) { + if (sc->flags & ATHN_FLAG_FAST_PLL_CLOCK) + clks = AR_CLOCK_RATE_FAST_5GHZ_OFDM; + else + clks = AR_CLOCK_RATE_5GHZ_OFDM; + } else if (ic->ic_curmode == IEEE80211_MODE_11B) { clks = AR_CLOCK_RATE_CCK; - else if (ic->ic_curmode == IEEE80211_MODE_11A) - clks = AR_CLOCK_RATE_5GHZ_OFDM; - else + } else clks = AR_CLOCK_RATE_2GHZ_OFDM; +#ifndef IEEE80211_NO_HT + if (sc->curchanext != NULL) + clks *= 2; +#endif clks *= (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; - /* XXX 40MHz. */ - AR_WRITE(sc, AR_D_GBL_IFS_SLOT, clks); } diff --git a/sys/dev/ic/athnreg.h b/sys/dev/ic/athnreg.h index 189cfdab65b..2e2008c3042 100644 --- a/sys/dev/ic/athnreg.h +++ b/sys/dev/ic/athnreg.h @@ -1,4 +1,4 @@ -/* $OpenBSD: athnreg.h,v 1.9 2010/05/13 09:03:12 damien Exp $ */ +/* $OpenBSD: athnreg.h,v 1.10 2010/05/16 08:50:58 damien Exp $ */ /*- * Copyright (c) 2009 Damien Bergamini <damien.bergamini@free.fr> @@ -1268,9 +1268,10 @@ #define AR_BASE_PHY_ACTIVE_DELAY 100 -#define AR_CLOCK_RATE_CCK 22 -#define AR_CLOCK_RATE_5GHZ_OFDM 40 -#define AR_CLOCK_RATE_2GHZ_OFDM 44 +#define AR_CLOCK_RATE_CCK 22 +#define AR_CLOCK_RATE_5GHZ_OFDM 40 +#define AR_CLOCK_RATE_FAST_5GHZ_OFDM 44 +#define AR_CLOCK_RATE_2GHZ_OFDM 44 #define AR_PWR_DECREASE_FOR_2_CHAIN 6 /* 10 * log10(2) * 2 */ #define AR_PWR_DECREASE_FOR_3_CHAIN 9 /* 10 * log10(3) * 2 */ |