diff options
| author |   deraadt <deraadt@openbsd.org> | 2014-09-27 08:28:11 +0000 |
|---|---|---|
| committer | deraadt <deraadt@openbsd.org> | 2014-09-27 08:28:11 +0000 |
| commit | df614b5d5bb04fc6219f7eaea208ee5ac77c4ffd (patch) | |
| tree | 2162675568309731ed1eb1b9971e98624cef8c6b | |
| parent | Removed an ununsed macro (diff) | |
| download | wireguard-openbsd-df614b5d5bb04fc6219f7eaea208ee5ac77c4ffd.tar.xz wireguard-openbsd-df614b5d5bb04fc6219f7eaea208ee5ac77c4ffd.zip | |
retire Accoom Networks Artery T1/E1 drive; ok claudio
37 files changed, 10 insertions, 4532 deletions
diff --git a/distrib/sets/lists/base/md.alpha b/distrib/sets/lists/base/md.alpha index c448843e50a..8063d93d661 100644 --- a/distrib/sets/lists/base/md.alpha +++ b/distrib/sets/lists/base/md.alpha @@ -1210,8 +1210,6 @@ ./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/alpha-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.amd64 b/distrib/sets/lists/base/md.amd64 index b35f8333d6a..eaa08ce3d95 100644 --- a/distrib/sets/lists/base/md.amd64 +++ b/distrib/sets/lists/base/md.amd64 @@ -1237,8 +1237,6 @@ ./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/amd64-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.armish b/distrib/sets/lists/base/md.armish index f3462d4c016..b86883dc5fa 100644 --- a/distrib/sets/lists/base/md.armish +++ b/distrib/sets/lists/base/md.armish @@ -1224,8 +1224,6 @@ ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.armv7 b/distrib/sets/lists/base/md.armv7 index d906ccdc629..1b4b6c97e11 100644 --- a/distrib/sets/lists/base/md.armv7 +++ b/distrib/sets/lists/base/md.armv7 @@ -1198,8 +1198,6 @@ ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.aviion b/distrib/sets/lists/base/md.aviion index 412bafd7412..509af8ff4b7 100644 --- a/distrib/sets/lists/base/md.aviion +++ b/distrib/sets/lists/base/md.aviion @@ -1149,8 +1149,6 @@ ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.hppa b/distrib/sets/lists/base/md.hppa index 98a1a389a1e..1cbec38bd93 100644 --- a/distrib/sets/lists/base/md.hppa +++ b/distrib/sets/lists/base/md.hppa @@ -1158,8 +1158,6 @@ ./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/hppa-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.hppa64 b/distrib/sets/lists/base/md.hppa64 index 907c4a31511..695696e7b1c 100644 --- a/distrib/sets/lists/base/md.hppa64 +++ b/distrib/sets/lists/base/md.hppa64 @@ -1159,8 +1159,6 @@ ./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/hppa64-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.i386 b/distrib/sets/lists/base/md.i386 index 937d44a96e0..24de41fdb5a 100644 --- a/distrib/sets/lists/base/md.i386 +++ b/distrib/sets/lists/base/md.i386 @@ -1165,8 +1165,6 @@ ./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/i386-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.landisk b/distrib/sets/lists/base/md.landisk index 88543948865..e3ae0e349dd 100644 --- a/distrib/sets/lists/base/md.landisk +++ b/distrib/sets/lists/base/md.landisk @@ -1119,8 +1119,6 @@ ./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/sh-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.loongson b/distrib/sets/lists/base/md.loongson index 08d2dafaaa1..fe11189e427 100644 --- a/distrib/sets/lists/base/md.loongson +++ b/distrib/sets/lists/base/md.loongson @@ -1125,8 +1125,6 @@ ./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/mips64el-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.luna88k b/distrib/sets/lists/base/md.luna88k index c5af9797569..48a98fdeb41 100644 --- a/distrib/sets/lists/base/md.luna88k +++ b/distrib/sets/lists/base/md.luna88k @@ -1097,8 +1097,6 @@ ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/m88k-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.macppc b/distrib/sets/lists/base/md.macppc index 278c1a20b3b..d80e8d69a69 100644 --- a/distrib/sets/lists/base/md.macppc +++ b/distrib/sets/lists/base/md.macppc @@ -1160,8 +1160,6 @@ ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.octeon b/distrib/sets/lists/base/md.octeon index d48d32276b5..bafce749629 100644 --- a/distrib/sets/lists/base/md.octeon +++ b/distrib/sets/lists/base/md.octeon @@ -1091,8 +1091,6 @@ ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.sgi b/distrib/sets/lists/base/md.sgi index f3fc6ed7ad9..02539f42ee3 100644 --- a/distrib/sets/lists/base/md.sgi +++ b/distrib/sets/lists/base/md.sgi @@ -1154,8 +1154,6 @@ ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/mips64-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.socppc b/distrib/sets/lists/base/md.socppc index 6e4c08cc8ce..87748d436d2 100644 --- a/distrib/sets/lists/base/md.socppc +++ b/distrib/sets/lists/base/md.socppc @@ -1153,8 +1153,6 @@ ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/powerpc-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.sparc b/distrib/sets/lists/base/md.sparc index 4c69ebd5de3..821e9cef6a6 100644 --- a/distrib/sets/lists/base/md.sparc +++ b/distrib/sets/lists/base/md.sparc @@ -639,8 +639,6 @@ ./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/sparc-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.sparc64 b/distrib/sets/lists/base/md.sparc64 index db2708507e2..abe1bdf8440 100644 --- a/distrib/sets/lists/base/md.sparc64 +++ b/distrib/sets/lists/base/md.sparc64 @@ -697,8 +697,6 @@ ./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/sparc64-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.vax b/distrib/sets/lists/base/md.vax index 595d3f7dd3b..fd886f06b94 100644 --- a/distrib/sets/lists/base/md.vax +++ b/distrib/sets/lists/base/md.vax @@ -597,8 +597,6 @@ ./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/vax-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/base/md.zaurus b/distrib/sets/lists/base/md.zaurus index 46c4b926ece..366f890a7d2 100644 --- a/distrib/sets/lists/base/md.zaurus +++ b/distrib/sets/lists/base/md.zaurus @@ -1178,8 +1178,6 @@ ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/ixgbe.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/ixgbe_type.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/mpiireg.ph -./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/musyccreg.ph -./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/musyccvar.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/neoreg.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/pccbbreg.ph ./usr/libdata/perl5/site_perl/arm-openbsd/dev/pci/pccbbvar.ph diff --git a/distrib/sets/lists/comp/mi b/distrib/sets/lists/comp/mi index c7fdfb7aac2..1e6bf2d5325 100644 --- a/distrib/sets/lists/comp/mi +++ b/distrib/sets/lists/comp/mi @@ -607,8 +607,6 @@ ./usr/include/dev/pci/ixgbe.h ./usr/include/dev/pci/ixgbe_type.h ./usr/include/dev/pci/mpiireg.h -./usr/include/dev/pci/musyccreg.h -./usr/include/dev/pci/musyccvar.h ./usr/include/dev/pci/neoreg.h ./usr/include/dev/pci/pccbbreg.h ./usr/include/dev/pci/pccbbvar.h diff --git a/distrib/sets/lists/man/mi b/distrib/sets/lists/man/mi index 87ea7d5ddc7..7058447053f 100644 --- a/distrib/sets/lists/man/mi +++ b/distrib/sets/lists/man/mi @@ -1304,7 +1304,6 @@ ./usr/share/man/man4/armv7/prcm.4 ./usr/share/man/man4/armv7/sitaracm.4 ./usr/share/man/man4/arp.4 -./usr/share/man/man4/art.4 ./usr/share/man/man4/asbtm.4 ./usr/share/man/man4/ast.4 ./usr/share/man/man4/atapiscsi.4 @@ -1649,7 +1648,6 @@ ./usr/share/man/man4/mtdphy.4 ./usr/share/man/man4/mtio.4 ./usr/share/man/man4/multicast.4 -./usr/share/man/man4/musycc.4 ./usr/share/man/man4/myx.4 ./usr/share/man/man4/ne.4 ./usr/share/man/man4/neo.4 diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile index 1be2d3f49f1..1c9bc39dd1e 100644 --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -1,4 +1,4 @@ -# $OpenBSD: Makefile,v 1.581 2014/08/20 11:23:41 mikeb Exp $ +# $OpenBSD: Makefile,v 1.582 2014/09/27 08:28:12 deraadt Exp $ MAN= aac.4 ac97.4 acphy.4 \ acpi.4 acpiac.4 acpiasus.4 acpibat.4 acpibtn.4 acpicpu.4 acpidock.4 \ @@ -9,7 +9,7 @@ MAN= aac.4 ac97.4 acphy.4 \ admtm.4 admtmp.4 admtt.4 adt.4 adtfsm.4 adv.4 age.4 alc.4 ale.4 agp.4 \ aha.4 ahb.4 ahc.4 ahci.4 ahd.4 aibs.4 aic.4 \ akbd.4 alipm.4 amas.4 amdiic.4 amdpm.4 ami.4 amphy.4 \ - ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 art.4 \ + ams.4 an.4 andl.4 aps.4 arc.4 arcofi.4 \ asbtm.4 ast.4 atapiscsi.4 atphy.4 ath.4 athn.4 atu.4 atw.4 \ auacer.4 audio.4 \ aue.4 auglx.4 auich.4 auixp.4 autri.4 auvia.4 axe.4 axen.4 az.4 azalia.4 \ @@ -75,7 +75,6 @@ MAN= aac.4 ac97.4 acphy.4 \ xe.4 xf86.4 xge.4 xhci.4 xl.4 xmphy.4 yds.4 ym.4 zero.4 zyd.4 MLINKS+=adv.4 advansys.4 adv.4 adw.4 -MLINKS+=art.4 musycc.4 MLINKS+=audio.4 mixer.4 MLINKS+=cardbus.4 cbb.4 MLINKS+=drm.4 inteldrm.4 drm.4 radeondrm.4 diff --git a/share/man/man4/art.4 b/share/man/man4/art.4 deleted file mode 100644 index ee70a2e3355..00000000000 --- a/share/man/man4/art.4 +++ /dev/null @@ -1,151 +0,0 @@ -.\" $OpenBSD: art.4,v 1.8 2013/06/02 20:23:33 tedu Exp $ -.\" -.\" Copyright (c) 2005 Internet Business Solutions AG, Zurich, Switzerland -.\" Written by: Claudio Jeker <jeker@accoom.net> -.\" -.\" Permission to use, copy, modify, and distribute this software for any -.\" purpose with or without fee is hereby granted, provided that the above -.\" copyright notice and this permission notice appear in all copies. -.\" -.\" THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -.\" WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -.\" MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -.\" ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -.\" WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -.\" ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -.\" OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -.\" -.\" -.Dd $Mdocdate: June 2 2013 $ -.Dt ART 4 -.Os -.Sh NAME -.Nm art , -.Nm musycc -.Nd Accoom Networks Artery T1/E1 network device -.Sh SYNOPSIS -.Cd "musycc* at pci?" -.Cd "art* at musycc?" -.Sh DESCRIPTION -The -.Nm -device driver supports the Accoom Networks Artery Series Network -cards. -This includes the following models: -.Pp -.Bl -item -offset indent -compact -.It -Accoom Artery Single T1/E1 PCI -.It -Accoom Artery Dual T1/E1 PCI -.El -.Pp -The following media types (as given to -.Xr ifconfig 8 ) -are supported: -.Pp -.Bl -tag -width "media E1-G.704-CRC4" -offset 3n -compact -.It Cm media No T1 -Set T1, B8ZS ESF operation. -.It Cm media No T1-AMI -Set T1, AMI SF operation. -.It Cm media No E1 -Set E1, HDB3, G.703 clearchannel operation. -.It Cm media No E1-G.704 -Set E1, HDB3, G.704 structured operation without CRC4 checksum. -.It Cm media No E1-G.704-CRC4 -Set E1, HDB3, G.704 structured operation with CRC4 checksum. -.El -.Pp -If no media type is set, the -.Nm -driver places the card into E1-G.704-CRC4 mode. -.Pp -The -.Nm -driver supports the following media options for all available media types: -.Pp -.Bl -tag -width "mediaopt ppp" -offset 3n -compact -.It Cm mediaopt No ppp -Use PPP line protocol. -.El -.Pp -If no media options are set, -the card defaults to cHDLC (Cisco High-Level Data Link Control) with 32-bit -HDLC CRC checksum. -.Pp -It is possible to change the timeslot range for the following media types: -.Pp -.Bl -item -offset indent -compact -.It -T1 -.It -T1-AMI -.It -E1-G.704 -.It -E1-G.704-CRC4 -.El -.Pp -If no timeslots are configured, the -.Nm -driver configures the card to use all possible channels. -Use -.Xr ifconfig 8 -to change the timeslot range. -For example: -.Pp -Enable all possible channels for this card: -.Dl # ifconfig art0 timeslot all -.Pp -Enable channels 1-31 for this card: -.Dl # ifconfig art0 timeslot 1-31 -.Pp -Enable channels 1-15, 16-31 for this card: -.Dl # ifconfig art0 timeslot 1-15,16-31 -.Pp -It is possible to change the clock mode of the interface with -.Xr ifconfig 8 . -To use the internal clock as clock source for the line, use -.Em master -mode. -For example: -.Pp -.Dl # ifconfig art0 media E1-G.704 mode master -.Pp -The default mode recovers the clock from the incoming line signal. -This can be explicitly set by using the -.Em autoselect -mode. -For example: -.Pp -.Dl # ifconfig art0 media E1-G.704 mode autoselect -.Sh DIAGNOSTICS -.Bl -diag -.It "art0: device timeout" -The device has stopped responding to the network -.It "art0: internal FIFO underflow" -The internal FIFO got empty while transmitting a packet. -This may indicate a PCI bus congestion. -.It "art0: internal FIFO overflow" -The internal FIFO overflowed while receiving a packet. -This may indicate a PCI bus congestion. -.It "art0: Failed to malloc memory" -There are not enough mbufs available for allocation. -.El -.Sh SEE ALSO -.Xr ifmedia 4 , -.Xr pci 4 , -.Xr sppp 4 , -.Xr hostname.if 5 , -.Xr ifconfig 8 -.Sh HISTORY -The -.Nm -device driver first appeared in -.Ox 3.8 . -.Sh AUTHORS -The -.Nm -device driver was written by Claudio Jeker and Andre Oppermann. -This manual page was written by Claudio Jeker. diff --git a/share/man/man4/pci.4 b/share/man/man4/pci.4 index 1d097b8b2bf..758cb046dc0 100644 --- a/share/man/man4/pci.4 +++ b/share/man/man4/pci.4 @@ -1,4 +1,4 @@ -.\" $OpenBSD: pci.4,v 1.331 2014/08/15 14:16:01 mikeb Exp $ +.\" $OpenBSD: pci.4,v 1.332 2014/09/27 08:28:12 deraadt Exp $ .\" $NetBSD: pci.4,v 1.29 2000/04/01 00:32:23 tsarna Exp $ .\" .\" Copyright (c) 2000 Theo de Raadt. All rights reserved. @@ -31,7 +31,7 @@ .\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF .\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. .\" -.Dd $Mdocdate: August 15 2014 $ +.Dd $Mdocdate: September 27 2014 $ .Dt PCI 4 .Os .Sh NAME @@ -176,8 +176,6 @@ Attansic L1 10/100/Gigabit Ethernet device Atheros AR813x/AR815x 10/100/Gigabit Ethernet device .It Xr ale 4 Atheros AR8121/AR8113/AR8114 10/100/Gigabit Ethernet device -.It Xr art 4 -Accoom Networks Artery T1/E1 network device .It Xr bce 4 Broadcom BCM4401 10/100 Ethernet device .It Xr bge 4 diff --git a/sys/arch/alpha/conf/GENERIC b/sys/arch/alpha/conf/GENERIC index da2ab11da65..2afab3f0875 100644 --- a/sys/arch/alpha/conf/GENERIC +++ b/sys/arch/alpha/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.247 2014/08/20 06:14:42 mikeb Exp $ +# $OpenBSD: GENERIC,v 1.248 2014/09/27 08:28:12 deraadt Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -232,8 +232,6 @@ mskc* at pci? # Marvell Yukon-2 msk* at mskc? # each port of above tl* at pci? # Compaq Thunderlan ethernet ste* at pci? # Sundance ST201 ethernet -musycc* at pci? # Conexant HDLC controller -art* at musycc? # Accoom Artery E1/T1 cards xge* at pci? # Neterion Xframe-I/II 10Gb ethernet sf* at pci? # Adaptec AIC-6915 ethernet wb* at pci? # Winbond W89C840F ethernet diff --git a/sys/arch/amd64/conf/GENERIC b/sys/arch/amd64/conf/GENERIC index af14ffd8ca0..3d378708b96 100644 --- a/sys/arch/amd64/conf/GENERIC +++ b/sys/arch/amd64/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.375 2014/08/20 06:14:42 mikeb Exp $ +# $OpenBSD: GENERIC,v 1.376 2014/09/27 08:28:12 deraadt Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -443,8 +443,6 @@ stge* at pci? # Sundance TC9021 GigE hme* at pci? # Sun Happy Meal vge* at pci? # VIA VT612x nfe* at pci? # NVIDIA nForce Ethernet -musycc* at pci? # Conexant HDLC controller -art* at musycc? # Accoom Artery E1/T1 cards xge* at pci? # Neterion Xframe-I/II 10Gb ethernet thtc* at pci? # Tehuti Networks 10Gb ethernet tht* at thtc? diff --git a/sys/arch/i386/conf/GENERIC b/sys/arch/i386/conf/GENERIC index 43c191480be..345e32417ce 100644 --- a/sys/arch/i386/conf/GENERIC +++ b/sys/arch/i386/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.785 2014/09/08 01:47:05 guenther Exp $ +# $OpenBSD: GENERIC,v 1.786 2014/09/27 08:28:12 deraadt Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -578,8 +578,6 @@ hme* at pci? # Sun Happy Meal bce* at pci? # Broadcom BCM4401 vge* at pci? # VIA VT612x nfe* at pci? # NVIDIA nForce Ethernet -musycc* at pci? # Conexant HDLC controller -art* at musycc? # Accoom Artery E1/T1 cards xge* at pci? # Neterion Xframe-I/II 10Gb ethernet thtc* at pci? # Tehuti Networks 10Gb ethernet tht* at thtc? diff --git a/sys/arch/macppc/conf/GENERIC b/sys/arch/macppc/conf/GENERIC index d937733ec69..8662e58e7c3 100644 --- a/sys/arch/macppc/conf/GENERIC +++ b/sys/arch/macppc/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.240 2014/09/14 18:59:18 brad Exp $g +# $OpenBSD: GENERIC,v 1.241 2014/09/27 08:28:12 deraadt Exp $g # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -96,8 +96,6 @@ ral* at pci? # Ralink RT2500/RT2501/RT2600 rtw* at pci? # Realtek 8180 vr* at pci? # VIA Rhine ethernet pcn* at pci? # AMD PCnet-PCI Ethernet -musycc* at pci? # Conexant HDLC controller -art* at musycc? # Accoom Artery E1/T1 cards xge* at pci? # Neterion Xframe-I/II 10Gb ethernet mbg* at pci? # Meinberg Funkuhren radio clocks malo* at pci? # Marvell Libertas diff --git a/sys/arch/sparc64/conf/GENERIC b/sys/arch/sparc64/conf/GENERIC index 439584a1a26..7210bd8b3ba 100644 --- a/sys/arch/sparc64/conf/GENERIC +++ b/sys/arch/sparc64/conf/GENERIC @@ -1,4 +1,4 @@ -# $OpenBSD: GENERIC,v 1.290 2014/09/14 19:02:43 brad Exp $ +# $OpenBSD: GENERIC,v 1.291 2014/09/27 08:28:12 deraadt Exp $ # # For further information on compiling OpenBSD kernels, see the config(8) # man page. @@ -91,8 +91,6 @@ rl* at pci? # RealTek 81[23]9 ethernet vr* at pci? # VIA Rhine ethernet re* at pci? # RealTek 8169/8169S/8110S re* at cardbus? # RealTek 8169/8169S/8110S -musycc* at pci? # Conexant HDLC controller -art* at musycc? # Accoom Artery E1/T1 cards thtc* at pci? # Tehuti Networks 10Gb ethernet tht* at thtc? jme* at pci? # JMicron JMC250/JMC260 Ethernet diff --git a/sys/dev/pci/bt8370.c b/sys/dev/pci/bt8370.c deleted file mode 100644 index b8f58acf18e..00000000000 --- a/sys/dev/pci/bt8370.c +++ /dev/null @@ -1,998 +0,0 @@ -/* $OpenBSD: bt8370.c,v 1.7 2006/01/31 16:51:13 claudio Exp $ */ - -/* - * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Andre Oppermann <oppermann@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include <sys/param.h> -#include <sys/types.h> - -#include <sys/device.h> -#include <sys/systm.h> -#include <sys/socket.h> -#include <sys/sockio.h> -#include <sys/syslog.h> - -#include <net/if.h> -#include <net/if_media.h> -#include <net/if_types.h> -#include <net/if_sppp.h> - -#include <netinet/in.h> -#include <netinet/if_ether.h> - -#include <machine/cpu.h> -#include <machine/bus.h> - -#include "musyccreg.h" -#include "musyccvar.h" -#include "if_art.h" -#include "bt8370reg.h" - -#define FRAMER_LIU_E1_120 1 -#define FRAMER_LIU_T1_133 2 - -void bt8370_set_sbi_clock_mode(struct art_softc *, enum art_sbi_type, - u_int, int); -void bt8370_set_bus_mode(struct art_softc *, enum art_sbi_mode, int); -void bt8370_set_line_buildout(struct art_softc *, int); -void bt8370_set_loopback_mode(struct art_softc *, enum art_loopback); -void bt8370_set_bop_mode(struct art_softc *ac, int); -void bt8370_set_dl_1_mode(struct art_softc *, int); -void bt8370_set_dl_2_mode(struct art_softc *, int); -void bt8370_intr_enable(struct art_softc *ac, int); - -#ifndef ACCOOM_DEBUG -#define bt8370_print_status(x) -#define bt8370_print_counters(x) -#define bt8370_dump_registers(x) -#else -void bt8370_print_status(struct art_softc *); -void bt8370_print_counters(struct art_softc *); -void bt8370_dump_registers(struct art_softc *); -#endif - -int -bt8370_reset(struct art_softc *ac) -{ - u_int8_t cr0; - - ebus_write(&ac->art_ebus, Bt8370_CR0, 0x00); - DELAY(10); /* 10 microseconds */ - ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_RESET); - DELAY(20); /* 20 microseconds */ - ebus_write(&ac->art_ebus, Bt8370_CR0, 0x00); - cr0 = ebus_read(&ac->art_ebus, Bt8370_CR0); - if (cr0 != 0x0) { - log(LOG_ERR, "%s: reset not successful\n", - ac->art_dev.dv_xname); - return (-1); - } - return (0); -} - -int -bt8370_set_frame_mode(struct art_softc *ac, enum art_sbi_type type, u_int mode, - u_int clockmode) -{ - int channels; - - /* Get into a clean state */ - bt8370_reset(ac); - - /* Disable all interrupts to be sure */ - bt8370_intr_enable(ac, 0); - - switch (mode) { - case IFM_TDM_E1: /* 32 payload channels, bit transparent */ - channels = 32; - - /* Global Config */ - ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS); - - /* Primary Config */ - bt8370_set_loopback_mode(ac, ART_NOLOOP); - ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00); - - /* Timing and Clock Config */ - bt8370_set_sbi_clock_mode(ac, type, clockmode, channels); - - /* Receiver RLIU, RCVR */ - bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_HDB3 | - RCR0_RABORT | RCR0_LFA_FAS | RCR0_RZCS_NBPV); - ebus_write(&ac->art_ebus, Bt8370_RALM, 0x00); - ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT); - - /* Transmitter TLIU, XMTR */ - ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_FAS); - ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT | - TCR1_HDB3); - ebus_write(&ac->art_ebus, Bt8370_TFRM, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TALM, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF); - - /* Bit Oriented Protocol Transceiver BOP disabled */ - bt8370_set_bop_mode(ac, 0); - - /* Data Link #1 disabled */ - bt8370_set_dl_1_mode(ac, 0); - - /* Data Link #2 disabled */ - bt8370_set_dl_2_mode(ac, 0); - - ACCOOM_PRINTF(1, ("%s: set to E1 G.703 unframed, HDB3\n", - ac->art_dev.dv_xname)); - break; - case IFM_TDM_E1_G704: /* 31 payload channels, byte aligned */ - channels = 32; - - /* Global Config */ - ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS); - - /* Primary Config */ - bt8370_set_loopback_mode(ac, ART_NOLOOP); - ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00); - - /* Timing and Clock Config */ - bt8370_set_sbi_clock_mode(ac, type, clockmode, channels); - - /* Receiver RLIU, RCVR */ - bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE | - RCR0_HDB3 | RCR0_LFA_FAS | RCR0_RZCS_NBPV); - ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS); - ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT); - - /* Transmitter TLIU, XMTR */ - ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_FAS); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT | - TCR1_3FAS | TCR1_HDB3); - ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL | - TFRM_FBIT); - ebus_write(&ac->art_ebus, Bt8370_TMAN, TMAN_MALL); - ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL); - ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF); - - /* Bit Oriented Protocol Transceiver BOP disabled */ - bt8370_set_bop_mode(ac, 0); - - /* Data Link #1 disabled */ - bt8370_set_dl_1_mode(ac, 0); - - /* Data Link #2 disabled */ - bt8370_set_dl_2_mode(ac, 0); - - ACCOOM_PRINTF(1, ("%s: set to E1 G.704, HDB3\n", - ac->art_dev.dv_xname)); - break; - case IFM_TDM_E1_G704_CRC4: /* 31 payload channels, byte aligned */ - channels = 32; - - /* - * Over normal G.704 the following registers need changes: - * CR0 = +CRC - * TFRM = +INS_CRC - */ - - /* Global Config */ - ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_E1_FAS_CRC); - - /* Primary Config */ - bt8370_set_loopback_mode(ac, ART_NOLOOP); - ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00); - - /* Timing and Clock Config */ - bt8370_set_sbi_clock_mode(ac, type, clockmode, channels); - - /* Receiver RLIU, RCVR */ - bt8370_set_line_buildout(ac, FRAMER_LIU_E1_120); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE | - RCR0_HDB3 | RCR0_LFA_FASCRC | RCR0_RZCS_NBPV); - ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS); - ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT); - - /* Transmitter TLIU, XMTR */ - ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_MFAS); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT | - TCR1_3FAS | TCR1_HDB3); - ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL | - TFRM_MF | TFRM_FE | TFRM_CRC | TFRM_FBIT); - ebus_write(&ac->art_ebus, Bt8370_TMAN, TMAN_MALL); - ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL | TALM_AAIS); - ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF); - - /* Bit Oriented Protocol Transceiver BOP disabled */ - bt8370_set_bop_mode(ac, 0); - - /* Data Link #1 disabled */ - bt8370_set_dl_1_mode(ac, 0); - - /* Data Link #2 disabled */ - bt8370_set_dl_2_mode(ac, 0); - - ACCOOM_PRINTF(1, ("%s: set to E1 G.704 CRC4, HDB3\n", - ac->art_dev.dv_xname)); - break; - case IFM_TDM_T1_AMI: /* 24 payload channels, byte aligned */ - channels = 25; /* zero is ignored for T1 */ - - /* Global Config */ - ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_T1_SF); - - /* Primary Config */ - bt8370_set_loopback_mode(ac, ART_NOLOOP); - ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00); - - /* Timing and Clock Config */ - bt8370_set_sbi_clock_mode(ac, type, clockmode, channels); - - /* Receiver RLIU, RCVR */ - bt8370_set_line_buildout(ac, FRAMER_LIU_T1_133); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE | - RCR0_AMI | RCR0_LFA_26F | RCR0_RZCS_NBPV); - ebus_write(&ac->art_ebus, Bt8370_RALM, RALM_FSNFAS); - ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT); - - /* Transmitter TLIU, XMTR */ - ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_SF); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT | - TCR1_26F | TCR1_AMI); - ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_YEL | - TFRM_MF | TFRM_FBIT); - ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL); - ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF); - - /* Bit Oriented Protocol Transceiver BOP disabled */ - bt8370_set_bop_mode(ac, 0); - - /* Data Link #1 disabled */ - bt8370_set_dl_1_mode(ac, 0); - - /* Data Link #2 disabled */ - bt8370_set_dl_2_mode(ac, 0); - - ACCOOM_PRINTF(1, ("%s: set to T1 SF, AMI\n", - ac->art_dev.dv_xname)); - break; - case IFM_TDM_T1: /* 24 payload channels, byte aligned */ - channels = 25; /* zero is ignored for T1 */ - - /* Global Config */ - ebus_write(&ac->art_ebus, Bt8370_CR0, CR0_T1_ESF); - - /* Primary Config */ - bt8370_set_loopback_mode(ac, ART_NOLOOP); - ebus_write(&ac->art_ebus, Bt8370_DL3_TS, 0x00); - - /* Timing and Clock Config */ - bt8370_set_sbi_clock_mode(ac, type, clockmode, channels); - - /* Receiver RLIU, RCVR */ - bt8370_set_line_buildout(ac, FRAMER_LIU_T1_133); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_RCR0, RCR0_RFORCE | - RCR0_B8ZS | RCR0_LFA_26F | RCR0_RZCS_NBPV); - ebus_write(&ac->art_ebus, Bt8370_RLB, 0x09); - ebus_write(&ac->art_ebus, Bt8370_LBA, 0x08); - ebus_write(&ac->art_ebus, Bt8370_LBD, 0x24); - ebus_write(&ac->art_ebus, Bt8370_RALM, 0x00); - ebus_write(&ac->art_ebus, Bt8370_LATCH, LATCH_STOPCNT); - - /* Transmitter TLIU, XMTR */ - ebus_write(&ac->art_ebus, Bt8370_TCR0, TCR0_ESFCRC); - /* This one is critical */ - ebus_write(&ac->art_ebus, Bt8370_TCR1, TCR1_TABORT | - TCR1_26F | TCR1_B8ZS); - ebus_write(&ac->art_ebus, Bt8370_TFRM, TFRM_CRC | - TFRM_FBIT); - ebus_write(&ac->art_ebus, Bt8370_TMAN, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TALM, TALM_AYEL); - ebus_write(&ac->art_ebus, Bt8370_TPATT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TLB, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSA4, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA5, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA6, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA7, 0xFF); - ebus_write(&ac->art_ebus, Bt8370_TSA8, 0xFF); - - /* Bit Oriented Protocol Transceiver BOP setup */ - bt8370_set_bop_mode(ac, ART_BOP_ESF); - - /* Data Link #1 set to BOP mode for FDL */ - bt8370_set_dl_1_mode(ac, ART_DL1_BOP); - - /* Data Link #2 disabled */ - bt8370_set_dl_2_mode(ac, 0); - - ACCOOM_PRINTF(1, ("%s: set to T1 ESF CRC6, B8ZS\n", - ac->art_dev.dv_xname)); - break; - /* - * case FAS_BSLIP: - * case FAS_CRC_BSLIP: - * case FAS_CAS: - * case FAS_CAS_BSLIP: - * case FAS_CRC_CAS: - * case FAS_CRC_CAS_BSLIP: - * case FT: - * case ESF_NOCRC: - * case SF_JYEL: - * case SF_T1DM: - * case SLC_FSLOF: - * case SLC: - * case ESF_xx (MimicCRC, ForceCRC?) - * - * are not yet implemented. - * If you need one of them please contact us. - */ - default: - return (-1); - } - return (0); -} - -void -bt8370_set_sbi_clock_mode(struct art_softc *ac, enum art_sbi_type mode, - u_int linemode, int channels) -{ - u_int8_t cmux, jatcr; - - /* - * mode is either master or slave. - * linemode is either T1 (1544) or E1 (2048) external or internal. - */ - switch (mode) { - case ART_SBI_MASTER: - ACCOOM_PRINTF(1, ("%s: set to MASTER\n", - ac->art_dev.dv_xname)); - /* - * ONESEC pulse output, - * RDL/TDL/INDY ignored, - * RFSYNC Receive Frame Sync output, - * RMSYNC Reveice MultiFrame Sync output, - * TFYNC Transmit Frame Sync output, - * TMSYNC Transmit MultiFrame Sync output. - */ - ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_ONESEC_IO | - PIO_TDL_IO | PIO_RFSYNC_IO | PIO_RMSYNC_IO | - PIO_TFSYNC_IO | PIO_TMSYNC_IO); - /* - * TDL/RDL/INDY/TCKO three-stated. - * CLADO enabled, drives SBI bus RCLK, TCLK and - * is connected to own TSBCKI and TSBCKI on slave. - * RCKO enabled, is connected to TCKI on slave. - */ - ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE | - POE_RDL_OE | POE_INDY_OE | POE_TCKO_OE); - /* - * We are the SBI bus master and take clock from our own - * CLADO. The TCKI source depends on line or internal - * clocking. - */ - cmux = CMUX_RSBCKI_CLADO | CMUX_TSBCKI_CLADO | - CMUX_CLADI_CLADI; - break; - case ART_SBI_SLAVE: - ACCOOM_PRINTF(1, ("%s: set to SLAVE\n", - ac->art_dev.dv_xname)); - /* - * ONESEC pulse input, - * RDL/TDL/INDY ignored, - * RFSYNC Receive Frame Sync input, - * RMSYNC Reveice MultiFrame Sync input, - * TFYNC Transmit Frame Sync input, - * TMSYNC Transmit MultiFrame Sync input. - */ - ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_TDL_IO); - /* - * TDL/RDL/INDY/TCKO three-stated. - * CLADO enabled, is connected to own ACKI and - * RSBCKI, ACKI on master. - * RCKO enabled, is connected to TCKI on master. - */ - ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE | - POE_RDL_OE | POE_INDY_OE | POE_TCKO_OE); - /* - * We are the SBI bus slave and take clock from TSBCKI. - * The TCKI source depends on line or internal clocking. - */ - cmux = CMUX_RSBCKI_TSBCKI | CMUX_TSBCKI_TSBCKI | - CMUX_CLADI_CLADI; - break; - case ART_SBI_SINGLE: - ACCOOM_PRINTF(1, ("%s: set to SINGLE\n", - ac->art_dev.dv_xname)); - /* - * ONESEC pulse output, - * RDL/TDL/INDY ignored, - * RFSYNC Receive Frame Sync output, - * RMSYNC Reveice MultiFrame Sync output, - * TFSYNC Transmit Frame Sync output, - * TMSYNC Transmit MultiFrame Sync output. - */ - ebus_write(&ac->art_ebus, Bt8370_PIO, PIO_ONESEC_IO | - PIO_TDL_IO | PIO_RFSYNC_IO | PIO_RMSYNC_IO | - PIO_TFSYNC_IO | PIO_TMSYNC_IO); - /* - * TDL/RDL/INDY/TCKO three-stated, CLADO/RCKO enabled. - */ - ebus_write(&ac->art_ebus, Bt8370_POE, POE_TDL_OE | - POE_RDL_OE | POE_INDY_OE | POE_RCKO_OE); - /* - * We are the SBI bus master and take clock from our own - * CLADO. The TCKI source is always CLADO (jitter attenuated - * if receive clock). - */ - cmux = CMUX_RSBCKI_CLADO | CMUX_TSBCKI_CLADO | - CMUX_CLADI_RCKO; - break; - } - - /* Transmit clock from where? */ - switch (linemode) { - case IFM_TDM_MASTER: - ACCOOM_PRINTF(1, ("%s: clock MASTER\n", - ac->art_dev.dv_xname)); - if (mode == ART_SBI_MASTER) - cmux |= CMUX_TCKI_RSBCKI; - else - cmux |= CMUX_TCKI_CLADO; - jatcr = JAT_CR_JFREE; - break; - /* case ART_CLOCK_EXTREF: */ - default: - ACCOOM_PRINTF(1, ("%s: clock LINE\n", - ac->art_dev.dv_xname)); - cmux |= CMUX_TCKI_RCKO; - jatcr = JAT_CR_JEN | JAT_CR_JDIR_RX | JAT_CR_JSIZE32; - break; - } - - ebus_write(&ac->art_ebus, Bt8370_CMUX, cmux); - ebus_write(&ac->art_ebus, Bt8370_JAT_CR, jatcr); - - /* Set up the SBI (System Bus Interface) and clock source. */ - switch (mode) { - case ART_SBI_MASTER: - ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_4096 | - CSEL_OSEL_4096); - bt8370_set_bus_mode(ac, SBI_MODE_4096_A, channels); - /* no need to set musycc port mode */ - break; - case ART_SBI_SLAVE: - /* - * On the slave the CLADO depends on the line type - * of the master. - */ - bt8370_set_bus_mode(ac, SBI_MODE_4096_B, channels); - /* no need to set musycc port mode */ - break; - case ART_SBI_SINGLE: - if (channels == 25) { - ACCOOM_PRINTF(1, ("%s: SINGLE T1\n", - ac->art_dev.dv_xname)); - ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_1544 | - CSEL_OSEL_1544); - bt8370_set_bus_mode(ac, SBI_MODE_1544, channels); - musycc_set_port(ac->art_channel->cc_group, - MUSYCC_PORT_MODE_T1); - } else { - ACCOOM_PRINTF(1, ("%s: SINGLE E1\n", - ac->art_dev.dv_xname)); - ebus_write(&ac->art_ebus, Bt8370_CSEL, CSEL_VSEL_2048 | - CSEL_OSEL_2048); - bt8370_set_bus_mode(ac, SBI_MODE_2048, channels); - musycc_set_port(ac->art_channel->cc_group, - MUSYCC_PORT_MODE_E1); - } - break; - } - ebus_write(&ac->art_ebus, Bt8370_CLAD_CR, CLAD_CR_LFGAIN); -} - -void -bt8370_set_bus_mode(struct art_softc *ac, enum art_sbi_mode mode, int nchannels) -{ - bus_size_t channel; - - /* - * Be aware that on the CN847x 'TSYNC_EDGE' has to be set to - * 'raising edge' in the port config for this to work correctly. - * All others (including RSYNC) are on 'falling edge'. - */ - ebus_write(&ac->art_ebus, Bt8370_RSB_CR, RSB_CR_BUS_RSB | - RSB_CR_SIG_OFF | RSB_CR_RPCM_NEG | RSB_CR_RSYN_NEG | - RSB_CR_RSB_CTR | TSB_CR_TSB_NORMAL); - ebus_write(&ac->art_ebus, Bt8370_RSYNC_BIT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_RSYNC_TS, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSB_CR, TSB_CR_BUS_TSB | - TSB_CR_TPCM_NEG | TSB_CR_TSYN_NEG | TSB_CR_TSB_CTR | - TSB_CR_TSB_NORMAL); - ebus_write(&ac->art_ebus, Bt8370_TSYNC_BIT, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSYNC_TS, 0x00); - ebus_write(&ac->art_ebus, Bt8370_RSIG_CR, 0x00); - ebus_write(&ac->art_ebus, Bt8370_RSYNC_FRM, 0x00); - - /* Mode dependent */ - switch (mode) { - case SBI_MODE_1536: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_1536); - break; - case SBI_MODE_1544: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_1544); - break; - case SBI_MODE_2048: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_2048); - break; - case SBI_MODE_4096_A: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_4096_A); - break; - case SBI_MODE_4096_B: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_4096_B); - break; - case SBI_MODE_8192_A: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_8192_A); - break; - case SBI_MODE_8192_B: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_8192_B); - break; - case SBI_MODE_8192_C: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_8192_C); - break; - case SBI_MODE_8192_D: - ebus_write(&ac->art_ebus, Bt8370_SBI_CR, SBI_CR_SBI_OE | - SBI_CR_8192_D); - break; - } - - /* Initialize and reset all channels */ - for (channel = 0; channel < 32; channel++) { - ebus_write(&ac->art_ebus, Bt8370_SBCn + channel, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TPCn + channel, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSIGn + channel, 0x00); - ebus_write(&ac->art_ebus, Bt8370_TSLIP_LOn + channel, 0x7e); - ebus_write(&ac->art_ebus, Bt8370_RSLIP_LOn + channel, 0x7e); - ebus_write(&ac->art_ebus, Bt8370_RPCn + channel, 0x00); - } - - /* Configure used channels */ - for (channel = Bt8370_SBCn; channel < Bt8370_SBCn + - nchannels; channel++) { - ebus_write(&ac->art_ebus, channel, SBCn_RINDO | - SBCn_TINDO | SBCn_ASSIGN); - /* In T1 mode timeslot 0 must not be used. */ - if (nchannels == 25 && channel == Bt8370_SBCn) - ebus_write(&ac->art_ebus, channel, 0x00); - } - for (channel = Bt8370_TPCn; channel < Bt8370_TPCn + - nchannels; channel++) { - ebus_write(&ac->art_ebus, channel, TPCn_CLEAR); - } - for (channel = Bt8370_RPCn; channel < Bt8370_RPCn + - nchannels; channel++) { - ebus_write(&ac->art_ebus, channel, RPCn_CLEAR); - } -} - -void -bt8370_set_line_buildout(struct art_softc *ac, int mode) -{ - /* - * LIU Stuff: Send and Reveive side - * T1: 0-133, 133-266, 266-399, 399-533, 533-655, - * Long-Haul FCC Part 68. - * E1: ITU-T G.703 120 Ohm Twisted Pair. - */ - - ebus_write(&ac->art_ebus, Bt8370_RLIU_CR, RLIU_CR_FRZ_SHORT | - RLIU_CR_AGC2048 | RLIU_CR_LONG_EYE); - - switch (mode) { - case FRAMER_LIU_T1_133: - /* Short haul */ - ebus_write(&ac->art_ebus, Bt8370_VGA_MAX, 0x1F); - /* Force EQ off */ - ebus_write(&ac->art_ebus, Bt8370_PRE_EQ, 0xA6); - - ebus_write(&ac->art_ebus, Bt8370_TLIU_CR, TLIU_CR_100); - break; -#if 0 - case FRAMER_LIU_T1_266: - case FRAMER_LIU_T1_399: - case FRAMER_LIU_T1_533: - case FRAMER_LIU_T1_655: - case FRAMER_LIU_T1_LH68: -#endif - case FRAMER_LIU_E1_120: - /* Short haul */ - ebus_write(&ac->art_ebus, Bt8370_VGA_MAX, 0x1F); - /* Force EQ off */ - ebus_write(&ac->art_ebus, Bt8370_PRE_EQ, 0xA6); - - ebus_write(&ac->art_ebus, Bt8370_TLIU_CR, TLIU_CR_120); - break; - } - - /* - * Run this last. The RLIU reset causes the values written above - * to be activated. - */ - ebus_write(&ac->art_ebus, Bt8370_LIU_CR, LIU_CR_MAGIC | - LIU_CR_SQUELCH | LIU_CR_RST_LIU); -} - -void -bt8370_set_loopback_mode(struct art_softc *ac, enum art_loopback mode) -{ - switch (mode) { - case ART_RLOOP_PAYLOAD: /* Remote digital payload loopback */ - ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_PLOOP); - break; - case ART_RLOOP_LINE: /* Remote analog line signal loopback */ - ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_LLOOP); - break; - case ART_LLOOP_PAYLOAD: /* Local digital payload loopback */ - ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_FLOOP); - break; - case ART_LLOOP_LINE: /* Local analog line signal loopback */ - ebus_write(&ac->art_ebus, Bt8370_LOOP, LOOP_ALOOP); - break; - case ART_NOLOOP: /* Disable all loopbacks */ - ebus_write(&ac->art_ebus, Bt8370_LOOP, 0x00); - break; - } -} - -void -bt8370_set_bop_mode(struct art_softc *ac, int mode) -{ - /* disabled or ESF mode */ - switch (mode) { - case ART_BOP_ESF: - ebus_write(&ac->art_ebus, Bt8370_BOP, 0x9A); - break; - default: - ebus_write(&ac->art_ebus, Bt8370_BOP, 0x00); - break; - } -} - -void -bt8370_set_dl_1_mode(struct art_softc *ac, int mode) -{ - /* - * We don't support the builtin HDLC controllers, - * however some DL1 registers are used for the BOP - * in ESF mode. - */ - switch (mode) { - case ART_DL1_BOP: - ebus_write(&ac->art_ebus, Bt8370_DL1_TS, 0x40); - ebus_write(&ac->art_ebus, Bt8370_DL1_CTL, 0x03); - ebus_write(&ac->art_ebus, Bt8370_RDL1_FFC, 0x0A); - ebus_write(&ac->art_ebus, Bt8370_PRM1, 0x80); - ebus_write(&ac->art_ebus, Bt8370_TDL1_FEC, 0x0A); - break; - default: - ebus_write(&ac->art_ebus, Bt8370_RDL1_FFC, 0x0A); - ebus_write(&ac->art_ebus, Bt8370_TDL1, 0x00); - break; - } -} - -void -bt8370_set_dl_2_mode(struct art_softc *ac, int mode) -{ - /* We don't support the builtin HDLC controllers. */ - ebus_write(&ac->art_ebus, Bt8370_RDL2_FFC, 0x0A); - ebus_write(&ac->art_ebus, Bt8370_TDL2, 0x00); -} - -void -bt8370_intr_enable(struct art_softc *ac, int intr) -{ - switch (intr) { - default: - /* Disable all interrupts */ - ebus_write(&ac->art_ebus, Bt8370_IER7, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER6, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER5, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER4, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER3, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER2, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER1, 0x00); - ebus_write(&ac->art_ebus, Bt8370_IER0, 0x00); - break; - } - return; -} - -void -bt8370_intr(struct art_softc *ac) -{ - u_int8_t irr, alrm; - - /* IRR tells us which interrupt class fired. */ - irr = ebus_read(&ac->art_ebus, Bt8370_IRR); - /* If it wasn't us don't waste time. */ - if (irr == 0x00) - return; - - /* Reding the interrupt service registers clears them. */ - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR7); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR6); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR5); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR4); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR3); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR2); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR1); - alrm = ebus_read(&ac->art_ebus, Bt8370_ISR0); - - /* IRR should be zero now or something went wrong. */ - irr = ebus_read(&ac->art_ebus, Bt8370_IRR); - if (irr != 0x00) - ACCOOM_PRINTF(0, ("%s: Interrupts did not clear properly\n", - ac->art_dev.dv_xname)); - return; -} - -int -bt8370_link_status(struct art_softc *ac) -{ - u_int8_t rstat, alm1, alm2, alm3, alm1mask; - int status = 1; - - /* - * 1 everything fine - * 0 framing problems but link detected - * -1 no link detected - */ - - alm1mask = ALM1_RYEL | ALM1_RAIS | ALM1_RALOS | ALM1_RLOF; - /* - * XXX don't check RYEL in T1 mode it toggles more or less - * regular. - */ - if (IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1) - alm1mask &= ~ALM1_RYEL; - - rstat = ebus_read(&ac->art_ebus, Bt8370_RSTAT); - alm1 = ebus_read(&ac->art_ebus, Bt8370_ALM1); - alm2 = ebus_read(&ac->art_ebus, Bt8370_ALM2); - alm3 = ebus_read(&ac->art_ebus, Bt8370_ALM3); - - if ((rstat & (RSTAT_EXZ | RSTAT_BPV)) || - (alm1 & alm1mask) || (alm3 & (ALM3_SEF))) - status = 0; - - if ((alm1 & (ALM1_RLOS)) || - (alm2 & (ALM2_TSHORT))) - status = -1; - - return (status); -} - -#ifdef ACCOOM_DEBUG -void -bt8370_print_status(struct art_softc *ac) -{ - u_int8_t fstat, rstat, vga, alm1, alm2, alm3, sstat, loop; - - /* FSTAT Register. */ - fstat = ebus_read(&ac->art_ebus, Bt8370_FSTAT); - printf("%s: Current FSTAT:\n", ac->art_dev.dv_xname); - if (fstat & FSTAT_ACTIVE) { - printf("\tOffline Framer active "); - if (fstat & FSTAT_RXTXN) - printf("in Receive direction\n"); - else - printf("in Transmit direction\n"); - if (fstat & FSTAT_INVALID) - printf("\tNo Candidate found\n"); - if (fstat & FSTAT_FOUND) - printf("\tFrame Alignment found\n"); - if (fstat & FSTAT_TIMEOUT) - printf("\tFramer Search timeout\n"); - } else - printf("\tOffline inactive\n"); - - /* RSTAT and VGA Register. */ - rstat = ebus_read(&ac->art_ebus, Bt8370_RSTAT); - printf("%s: Current RSTAT:\n", ac->art_dev.dv_xname); - if (rstat & RSTAT_CPDERR) - printf("\tCLAD phase detector lost lock to CLADI reference\n"); - if (rstat & RSTAT_ZCSUB) - printf("\tHDB3/B8ZS pattern detected\n"); - if (rstat & RSTAT_EXZ) - printf("\tExcessive zeros detected\n"); - if (rstat & RSTAT_BPV) - printf("\tBipolar violations\n"); - if (rstat & RSTAT_EYEOPEN) - printf("\tReceived signal valid and RPLL locked\n"); - else - printf("\tReceived signal invalid\n"); - if (rstat & RSTAT_PRE_EQ) - printf("\tPre-Equalizer is ON\n"); - else - printf("\tPre-Equalizer is OFF\n"); - /* Need to write something to cause internal update. */ - ebus_write(&ac->art_ebus, Bt8370_VGA, 0x00); - vga = ebus_read(&ac->art_ebus, Bt8370_VGA); - printf("\t%i dB Gain\n", vga); - - /* Alarm 1 Status. */ - alm1 = ebus_read(&ac->art_ebus, Bt8370_ALM1); - printf("%s: Current ALM1:\n", ac->art_dev.dv_xname); - if (alm1 & ALM1_RMYEL) - printf("\tMultiframe Yellow Alarm [MYEL]\n"); - if (alm1 & ALM1_RYEL) - printf("\tYellow Alarm [YEL]\n"); - if (alm1 & ALM1_RAIS) - printf("\tRemote Alarm Indication [RAIS]\n"); - if (alm1 & ALM1_RALOS) - printf("\tAnalog Loss of Signal or RCKI Loss of Clock [RALOS]\n"); - if (alm1 & ALM1_RLOS) - printf("\tLoss of Signal [RLOS]\n"); - if (alm1 & ALM1_RLOF) - printf("\tLoss of Frame Alignment [RLOF]\n"); - if (alm1 & ALM1_SIGFRZ) - printf("\tSignalling Freeze\n"); - - /* Alarm 2 Status. */ - alm2 = ebus_read(&ac->art_ebus, Bt8370_ALM2); - printf("%s: Current ALM2:\n", ac->art_dev.dv_xname); - if (alm2 & ALM2_LOOPDN) - printf("\tLOOPDN code detected\n"); - if (alm2 & ALM2_LOOPUP) - printf("\tLOOPUP code detected\n"); - if (alm2 & ALM2_TSHORT) - printf("\tTransmitter short circuit\n"); - if (alm2 & ALM2_TLOC) - printf("\tTransmit loss of clock (relative to ACKI)\n"); - if (alm2 & ALM2_TLOF) - printf("\tTransmit loss of frame alignment (ignored)\n"); - - /* Alarm 3 Status. */ - alm3 = ebus_read(&ac->art_ebus, Bt8370_ALM3); - printf("%s: Current ALM3:\n", ac->art_dev.dv_xname); - if (alm3 & ALM3_RMAIS) - printf("\tRMAIS TS16 Alarm Indication Signal\n"); - if (alm3 & ALM3_SEF) - printf("\tSeverely Errored Frame encountered\n"); - if (alm3 & ALM3_SRED) - printf("\tLoss of CAS Alignment\n"); - if (alm3 & ALM3_MRED) - printf("\tLoss of MFAS Alignment\n"); - if (alm3 & ALM3_FRED) - printf("\tLoss of T1/FAS Alignment\n"); - /* LOF omitted */ - - /* Slip Buffer Status. */ - sstat = ebus_read(&ac->art_ebus, Bt8370_SSTAT); - printf("%s: Current SSTAT:\n", ac->art_dev.dv_xname); - if (sstat & SSTAT_TFSLIP) { - if (sstat & SSTAT_TUSLIP) - printf("\tControlled Transmit Slip, "); - else - printf("\tUncontrolled Transmit Slip, "); - if (sstat & SSTAT_TSDIR) - printf("repeated one frame\n"); - else - printf("deleted one frame\n"); - } else if (sstat & SSTAT_RFSLIP) { - if (sstat & SSTAT_RUSLIP) - printf("\tControlled Receive Slip, "); - else - printf("\tUncontrolled Receive Slip, "); - if (sstat & SSTAT_RSDIR) - printf("repeated one frame\n"); - else - printf("deleted one frame\n"); - } - - /* Loopback Status. */ - loop = ebus_read(&ac->art_ebus, Bt8370_LOOP); - printf("%s: Current LOOP:\n", ac->art_dev.dv_xname); - if (loop & LOOP_PLOOP) - printf("\tRemote Payload Loopback\n"); - if (loop & LOOP_LLOOP) - printf("\tRemote Line Loopback\n"); - if (loop & LOOP_FLOOP) - printf("\tLocal Payload Loopback\n"); - if (loop & LOOP_ALOOP) - printf("\tLocal Line Loopback\n"); - if (loop & 0x00) - printf("\tNo active Loopbacks\n"); -} - -void -bt8370_print_counters(struct art_softc *ac) -{ - u_int16_t counters[5]; - u_int16_t hi, lo; - int i; - - for (i = 0; i < 5; i++) { - lo = ebus_read(&ac->art_ebus, Bt8370_FERR_LSB + i); - hi = ebus_read(&ac->art_ebus, Bt8370_FERR_LSB + i + 1); - - counters[i] = lo | (hi << 8); - } - - printf("%s: %hu framing bit errors, %hu CRC errors, ", - ac->art_dev.dv_xname, counters[0], counters[1]); - printf("%hu line code violations\n", counters[2]); - printf("%s: %hu Far End Errors %hu PRBS bit errors\n", - ac->art_dev.dv_xname, counters[3], counters[4]); -} -void -bt8370_dump_registers(struct art_softc *ac) -{ - int i; - - printf("%s: dummping registers", ac->art_dev.dv_xname); - for (i = 0; i < 0x200; i++) { - if (i % 16 == 0) - printf("\n%03x:", i); - printf("%s%02x%s", i % 2 ? "" : " ", - ebus_read(&ac->art_ebus, i), - i % 8 == 7 ? " " : ""); - } - printf("\n"); -} - -#endif diff --git a/sys/dev/pci/files.pci b/sys/dev/pci/files.pci index 4466905f6f6..1937f449a6b 100644 --- a/sys/dev/pci/files.pci +++ b/sys/dev/pci/files.pci @@ -1,4 +1,4 @@ -# $OpenBSD: files.pci,v 1.308 2014/08/15 14:07:39 mikeb Exp $ +# $OpenBSD: files.pci,v 1.309 2014/09/27 08:28:12 deraadt Exp $ # $NetBSD: files.pci,v 1.20 1996/09/24 17:47:15 christos Exp $ # # Config file and device description for machine-independent PCI code. @@ -733,18 +733,6 @@ device ichwdt {} attach ichwdt at pci file dev/pci/ichwdt.c ichwdt -# Mindspeed/Conexant MUSYCC HDLC controller -device musycc {} : ifnet -attach musycc at pci -file dev/pci/musycc.c musycc -file dev/pci/musycc_obsd.c musycc - -# Accoom Artery PCI card -device art: musycc, ifnet, ifmedia, sppp -attach art at musycc -file dev/pci/if_art.c art -file dev/pci/bt8370.c art - # VMware VMXnet virtual interface device vic: ether, ifnet, ifmedia attach vic at pci diff --git a/sys/dev/pci/if_art.c b/sys/dev/pci/if_art.c deleted file mode 100644 index df71aade7bf..00000000000 --- a/sys/dev/pci/if_art.c +++ /dev/null @@ -1,449 +0,0 @@ -/* $OpenBSD: if_art.c,v 1.21 2014/09/14 14:17:25 jsg Exp $ */ - -/* - * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Claudio Jeker <jeker@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include <sys/param.h> -#include <sys/types.h> - -#include <sys/device.h> -#include <sys/socket.h> -#include <sys/sockio.h> -#include <sys/syslog.h> -#include <sys/systm.h> - -#include <machine/bus.h> - -#include <net/if.h> -#include <net/if_media.h> -#include <net/if_sppp.h> - -#include <dev/pci/musyccvar.h> -#include <dev/pci/if_art.h> - -#define ART_E1_MASK 0xffffffff -#define ART_T1_MASK 0x01fffffe - -int art_match(struct device *, void *, void *); -void art_softc_attach(struct device *, struct device *, void *); - -int art_ioctl(struct ifnet *, u_long, caddr_t); -int art_ifm_change(struct ifnet *); -void art_ifm_status(struct ifnet *, struct ifmediareq *); -int art_ifm_options(struct ifnet *, struct channel_softc *, u_int); -void art_onesec(void *); -void art_linkstate(void *); -u_int32_t art_mask_tsmap(u_int, u_int32_t); - -struct cfattach art_ca = { - sizeof(struct art_softc), art_match, art_softc_attach -}; - -struct cfdriver art_cd = { - NULL, "art", DV_IFNET -}; - -int -art_match(struct device *parent, void *match, void *aux) -{ - struct musycc_attach_args *ma = aux; - - if (ma->ma_type == MUSYCC_FRAMER_BT8370) - return (1); - return (0); -} - -/* - * used for the one second timer - */ -extern int hz; - -void -art_softc_attach(struct device *parent, struct device *self, void *aux) -{ - struct art_softc *sc = (struct art_softc *)self; - struct musycc_softc *psc = (struct musycc_softc *)parent; - struct musycc_attach_args *ma = aux; - - printf(" \"%s\"", ma->ma_product); - - if (ebus_attach_device(&sc->art_ebus, psc, ma->ma_base, - ma->ma_size) != 0) { - printf(": can't map framer\n"); - return; - } - - /* set basic values */ - sc->art_port = ma->ma_port; - sc->art_slot = ma->ma_slot; - sc->art_gnum = ma->ma_gnum; - sc->art_type = ma->ma_flags & 0x03; - - sc->art_channel = musycc_channel_create(self->dv_xname, 1); - if (sc->art_channel == NULL) { - printf(": could not alloc channel descriptor\n"); - return; - } - - if (musycc_channel_attach(psc, sc->art_channel, self, sc->art_gnum) == - -1) { - printf(": unable to attach to hdlc controller\n"); - return; - } - - ifmedia_init(&sc->art_ifm, 0, art_ifm_change, art_ifm_status); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1, 0, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1_AMI, 0, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1, 0, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704, 0, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704_CRC4, 0, 0), 0, NULL); - - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1, IFM_TDM_MASTER, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1_AMI, IFM_TDM_MASTER, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1, IFM_TDM_MASTER, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704, IFM_TDM_MASTER, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704_CRC4, IFM_TDM_MASTER, 0), - 0, NULL); - - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1, IFM_TDM_PPP, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1, IFM_TDM_PPP, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1_AMI, IFM_TDM_PPP, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704, IFM_TDM_PPP, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704_CRC4, IFM_TDM_PPP, 0), 0, - NULL); - - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1, IFM_TDM_PPP | IFM_TDM_MASTER, 0), - 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1, IFM_TDM_PPP | IFM_TDM_MASTER, 0), - 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_T1_AMI, IFM_TDM_PPP | IFM_TDM_MASTER, - 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704, IFM_TDM_PPP | - IFM_TDM_MASTER, 0), 0, NULL); - ifmedia_add(&sc->art_ifm, - IFM_MAKEWORD(IFM_TDM, IFM_TDM_E1_G704_CRC4, IFM_TDM_PPP | - IFM_TDM_MASTER, 0), 0, NULL); - - printf("\n"); - - if (bt8370_reset(sc) != 0) - return; - - /* Initialize timeout for statistics update. */ - timeout_set(&sc->art_onesec, art_onesec, sc); - - ifmedia_set(&sc->art_ifm, IFM_TDM|IFM_TDM_E1_G704_CRC4); - sc->art_media = sc->art_ifm.ifm_media; - - bt8370_set_frame_mode(sc, sc->art_type, IFM_TDM_E1_G704_CRC4, 0); - musycc_attach_sppp(sc->art_channel, art_ioctl); - - /* Set linkstate hook to track link state changes done by sppp. */ - sc->art_linkstatehook = hook_establish( - sc->art_channel->cc_ifp->if_linkstatehooks, 0, art_linkstate, sc); - - /* Schedule the timeout one second from now. */ - timeout_add_sec(&sc->art_onesec, 1); -} - -/* interface ioctl */ -int -art_ioctl(struct ifnet *ifp, u_long command, caddr_t data) -{ - struct ifreq *ifr = (struct ifreq*) data; - struct channel_softc *cc = ifp->if_softc; - struct art_softc *ac = (struct art_softc *)cc->cc_parent; - u_int32_t tsmap; - int s, rv = 0; - - s = splnet(); - switch (command) { - case SIOCSIFADDR: - if ((rv = musycc_init_channel(cc, ac->art_slot))) - break; - rv = sppp_ioctl(ifp, command, data); - break; - case SIOCSIFTIMESLOT: - if ((rv = suser(curproc, 0)) != 0) - break; - rv = copyin(ifr->ifr_data, &tsmap, sizeof(tsmap)); - if (rv) - break; - if (art_mask_tsmap(IFM_SUBTYPE(ac->art_media), tsmap) != - tsmap) { - rv = EINVAL; - break; - } - if (ac->art_type == ART_SBI_SINGLE && - (IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1 || - IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1_AMI)) - /* - * need to adjust timeslot mask for T1 on single port - * cards. There timeslot 0-23 are usable not 1-24 - */ - tsmap >>= 1; - - cc->cc_tslots = tsmap; - rv = musycc_init_channel(cc, ac->art_slot); - break; - case SIOCGIFTIMESLOT: - tsmap = cc->cc_tslots; - if (ac->art_type == ART_SBI_SINGLE && - (IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1 || - IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1_AMI)) - tsmap <<= 1; - rv = copyout(&tsmap, ifr->ifr_data, sizeof(tsmap)); - break; - case SIOCSIFFLAGS: - /* - * If interface is marked up and not running, then start it. - * If it is marked down and running, stop it. - */ - if (ifr->ifr_flags & IFF_UP && cc->cc_state != CHAN_RUNNING) { - if ((rv = musycc_init_channel(cc, ac->art_slot))) - break; - } else if ((ifr->ifr_flags & IFF_UP) == 0 && - cc->cc_state == CHAN_RUNNING) - musycc_stop_channel(cc); - rv = sppp_ioctl(ifp, command, data); - break; - case SIOCSIFMEDIA: - case SIOCGIFMEDIA: - if (ac != NULL) - rv = ifmedia_ioctl(ifp, ifr, &ac->art_ifm, command); - else - rv = EINVAL; - break; - default: - rv = sppp_ioctl(ifp, command, data); - break; - } - splx(s); - return (rv); -} - -int -art_ifm_change(struct ifnet *ifp) -{ - struct channel_softc *cc = ifp->if_softc; - struct art_softc *ac = (struct art_softc *)cc->cc_parent; - struct ifmedia *ifm = &ac->art_ifm; - u_int64_t baudrate; - int rv, s; - - ACCOOM_PRINTF(2, ("%s: art_ifm_change %08x\n", ifp->if_xname, - ifm->ifm_media)); - - if (IFM_TYPE(ifm->ifm_media) != IFM_TDM) - return (EINVAL); - - /* OPTIONS (controller mode hdlc, ppp, eoe) */ - if ((rv = art_ifm_options(ifp, cc, IFM_OPTIONS(ifm->ifm_media))) != 0) - return (rv); - - /* SUBTYPE (framing mode T1/E1) + MODE (clocking master/slave) */ - if (IFM_SUBTYPE(ifm->ifm_media) != IFM_SUBTYPE(ac->art_media) || - IFM_MODE(ifm->ifm_media) != IFM_MODE(ac->art_media)) { - ACCOOM_PRINTF(0, ("%s: art_ifm_change type %d mode %x\n", - ifp->if_xname, IFM_SUBTYPE(ifm->ifm_media), - IFM_MODE(ifm->ifm_media))); - - bt8370_set_frame_mode(ac, ac->art_type, - IFM_SUBTYPE(ifm->ifm_media), IFM_MODE(ifm->ifm_media)); - - if (IFM_SUBTYPE(ifm->ifm_media) != IFM_SUBTYPE(ac->art_media)) { - /* adjust timeslot map on media change */ - cc->cc_tslots = art_mask_tsmap( - IFM_SUBTYPE(ifm->ifm_media), cc->cc_tslots); - - if (ac->art_type == ART_SBI_SINGLE && - (IFM_SUBTYPE(ifm->ifm_media) == IFM_TDM_T1 || - IFM_SUBTYPE(ifm->ifm_media) == IFM_TDM_T1_AMI) && - (IFM_SUBTYPE(ac->art_media) != IFM_TDM_T1 && - IFM_SUBTYPE(ac->art_media) != IFM_TDM_T1_AMI)) - /* - * need to adjust timeslot mask for T1 on - * single port cards. There timeslot 0-23 are - * usable not 1-24 - */ - cc->cc_tslots >>= 1; - else if (ac->art_type == ART_SBI_SINGLE && - (IFM_SUBTYPE(ifm->ifm_media) != IFM_TDM_T1 && - IFM_SUBTYPE(ifm->ifm_media) != IFM_TDM_T1_AMI) && - (IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1 || - IFM_SUBTYPE(ac->art_media) == IFM_TDM_T1_AMI)) - /* undo the last adjustment */ - cc->cc_tslots <<= 1; - } - - /* re-init the card */ - if ((rv = musycc_init_channel(cc, ac->art_slot))) - return (rv); - } - - baudrate = ifmedia_baudrate(ac->art_media); - if (baudrate != ifp->if_baudrate) { - ifp->if_baudrate = baudrate; - s = splsoftnet(); - if_link_state_change(ifp); - splx(s); - } - - ac->art_media = ifm->ifm_media; - - return (0); -} - -void -art_ifm_status(struct ifnet *ifp, struct ifmediareq *ifmreq) -{ - struct art_softc *ac; - - ac = (struct art_softc *) - ((struct channel_softc *)ifp->if_softc)->cc_parent; - ifmreq->ifm_status = IFM_AVALID; - if (LINK_STATE_IS_UP(ifp->if_link_state)) - ifmreq->ifm_status |= IFM_ACTIVE; - ifmreq->ifm_active = ac->art_media; - - return; -} - -int -art_ifm_options(struct ifnet *ifp, struct channel_softc *cc, u_int options) -{ - struct art_softc *ac = (struct art_softc *)cc->cc_parent; - u_int flags = cc->cc_ppp.pp_flags; - int rv; - - if (options == IFM_TDM_PPP) { - flags &= ~PP_CISCO; - flags |= PP_KEEPALIVE; - } else if (options == 0) { - flags |= PP_CISCO; - flags |= PP_KEEPALIVE; - } else { - ACCOOM_PRINTF(0, ("%s: Unsupported ifmedia options\n", - ifp->if_xname)); - return (EINVAL); - } - if (flags != cc->cc_ppp.pp_flags) { - musycc_stop_channel(cc); - cc->cc_ppp.pp_flags = flags; - if ((rv = musycc_init_channel(cc, ac->art_slot))) - return (rv); - return (sppp_ioctl(ifp, SIOCSIFFLAGS, NULL)); - } - return (0); -} - -void -art_onesec(void *arg) -{ - struct art_softc *ac = arg; - struct ifnet *ifp = ac->art_channel->cc_ifp; - struct sppp *ppp = &ac->art_channel->cc_ppp; - int s, rv, link_state; - - rv = bt8370_link_status(ac); - switch (rv) { - case 1: - link_state = LINK_STATE_UP; - /* set green led */ - ebus_set_led(ac->art_channel, 1, MUSYCC_LED_GREEN); - break; - case 0: - link_state = LINK_STATE_DOWN; - /* set green led and red led as well */ - ebus_set_led(ac->art_channel, 1, - MUSYCC_LED_GREEN | MUSYCC_LED_RED); - break; - default: - link_state = LINK_STATE_DOWN; - /* turn green led off */ - ebus_set_led(ac->art_channel, 0, MUSYCC_LED_GREEN); - break; - } - - if (link_state != ifp->if_link_state) { - s = splsoftnet(); - if (LINK_STATE_IS_UP(link_state)) - ppp->pp_up(ppp); - else - ppp->pp_down(ppp); - splx(s); - } - - /* - * run musycc onesec job - */ - musycc_tick(ac->art_channel); - - /* - * Schedule another timeout one second from now. - */ - timeout_add_sec(&ac->art_onesec, 1); -} - -void -art_linkstate(void *arg) -{ - struct art_softc *ac = arg; - struct ifnet *ifp = ac->art_channel->cc_ifp; - - if (LINK_STATE_IS_UP(ifp->if_link_state)) - /* turn red led off */ - ebus_set_led(ac->art_channel, 0, MUSYCC_LED_RED); - else - /* turn red led on */ - ebus_set_led(ac->art_channel, 1, MUSYCC_LED_RED); -} - -u_int32_t -art_mask_tsmap(u_int mode, u_int32_t tsmap) -{ - switch (mode) { - case IFM_TDM_E1: - case IFM_TDM_E1_G704: - case IFM_TDM_E1_G704_CRC4: - return (tsmap & ART_E1_MASK); - case IFM_TDM_T1_AMI: - case IFM_TDM_T1: - return (tsmap & ART_T1_MASK); - default: - return (tsmap); - } -} diff --git a/sys/dev/pci/if_art.h b/sys/dev/pci/if_art.h deleted file mode 100644 index 880ff22754a..00000000000 --- a/sys/dev/pci/if_art.h +++ /dev/null @@ -1,83 +0,0 @@ -/* $OpenBSD: if_art.h,v 1.5 2005/10/26 09:26:56 claudio Exp $ */ - -/* - * Copyright (c) 2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Claudio Jeker <jeker@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#ifndef __IF_ART_H__ -#define __IF_ART_H__ - -#define MUSYCC_FRAMER_BT8370 0x8370 - -enum art_sbi_type { - ART_SBI_SINGLE, - ART_SBI_MASTER, - ART_SBI_SLAVE -}; - -struct art_softc { - struct device art_dev; /* generic device structures */ - struct ebus_dev art_ebus; /* ebus attachement */ - struct ifmedia art_ifm; /* interface media descriptor */ - struct timeout art_onesec; /* onesec timeout */ - struct musycc_softc *art_parent; /* parent hdlc controller */ - struct channel_softc *art_channel; /* channel config */ - void *art_linkstatehook; - - u_int art_media; /* if_media media */ - enum art_sbi_type art_type; /* System Bus Type */ - u_int8_t art_gnum; /* group number */ - u_int8_t art_port; /* port number */ - char art_slot; /* TDM slot */ -}; - -enum art_sbi_mode { - SBI_MODE_1536 = 1, /* 24TS */ - SBI_MODE_1544, /* 24TS + F bit */ - SBI_MODE_2048, /* 32TS */ - SBI_MODE_4096_A, /* lower 32TS */ - SBI_MODE_4096_B, /* upper 32TS */ - SBI_MODE_8192_A, /* first 32TS */ - SBI_MODE_8192_B, /* second 32TS */ - SBI_MODE_8192_C, /* third 32TS */ - SBI_MODE_8192_D /* last 32TS */ -}; - -enum art_linecode { - ART_LIU_AMI, /* Alternate Mark Inversion */ - ART_LIU_B8ZS, /* Bipolar 8-zero Substitution */ - ART_LIU_HDB3 /* High Density Bipolar 3 */ -}; - -enum art_loopback { - ART_NOLOOP, /* All Loopback disabled */ - ART_RLOOP_PAYLOAD, /* Remote Payload Loopback */ - ART_RLOOP_LINE, /* Remote Line Loopback */ - ART_LLOOP_PAYLOAD, /* Local Payload Loopback */ - ART_LLOOP_LINE /* Local Line Loopback */ -}; - -#define ART_DL1_BOP 1 -#define ART_BOP_ESF 1 - -int bt8370_reset(struct art_softc *); -int bt8370_set_frame_mode(struct art_softc *, enum art_sbi_type, u_int, - u_int); -void bt8370_intr_enable(struct art_softc *, int); -void bt8370_intr(struct art_softc *); -int bt8370_link_status(struct art_softc *); - -#endif diff --git a/sys/dev/pci/musycc.c b/sys/dev/pci/musycc.c deleted file mode 100644 index ae73a363f0b..00000000000 --- a/sys/dev/pci/musycc.c +++ /dev/null @@ -1,2001 +0,0 @@ -/* $OpenBSD: musycc.c,v 1.22 2014/07/13 23:10:23 deraadt Exp $ */ - -/* - * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Claudio Jeker <jeker@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#include "bpfilter.h" - -#include <sys/param.h> -#include <sys/types.h> - -#include <sys/device.h> -#include <sys/kernel.h> -#include <sys/limits.h> -#include <sys/malloc.h> -#include <sys/mbuf.h> -#include <sys/socket.h> -#include <sys/syslog.h> -#include <sys/systm.h> - -#include <machine/cpu.h> -#include <machine/bus.h> -#include <machine/intr.h> - -#include <net/if.h> -#include <net/if_media.h> -#include <net/if_sppp.h> - -#if NBPFILTER > 0 -#include <net/bpf.h> -#endif - -#include <dev/pci/musyccvar.h> -#include <dev/pci/musyccreg.h> - -int musycc_alloc_groupdesc(struct musycc_softc *); -int musycc_alloc_intqueue(struct musycc_softc *); -int musycc_alloc_group(struct musycc_group *); -void musycc_free_groupdesc(struct musycc_softc *); -void musycc_free_intqueue(struct musycc_softc *); -void musycc_free_dmadesc(struct musycc_group *); -void musycc_free_group(struct musycc_group *); -void musycc_set_group(struct musycc_group *, int, int, int); -int musycc_set_tsmap(struct musycc_group *, struct channel_softc *, char); -int musycc_set_chandesc(struct musycc_group *, int, int, int); -void musycc_activate_channel(struct musycc_group *, int); -void musycc_state_engine(struct musycc_group *, int, enum musycc_event); - -struct dma_desc *musycc_dma_get(struct musycc_group *); -void musycc_dma_free(struct musycc_group *, struct dma_desc *); -int musycc_list_tx_init(struct musycc_group *, int, int); -int musycc_list_rx_init(struct musycc_group *, int, int); -void musycc_list_tx_free(struct musycc_group *, int); -void musycc_list_rx_free(struct musycc_group *, int); -void musycc_reinit_dma(struct musycc_group *, int); -int musycc_newbuf(struct musycc_group *, struct dma_desc *, struct mbuf *); -int musycc_encap(struct musycc_group *, struct mbuf *, int); - -void musycc_rxeom(struct musycc_group *, int, int); -void musycc_txeom(struct musycc_group *, int, int); -void musycc_kick(struct musycc_group *); -void musycc_sreq(struct musycc_group *, int, u_int32_t, int, - enum musycc_event); - -#ifndef ACCOOM_DEBUG -#define musycc_dump_group(n, x) -#define musycc_dump_desc(n, x) -#define musycc_dump_dma(n, x, y) -#else -int accoom_debug = 0; - -char *musycc_intr_print(u_int32_t); -void musycc_dump_group(int, struct musycc_group *); -void musycc_dump_desc(int, struct musycc_group *); -void musycc_dump_dma(int, struct musycc_group *, int); -#endif - -int -musycc_attach_common(struct musycc_softc *sc, u_int32_t portmap, u_int32_t mode) -{ - struct musycc_group *mg; - int i, j; - - if (musycc_alloc_groupdesc(sc) == -1) { - printf(": couldn't alloc group descriptors\n"); - return (-1); - } - - if (musycc_alloc_intqueue(sc) == -1) { - printf(": couldn't alloc interrupt queue\n"); - musycc_free_groupdesc(sc); - return (-1); - } - - /* - * global configuration: set EBUS to sane defaults: - * intel mode, elapse = 3, blapse = 3, alapse = 3 - * XXX XXX disable INTB for now - */ - sc->mc_global_conf = (portmap & MUSYCC_CONF_PORTMAP) | - MUSYCC_CONF_MPUSEL | MUSYCC_CONF_ECKEN | - MUSYCC_CONF_ELAPSE_SET(3) | MUSYCC_CONF_ALAPSE_SET(3) | - MUSYCC_CONF_BLAPSE_SET(3) | MUSYCC_CONF_INTB; - - /* initialize group descriptors */ - sc->mc_groups = mallocarray(sc->mc_ngroups, - sizeof(struct musycc_group), M_DEVBUF, M_NOWAIT | M_ZERO); - if (sc->mc_groups == NULL) { - printf(": couldn't alloc group descriptors\n"); - musycc_free_groupdesc(sc); - musycc_free_intqueue(sc); - return (-1); - } - - for (i = 0; i < sc->mc_ngroups; i++) { - mg = &sc->mc_groups[i]; - mg->mg_hdlc = sc; - mg->mg_gnum = i; - mg->mg_port = i >> (portmap & MUSYCC_CONF_PORTMAP); - mg->mg_dmat = sc->mc_dmat; - - if (musycc_alloc_group(mg) == -1) { - printf(": couldn't alloc group structures\n"); - for (j = 0; j < i; j++) - musycc_free_group(&sc->mc_groups[j]); - musycc_free_groupdesc(sc); - musycc_free_intqueue(sc); - return (-1); - } - - mg->mg_group = (struct musycc_grpdesc *) - (sc->mc_groupkva + MUSYCC_GROUPBASE(i)); - bzero(mg->mg_group, sizeof(struct musycc_grpdesc)); - musycc_set_group(mg, MUSYCC_GRCFG_POLL32, MUSYCC_MAXFRM_MAX, - MUSYCC_MAXFRM_MAX); - musycc_set_port(mg, mode); - - bus_dmamap_sync(sc->mc_dmat, sc->mc_cfgmap, - MUSYCC_GROUPBASE(i), sizeof(struct musycc_grpdesc), - BUS_DMASYNC_PREWRITE); - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_GROUPBASE(i), - sc->mc_cfgmap->dm_segs[0].ds_addr + MUSYCC_GROUPBASE(i)); - } - - /* Dual Address Cycle Base Pointer */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_DACB_PTR, 0); - /* Global Configuration Descriptor */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_GLOBALCONF, - sc->mc_global_conf); - /* Interrupt Queue Descriptor */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_INTQPTR, - sc->mc_intrqptr); - /* - * Interrupt Queue Length. - * NOTE: a value of 1 indicates a queue length of 2 descriptors! - */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_INTQLEN, - MUSYCC_INTLEN - 1); - - /* Configure groups, needs to be done only once per group */ - for (i = 0; i < sc->mc_ngroups; i++) { - mg = &sc->mc_groups[i]; - musycc_sreq(mg, 0, MUSYCC_SREQ_SET(5), MUSYCC_SREQ_BOTH, - EV_NULL); - mg->mg_loaded = 1; - } - - return (0); -} - -int -musycc_alloc_groupdesc(struct musycc_softc *sc) -{ - /* - * Allocate per group/port shared memory. - * One big cunck of nports * 2048 bytes is allocated. This is - * done to ensure that all group structures are 2048 bytes aligned. - */ - if (bus_dmamem_alloc(sc->mc_dmat, sc->mc_ngroups * 2048, - 2048, 0, sc->mc_cfgseg, 1, &sc->mc_cfgnseg, BUS_DMA_NOWAIT)) { - return (-1); - } - if (bus_dmamem_map(sc->mc_dmat, sc->mc_cfgseg, sc->mc_cfgnseg, - sc->mc_ngroups * 2048, &sc->mc_groupkva, BUS_DMA_NOWAIT)) { - bus_dmamem_free(sc->mc_dmat, sc->mc_cfgseg, sc->mc_cfgnseg); - return (-1); - } - /* create and load bus dma segment, one for all ports */ - if (bus_dmamap_create(sc->mc_dmat, sc->mc_ngroups * 2048, - 1, sc->mc_ngroups * 2048, 0, BUS_DMA_NOWAIT, &sc->mc_cfgmap)) { - bus_dmamem_unmap(sc->mc_dmat, sc->mc_groupkva, - sc->mc_ngroups * 2048); - bus_dmamem_free(sc->mc_dmat, sc->mc_cfgseg, sc->mc_cfgnseg); - return (-1); - } - if (bus_dmamap_load(sc->mc_dmat, sc->mc_cfgmap, sc->mc_groupkva, - sc->mc_ngroups * 2048, NULL, BUS_DMA_NOWAIT)) { - musycc_free_groupdesc(sc); - return (-1); - } - - return (0); -} - -int -musycc_alloc_intqueue(struct musycc_softc *sc) -{ - /* - * allocate interrupt queue, use one page for the queue - */ - if (bus_dmamem_alloc(sc->mc_dmat, sizeof(struct musycc_intdesc), 4, 0, - sc->mc_intrseg, 1, &sc->mc_intrnseg, BUS_DMA_NOWAIT)) { - return (-1); - } - if (bus_dmamem_map(sc->mc_dmat, sc->mc_intrseg, sc->mc_intrnseg, - sizeof(struct musycc_intdesc), (caddr_t *)&sc->mc_intrd, - BUS_DMA_NOWAIT)) { - bus_dmamem_free(sc->mc_dmat, sc->mc_intrseg, sc->mc_intrnseg); - return (-1); - } - - /* create and load bus dma segment */ - if (bus_dmamap_create(sc->mc_dmat, sizeof(struct musycc_intdesc), - 1, sizeof(struct musycc_intdesc), 0, BUS_DMA_NOWAIT, - &sc->mc_intrmap)) { - bus_dmamem_unmap(sc->mc_dmat, (caddr_t)sc->mc_intrd, - sizeof(struct musycc_intdesc)); - bus_dmamem_free(sc->mc_dmat, sc->mc_intrseg, sc->mc_intrnseg); - return (-1); - } - if (bus_dmamap_load(sc->mc_dmat, sc->mc_intrmap, sc->mc_intrd, - sizeof(struct musycc_intdesc), NULL, BUS_DMA_NOWAIT)) { - musycc_free_intqueue(sc); - return (-1); - } - - /* initialize the interrupt queue pointer */ - sc->mc_intrqptr = sc->mc_intrmap->dm_segs[0].ds_addr + - offsetof(struct musycc_intdesc, md_intrq[0]); - - return (0); -} - -int -musycc_alloc_group(struct musycc_group *mg) -{ - struct dma_desc *dd; - int j; - - /* Allocate per group dma memory */ - if (bus_dmamem_alloc(mg->mg_dmat, MUSYCC_DMA_MAPSIZE, - PAGE_SIZE, 0, mg->mg_listseg, 1, &mg->mg_listnseg, - BUS_DMA_NOWAIT | BUS_DMA_ZERO)) - return (-1); - if (bus_dmamem_map(mg->mg_dmat, mg->mg_listseg, mg->mg_listnseg, - MUSYCC_DMA_MAPSIZE, &mg->mg_listkva, BUS_DMA_NOWAIT)) { - bus_dmamem_free(mg->mg_dmat, mg->mg_listseg, mg->mg_listnseg); - return (-1); - } - - /* create and load bus dma segment */ - if (bus_dmamap_create(mg->mg_dmat, MUSYCC_DMA_MAPSIZE, 1, - MUSYCC_DMA_MAPSIZE, 0, BUS_DMA_NOWAIT, &mg->mg_listmap)) { - bus_dmamem_unmap(mg->mg_dmat, mg->mg_listkva, - MUSYCC_DMA_MAPSIZE); - bus_dmamem_free(mg->mg_dmat, mg->mg_listseg, mg->mg_listnseg); - return (-1); - } - if (bus_dmamap_load(mg->mg_dmat, mg->mg_listmap, mg->mg_listkva, - MUSYCC_DMA_MAPSIZE, NULL, BUS_DMA_NOWAIT)) { - musycc_free_dmadesc(mg); - return (-1); - } - - /* - * Create spare maps for musycc_start and musycc_newbuf. - * Limit the dma queue to MUSYCC_DMA_SIZE entries even though there - * is no actual hard limit from the chip. - */ - if (bus_dmamap_create(mg->mg_dmat, MCLBYTES, MUSYCC_DMA_SIZE, MCLBYTES, - 0, BUS_DMA_NOWAIT, &mg->mg_tx_sparemap) != 0) { - musycc_free_dmadesc(mg); - return (-1); - } - if (bus_dmamap_create(mg->mg_dmat, MCLBYTES, MUSYCC_DMA_SIZE, MCLBYTES, - 0, BUS_DMA_NOWAIT, &mg->mg_rx_sparemap) != 0) { - bus_dmamap_destroy(mg->mg_dmat, mg->mg_tx_sparemap); - musycc_free_dmadesc(mg); - return (-1); - } - - mg->mg_dma_pool = (struct dma_desc *)mg->mg_listkva; - - /* add all descriptors to the freelist */ - for (j = 0; j < MUSYCC_DMA_CNT; j++) { - dd = &mg->mg_dma_pool[j]; - /* initialize, same as for spare maps */ - if (bus_dmamap_create(mg->mg_dmat, MCLBYTES, MUSYCC_DMA_SIZE, - MCLBYTES, 0, BUS_DMA_NOWAIT, &dd->map)) { - musycc_free_group(mg); - return (-1); - } - /* link */ - dd->nextdesc = mg->mg_freelist; - mg->mg_freelist = dd; - mg->mg_freecnt++; - } - - return (0); -} - -void -musycc_free_groupdesc(struct musycc_softc *sc) -{ - bus_dmamap_destroy(sc->mc_dmat, sc->mc_cfgmap); - bus_dmamem_unmap(sc->mc_dmat, sc->mc_groupkva, - sc->mc_ngroups * 2048); - bus_dmamem_free(sc->mc_dmat, sc->mc_cfgseg, sc->mc_cfgnseg); -} - -void -musycc_free_intqueue(struct musycc_softc *sc) -{ - bus_dmamap_destroy(sc->mc_dmat, sc->mc_intrmap); - bus_dmamem_unmap(sc->mc_dmat, (caddr_t)sc->mc_intrd, - sizeof(struct musycc_intdesc)); - bus_dmamem_free(sc->mc_dmat, sc->mc_intrseg, sc->mc_intrnseg); -} - -void -musycc_free_dmadesc(struct musycc_group *mg) -{ - bus_dmamap_destroy(mg->mg_dmat, mg->mg_listmap); - bus_dmamem_unmap(mg->mg_dmat, mg->mg_listkva, - MUSYCC_DMA_MAPSIZE); - bus_dmamem_free(mg->mg_dmat, mg->mg_listseg, mg->mg_listnseg); -} - -void -musycc_free_group(struct musycc_group *mg) -{ - bus_dmamap_destroy(mg->mg_dmat, mg->mg_tx_sparemap); - bus_dmamap_destroy(mg->mg_dmat, mg->mg_tx_sparemap); - /* XXX dma descriptors ? */ - musycc_free_dmadesc(mg); - mg->mg_dma_pool = NULL; - mg->mg_freelist = NULL; - mg->mg_freecnt = 0; -} - -void -musycc_set_group(struct musycc_group *mg, int poll, int maxa, int maxb) -{ - /* set global conf and interrupt descriptor */ - mg->mg_group->global_conf = htole32(mg->mg_hdlc->mc_global_conf); - /* - * Interrupt Queue and Length. - * NOTE: a value of 1 indicates the queue length of 2 descriptors! - */ - mg->mg_group->int_queuep = htole32(mg->mg_hdlc->mc_intrqptr); - mg->mg_group->int_queuelen = htole32(MUSYCC_INTLEN - 1); - - /* group config */ - mg->mg_group->group_conf = htole32(MUSYCC_GRCFG_RXENBL | - MUSYCC_GRCFG_TXENBL | MUSYCC_GRCFG_SUBDSBL | - MUSYCC_GRCFG_MSKCOFA | MUSYCC_GRCFG_MSKOOF | - MUSYCC_GRCFG_MCENBL | (poll & MUSYCC_GRCFG_POLL64)); - - /* memory protection, not supported by device */ - - /* message length config, preinit with useful data */ - /* this is currently not used and the max is limited to 4094 bytes */ - mg->mg_group->msglen_conf = htole32(maxa); - mg->mg_group->msglen_conf |= htole32(maxb << MUSYCC_MAXFRM2_SHIFT); -} - -void -musycc_set_port(struct musycc_group *mg, int mode) -{ - /* - * All signals trigger on falling edge only exception is TSYNC - * which triggers on rising edge. For the framer TSYNC is set to - * falling edge too but Musycc needs rising edge or everything gets - * off by one. Don't three-state TX (not needed). - */ - mg->mg_group->port_conf = htole32(MUSYCC_PORT_TSYNC_EDGE | - MUSYCC_PORT_TRITX | (mode & MUSYCC_PORT_MODEMASK)); - - if (mg->mg_loaded) - musycc_sreq(mg, 0, MUSYCC_SREQ_SET(21), MUSYCC_SREQ_RX, - EV_NULL); -} - -/* - * Channel specifc calls - */ -int -musycc_set_tsmap(struct musycc_group *mg, struct channel_softc *cc, char slot) -{ - int i, nslots = 0, off, scale; - u_int32_t tslots = cc->cc_tslots; - - ACCOOM_PRINTF(1, ("%s: musycc_set_tsmap %08x slot %c\n", - cc->cc_ifp->if_xname, tslots, slot)); - - switch (slot) { - case 'A': /* single port, non interleaved */ - off = 0; - scale = 1; - break; - case 'a': /* dual port, interleaved */ - case 'b': - off = slot - 'a'; - scale = 2; - break; - case '1': /* possible quad port, interleaved */ - case '2': - case '3': - case '4': - off = slot - '1'; - scale = 4; - break; - default: - /* impossible */ - log(LOG_ERR, "%s: accessing unsupported slot %c", - cc->cc_ifp->if_xname, slot); - return (-1); - } - - /* - * setup timeslot map but first make sure no timeslot is already used - * note: 56kbps mode for T1-SF needs to be set in here - * note2: if running with port mapping the other group needs to be - * checked too or we may get funny results. Currenly not possible - * because of the slot offsets (odd, even slots). - */ - for (i = 0; i < sizeof(u_int32_t) * 8; i++) - if (tslots & (1 << i)) - if (mg->mg_group->tx_tsmap[i * scale + off] & - MUSYCC_TSLOT_ENABLED || - mg->mg_group->rx_tsmap[i * scale + off] & - MUSYCC_TSLOT_ENABLED) - return (0); - - for (i = 0; i < sizeof(u_int32_t) * 8; i++) - if (tslots & (1 << i)) { - nslots++; - mg->mg_group->tx_tsmap[i * scale + off] = - MUSYCC_TSLOT_CHAN(cc->cc_channel) | - MUSYCC_TSLOT_ENABLED; - mg->mg_group->rx_tsmap[i * scale + off] = - MUSYCC_TSLOT_CHAN(cc->cc_channel) | - MUSYCC_TSLOT_ENABLED; - } - - return (nslots); -} - -int -musycc_set_chandesc(struct musycc_group *mg, int chan, int nslots, int proto) -{ - u_int64_t mask = ULLONG_MAX; - int idx, n; - - ACCOOM_PRINTF(1, ("%s: musycc_set_chandesc nslots %d proto %d\n", - mg->mg_channels[chan]->cc_ifp->if_xname, nslots, proto)); - - if (nslots == 0 || nslots > 32) - return (EINVAL); - - n = 64 - 2 * nslots; - mask >>= n; - - for (idx = 0; idx <= n; idx += 2) - if (!(mg->mg_fifomask & mask << idx)) - break; - - if (idx > n) - return (EBUSY); - - mg->mg_fifomask |= mask << idx; - - /* setup channel descriptor */ - mg->mg_group->tx_cconf[chan] = htole32(MUSYCC_CHAN_BUFIDX_SET(idx) | - MUSYCC_CHAN_BUFLEN_SET(nslots * 2 - 1) | - MUSYCC_CHAN_PROTO_SET(proto)); - mg->mg_group->rx_cconf[chan] = htole32(MUSYCC_CHAN_BUFIDX_SET(idx) | - MUSYCC_CHAN_BUFLEN_SET(nslots * 2 - 1) | - MUSYCC_CHAN_MSKIDLE | MUSYCC_CHAN_MSKSUERR | MUSYCC_CHAN_MSKSINC | - MUSYCC_CHAN_MSKSDEC | MUSYCC_CHAN_MSKSFILT | - MUSYCC_CHAN_PROTO_SET(proto)); - - return (0); -} - -int -musycc_init_channel(struct channel_softc *cc, char slot) -{ - struct musycc_group *mg; - struct ifnet *ifp = cc->cc_ifp; - int nslots, rv, s; - - if (cc->cc_state == CHAN_FLOAT) - return (ENOTTY); - mg = cc->cc_group; - - ACCOOM_PRINTF(2, ("%s: musycc_init_channel [state %d] slot %c\n", - cc->cc_ifp->if_xname, cc->cc_state, slot)); - - if (cc->cc_state != CHAN_IDLE) { - musycc_sreq(mg, cc->cc_channel, MUSYCC_SREQ_SET(9), - MUSYCC_SREQ_BOTH, EV_STOP); - tsleep(cc, PZERO | PCATCH, "musycc", hz); - if (cc->cc_state != CHAN_IDLE) { - ACCOOM_PRINTF(0, ("%s: failed to reset channel\n", - cc->cc_ifp->if_xname)); - return (EIO); - } - } - - s = splnet(); - /* setup timeslot map */ - nslots = musycc_set_tsmap(mg, cc, slot); - if (nslots == -1) { - rv = EINVAL; - goto fail; - } else if (nslots == 0) { - rv = EBUSY; - goto fail; - } - - if ((rv = musycc_set_chandesc(mg, cc->cc_channel, nslots, - MUSYCC_PROTO_HDLC16))) - goto fail; - - /* setup tx DMA chain */ - musycc_list_tx_init(mg, cc->cc_channel, MUSYCC_DMA_SIZE); - /* setup rx DMA chain */ - if ((rv = musycc_list_rx_init(mg, cc->cc_channel, MUSYCC_DMA_SIZE))) { - ACCOOM_PRINTF(0, ("%s: initialization failed: " - "no memory for rx buffers\n", cc->cc_ifp->if_xname)); - goto fail; - } - - /* IFF_RUNNING set by sppp_ioctl() */ - ifp->if_flags &= ~IFF_OACTIVE; - - cc->cc_state = CHAN_TRANSIENT; - splx(s); - - musycc_dump_group(3, mg); - musycc_activate_channel(mg, cc->cc_channel); - tsleep(cc, PZERO | PCATCH, "musycc", hz); - - /* - * XXX we could actually check if the activation of the channels was - * successful but what type of error should we return? - */ - return (0); - -fail: - splx(s); - cc->cc_state = CHAN_IDLE; /* force idle state */ - musycc_free_channel(mg, cc->cc_channel); - return (rv); -} - -void -musycc_activate_channel(struct musycc_group *mg, int chan) -{ - ACCOOM_PRINTF(2, ("%s: musycc_activate_channel\n", - mg->mg_channels[chan]->cc_ifp->if_xname)); - musycc_sreq(mg, chan, MUSYCC_SREQ_SET(26), MUSYCC_SREQ_BOTH, - EV_NULL); - musycc_sreq(mg, chan, MUSYCC_SREQ_SET(24), MUSYCC_SREQ_BOTH, - EV_NULL); - musycc_sreq(mg, chan, MUSYCC_SREQ_SET(8), MUSYCC_SREQ_BOTH, - EV_ACTIVATE); -} - -void -musycc_stop_channel(struct channel_softc *cc) -{ - struct musycc_group *mg = cc->cc_group; - - if (cc->cc_state == CHAN_FLOAT) { - /* impossible */ - log(LOG_ERR, "%s: unexpected state in musycc_stop_channel", - cc->cc_ifp->if_xname); - cc->cc_state = CHAN_IDLE; /* reset */ - musycc_free_channel(mg, cc->cc_channel); - return; - } - - ACCOOM_PRINTF(2, ("%s: musycc_stop_channel\n", cc->cc_ifp->if_xname)); - musycc_sreq(mg, cc->cc_channel, MUSYCC_SREQ_SET(9), MUSYCC_SREQ_BOTH, - EV_STOP); - tsleep(cc, PZERO | PCATCH, "musycc", hz); -} - -void -musycc_free_channel(struct musycc_group *mg, int chan) -{ - u_int64_t mask = ULLONG_MAX; - int i, idx, s, slots; - - ACCOOM_PRINTF(2, ("%s: musycc_free_channel\n", - mg->mg_channels[chan]->cc_ifp->if_xname)); - - s = splnet(); - /* Clear the timeout timer. */ - mg->mg_channels[chan]->cc_ifp->if_timer = 0; - - /* clear timeslot map */ - for (i = 0; i < 128; i++) { - if (mg->mg_group->tx_tsmap[i] & MUSYCC_TSLOT_ENABLED) - if ((mg->mg_group->tx_tsmap[i] & MUSYCC_TSLOT_MASK) == - chan) - mg->mg_group->tx_tsmap[i] = 0; - if (mg->mg_group->rx_tsmap[i] & MUSYCC_TSLOT_ENABLED) - if ((mg->mg_group->rx_tsmap[i] & MUSYCC_TSLOT_MASK) == - chan) - mg->mg_group->rx_tsmap[i] = 0; - } - - /* clear channel descriptor, especially free FIFO space */ - idx = MUSYCC_CHAN_BUFIDX_GET(letoh32(mg->mg_group->tx_cconf[chan])); - slots = MUSYCC_CHAN_BUFLEN_GET(letoh32(mg->mg_group->tx_cconf[chan])); - slots = (slots + 1) / 2; - mask >>= 64 - 2 * slots; - mask <<= idx; - mg->mg_fifomask &= ~mask; - mg->mg_group->tx_cconf[chan] = 0; - mg->mg_group->rx_cconf[chan] = 0; - - /* free dma rings */ - musycc_list_rx_free(mg, chan); - musycc_list_tx_free(mg, chan); - - splx(s); - - /* update chip info with sreq */ - musycc_sreq(mg, chan, MUSYCC_SREQ_SET(24), MUSYCC_SREQ_BOTH, - EV_NULL); - musycc_sreq(mg, chan, MUSYCC_SREQ_SET(26), MUSYCC_SREQ_BOTH, - EV_IDLE); -} - -void -musycc_state_engine(struct musycc_group *mg, int chan, enum musycc_event ev) -{ - enum musycc_state state; - - if (mg->mg_channels[chan] == NULL) - return; - - state = mg->mg_channels[chan]->cc_state; - - ACCOOM_PRINTF(2, ("%s: musycc_state_engine state %d event %d\n", - mg->mg_channels[chan]->cc_ifp->if_xname, state, ev)); - - switch (ev) { - case EV_NULL: - /* no state change */ - return; - case EV_ACTIVATE: - state = CHAN_RUNNING; - break; - case EV_STOP: - /* channel disabled now free dma rings et al. */ - mg->mg_channels[chan]->cc_state = CHAN_TRANSIENT; - musycc_free_channel(mg, chan); - return; - case EV_IDLE: - state = CHAN_IDLE; - break; - case EV_WATCHDOG: - musycc_reinit_dma(mg, chan); - return; - } - - mg->mg_channels[chan]->cc_state = state; - wakeup(mg->mg_channels[chan]); -} - -/* - * DMA handling functions - */ - -struct dma_desc * -musycc_dma_get(struct musycc_group *mg) -{ - struct dma_desc *dd; - - splassert(IPL_NET); - - if (mg->mg_freecnt == 0) - return (NULL); - mg->mg_freecnt--; - dd = mg->mg_freelist; - mg->mg_freelist = dd->nextdesc; - /* clear some important data */ - dd->nextdesc = NULL; - dd->mbuf = NULL; - - return (dd); -} - -void -musycc_dma_free(struct musycc_group *mg, struct dma_desc *dd) -{ - splassert(IPL_NET); - - dd->nextdesc = mg->mg_freelist; - mg->mg_freelist = dd; - mg->mg_freecnt++; -} - -/* - * Initialize the transmit descriptors. Acctually they are left empty until - * a packet comes in. - */ -int -musycc_list_tx_init(struct musycc_group *mg, int c, int size) -{ - struct musycc_dma_data *md; - struct dma_desc *dd; - bus_addr_t base; - int i; - - splassert(IPL_NET); - ACCOOM_PRINTF(2, ("musycc_list_tx_init\n")); - md = &mg->mg_dma_d[c]; - md->tx_pend = NULL; - md->tx_cur = NULL; - md->tx_cnt = size; - md->tx_pkts = 0; - - base = mg->mg_listmap->dm_segs[0].ds_addr; - for (i = 0; i < md->tx_cnt; i++) { - dd = musycc_dma_get(mg); - if (dd == NULL) { - ACCOOM_PRINTF(0, ("musycc_list_tx_init: " - "out of dma_desc\n")); - musycc_list_tx_free(mg, c); - return (ENOBUFS); - } - dd->status = 0 /* MUSYCC_STATUS_NOPOLL */; - dd->data = 0; - if (md->tx_cur) { - md->tx_cur->nextdesc = dd; - md->tx_cur->next = htole32(base + (caddr_t)dd - - mg->mg_listkva); - md->tx_cur = dd; - } else - md->tx_pend = md->tx_cur = dd; - } - - dd->nextdesc = md->tx_pend; - dd->next = htole32(base + (caddr_t)md->tx_pend - mg->mg_listkva); - md->tx_pend = dd; - - mg->mg_group->tx_headp[c] = htole32(base + (caddr_t)dd - - mg->mg_listkva); - - bus_dmamap_sync(mg->mg_dmat, mg->mg_listmap, 0, MUSYCC_DMA_MAPSIZE, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - return (0); -} - - -/* - * Initialize the RX descriptors and allocate mbufs for them. Note that - * we arrange the descriptors in a closed ring, so that the last descriptor - * points back to the first. - */ -int -musycc_list_rx_init(struct musycc_group *mg, int c, int size) -{ - struct musycc_dma_data *md; - struct dma_desc *dd = NULL, *last; - bus_addr_t base; - int i; - - splassert(IPL_NET); - ACCOOM_PRINTF(2, ("musycc_list_rx_init\n")); - md = &mg->mg_dma_d[c]; - md->rx_cnt = size; - - base = mg->mg_listmap->dm_segs[0].ds_addr; - for (i = 0; i < size; i++) { - dd = musycc_dma_get(mg); - if (dd == NULL) { - ACCOOM_PRINTF(0, ("musycc_list_rx_init: " - "out of dma_desc\n")); - musycc_list_rx_free(mg, c); - return (ENOBUFS); - } - if (musycc_newbuf(mg, dd, NULL) == ENOBUFS) { - ACCOOM_PRINTF(0, ("musycc_list_rx_init: " - "out of mbufs\n")); - musycc_list_rx_free(mg, c); - return (ENOBUFS); - } - if (md->rx_prod) { - md->rx_prod->nextdesc = dd; - md->rx_prod->next = htole32(base + (caddr_t)dd - - mg->mg_listkva); - md->rx_prod = dd; - } else - last = md->rx_prod = dd; - } - - dd->nextdesc = last; - dd->next = htole32(base + (caddr_t)last - mg->mg_listkva); - - mg->mg_group->rx_headp[c] = htole32(base + (caddr_t)dd - - mg->mg_listkva); - - bus_dmamap_sync(mg->mg_dmat, mg->mg_listmap, 0, MUSYCC_DMA_MAPSIZE, - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - return (0); -} - -void -musycc_list_tx_free(struct musycc_group *mg, int c) -{ - struct musycc_dma_data *md; - struct dma_desc *dd, *tmp; - - md = &mg->mg_dma_d[c]; - - splassert(IPL_NET); - ACCOOM_PRINTF(2, ("musycc_list_tx_free\n")); - dd = md->tx_pend; - do { - if (dd == NULL) - break; - if (dd->map->dm_nsegs != 0) { - bus_dmamap_t map = dd->map; - - bus_dmamap_unload(mg->mg_dmat, map); - } - if (dd->mbuf != NULL) { - m_freem(dd->mbuf); - dd->mbuf = NULL; - } - tmp = dd; - dd = dd->nextdesc; - musycc_dma_free(mg, tmp); - } while (dd != md->tx_pend); - md->tx_pend = md->tx_cur = NULL; - md->tx_cnt = md->tx_use = md->tx_pkts = 0; -} - -void -musycc_list_rx_free(struct musycc_group *mg, int c) -{ - struct musycc_dma_data *md; - struct dma_desc *dd, *tmp; - - md = &mg->mg_dma_d[c]; - - splassert(IPL_NET); - ACCOOM_PRINTF(2, ("musycc_list_rx_free\n")); - dd = md->rx_prod; - do { - if (dd == NULL) - break; - if (dd->map->dm_nsegs != 0) { - bus_dmamap_t map = dd->map; - - bus_dmamap_unload(mg->mg_dmat, map); - } - if (dd->mbuf != NULL) { - m_freem(dd->mbuf); - dd->mbuf = NULL; - } - tmp = dd; - dd = dd->nextdesc; - musycc_dma_free(mg, tmp); - } while (dd != md->rx_prod); - md->rx_prod = NULL; - md->rx_cnt = 0; -} - -/* only used by the watchdog timeout */ -void -musycc_reinit_dma(struct musycc_group *mg, int c) -{ - int s; - - s = splnet(); - - musycc_list_tx_free(mg, c); - musycc_list_rx_free(mg, c); - - /* setup tx & rx DMA chain */ - if (musycc_list_tx_init(mg, c, MUSYCC_DMA_SIZE) || - musycc_list_rx_init(mg, c, MUSYCC_DMA_SIZE)) { - log(LOG_ERR, "%s: Failed to malloc memory\n", - mg->mg_channels[c]->cc_ifp->if_xname); - musycc_free_channel(mg, c); - } - splx(s); - - musycc_activate_channel(mg, c); -} - -/* - * Initialize an RX descriptor and attach an mbuf cluster. - */ -int -musycc_newbuf(struct musycc_group *mg, struct dma_desc *c, struct mbuf *m) -{ - struct mbuf *m_new = NULL; - bus_dmamap_t map; - - if (m == NULL) { - MGETHDR(m_new, M_DONTWAIT, MT_DATA); - if (m_new == NULL) - return (ENOBUFS); - - MCLGET(m_new, M_DONTWAIT); - if (!(m_new->m_flags & M_EXT)) { - m_freem(m_new); - return (ENOBUFS); - } - m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; - } else { - m_new = m; - m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; - m_new->m_data = m_new->m_ext.ext_buf; - } - - if (bus_dmamap_load(mg->mg_dmat, mg->mg_rx_sparemap, - mtod(m_new, caddr_t), m_new->m_pkthdr.len, NULL, - BUS_DMA_NOWAIT) != 0) { - ACCOOM_PRINTF(0, ("%s: rx load failed\n", - mg->mg_hdlc->mc_dev.dv_xname)); - m_freem(m_new); - return (ENOBUFS); - } - map = c->map; - c->map = mg->mg_rx_sparemap; - mg->mg_rx_sparemap = map; - - bus_dmamap_sync(mg->mg_dmat, c->map, 0, c->map->dm_mapsize, - BUS_DMASYNC_PREREAD); - - c->mbuf = m_new; - c->data = htole32(c->map->dm_segs[0].ds_addr); - c->status = htole32(MUSYCC_STATUS_NOPOLL | - MUSYCC_STATUS_LEN(m_new->m_pkthdr.len)); - - bus_dmamap_sync(mg->mg_dmat, mg->mg_listmap, - ((caddr_t)c - mg->mg_listkva), sizeof(struct dma_desc), - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - return (0); -} - -/* - * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data - * pointers to the fragment pointers. - */ -int -musycc_encap(struct musycc_group *mg, struct mbuf *m_head, int c) -{ - struct dma_desc *cur, *tmp; - bus_dmamap_t map; - bus_addr_t base; - u_int32_t status; - int i; - - splassert(IPL_NET); - - map = mg->mg_tx_sparemap; - if (bus_dmamap_load_mbuf(mg->mg_dmat, map, m_head, - BUS_DMA_NOWAIT) != 0) { - ACCOOM_PRINTF(0, ("%s: musycc_encap: dmamap_load failed\n", - mg->mg_channels[c]->cc_ifp->if_xname)); - return (ENOBUFS); - } - - cur = mg->mg_dma_d[c].tx_cur; - base = mg->mg_listmap->dm_segs[0].ds_addr; - - if (map->dm_nsegs + mg->mg_dma_d[c].tx_use >= mg->mg_dma_d[c].tx_cnt) { - ACCOOM_PRINTF(1, ("%s: tx out of dma bufs\n", - mg->mg_channels[c]->cc_ifp->if_xname)); - return (ENOBUFS); - } - - i = 0; - while (i < map->dm_nsegs) { - status = /* MUSYCC_STATUS_NOPOLL | */ - MUSYCC_STATUS_LEN(map->dm_segs[i].ds_len); - if (cur != mg->mg_dma_d[c].tx_cur) - status |= MUSYCC_STATUS_OWNER; - - cur->status = htole32(status); - cur->data = htole32(map->dm_segs[i].ds_addr); - - bus_dmamap_sync(mg->mg_dmat, mg->mg_listmap, - ((caddr_t)cur - mg->mg_listkva), sizeof(struct dma_desc), - BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); - - if (++i >= map->dm_nsegs) - break; - cur = cur->nextdesc; - } - - bus_dmamap_sync(mg->mg_dmat, map, 0, map->dm_mapsize, - BUS_DMASYNC_PREWRITE); - - cur->mbuf = m_head; - mg->mg_tx_sparemap = cur->map; - cur->map = map; - cur->status |= htole32(MUSYCC_STATUS_EOM); - tmp = mg->mg_dma_d[c].tx_cur; - mg->mg_dma_d[c].tx_cur = cur->nextdesc; - mg->mg_dma_d[c].tx_use += i; - mg->mg_dma_d[c].tx_pkts++; - - /* - * Last but not least, flag the buffer if the buffer is flagged to - * early, it may happen, that the buffer is already transmitted - * before we changed all relevant variables. - */ - tmp->status |= htole32(MUSYCC_STATUS_OWNER); -#if 0 - /* check for transmited packets NO POLLING mode only */ - /* - * Note: a bug in the HDLC chip seems to make it impossible to use - * no polling mode. - */ - musycc_txeom(mg, c); - if (mg->mg_dma_d[c].tx_pend == tmp) { - /* and restart as needed */ - printf("%s: tx needs kick\n", - mg->mg_channels[c]->cc_ifp->if_xname); - mg->mg_group->tx_headp[c] = htole32(base + - (caddr_t)mg->mg_dma_d[c].tx_pend - mg->mg_listkva); - - musycc_sreq(mg, c, MUSYCC_SREQ_SET(8), MUSYCC_SREQ_TX); - } -#endif - - return (0); -} - - -/* - * API towards the kernel - */ - -/* start transmit of new network buffer */ -void -musycc_start(struct ifnet *ifp) -{ - struct musycc_group *mg; - struct channel_softc *cc; - struct mbuf *m = NULL; - int s; - - cc = ifp->if_softc; - mg = cc->cc_group; - - ACCOOM_PRINTF(3, ("musycc_start\n")); - if (cc->cc_state != CHAN_RUNNING) - return; - if (ifp->if_flags & IFF_OACTIVE) - return; - if (sppp_isempty(ifp)) - return; - - s = splnet(); - while ((m = sppp_pick(ifp)) != NULL) { - if (musycc_encap(mg, m, cc->cc_channel)) { - ifp->if_flags |= IFF_OACTIVE; - break; - } - -#if NBPFILTER > 0 - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_OUT); -#endif - - /* now we are committed to transmit the packet */ - sppp_dequeue(ifp); - } - splx(s); - - /* - * Set a timeout in case the chip goes out to lunch. - */ - ifp->if_timer = 5; - - return; -} - - -/* - * Watchdog/transmission transmit timeout handler. Called when a - * transmission is started on the interface, but no interrupt is - * received before the timeout. This usually indicates that the - * card has wedged for some reason. - */ -void -musycc_watchdog(struct ifnet *ifp) -{ - struct channel_softc *cc = ifp->if_softc; - - log(LOG_ERR, "%s: device timeout\n", cc->cc_ifp->if_xname); - ifp->if_oerrors++; - - musycc_sreq(cc->cc_group, cc->cc_channel, MUSYCC_SREQ_SET(9), - MUSYCC_SREQ_BOTH, EV_WATCHDOG); -} - - -/* - * Interrupt specific functions - */ - -/* - * A frame has been uploaded: pass the resulting mbuf chain up to - * the higher level protocols. - */ -void -musycc_rxeom(struct musycc_group *mg, int channel, int forcekick) -{ - struct mbuf *m; - struct ifnet *ifp; - struct dma_desc *cur_rx, *start_rx; - int total_len = 0, consumed = 0; - u_int32_t rxstat; - - ACCOOM_PRINTF(3, ("musycc_rxeom\n")); - - ifp = mg->mg_channels[channel]->cc_ifp; - - start_rx = cur_rx = mg->mg_dma_d[channel].rx_prod; - if (cur_rx == NULL) - return; /* dma ring got cleared */ - do { - bus_dmamap_sync(mg->mg_dmat, mg->mg_listmap, - ((caddr_t)cur_rx - mg->mg_listkva), - sizeof(struct dma_desc), - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - - rxstat = letoh32(cur_rx->status); - if (!(rxstat & MUSYCC_STATUS_OWNER)) - break; - - m = cur_rx->mbuf; - cur_rx->mbuf = NULL; - total_len = MUSYCC_STATUS_LEN(rxstat); - - - /* - * If an error occurs, update stats, clear the - * status word and leave the mbuf cluster in place: - * it should simply get re-used next time this descriptor - * comes up in the ring. - */ - if (rxstat & MUSYCC_STATUS_ERROR) { - ifp->if_ierrors++; - ACCOOM_PRINTF(1, ("%s: rx error %08x\n", - ifp->if_xname, rxstat)); - musycc_newbuf(mg, cur_rx, m); - cur_rx = cur_rx->nextdesc; - consumed++; - continue; - } - - /* No errors; receive the packet. */ - bus_dmamap_sync(mg->mg_dmat, cur_rx->map, 0, - cur_rx->map->dm_mapsize, BUS_DMASYNC_POSTREAD); - if (musycc_newbuf(mg, cur_rx, NULL) != 0) { - cur_rx = cur_rx->nextdesc; - consumed++; - continue; - } - - cur_rx = cur_rx->nextdesc; - consumed++; - - /* TODO support mbuf chains */ - m->m_pkthdr.rcvif = ifp; - m->m_pkthdr.len = m->m_len = total_len; - ifp->if_ipackets++; - -#if NBPFILTER > 0 - if (ifp->if_bpf) - bpf_mtap(ifp->if_bpf, m, BPF_DIRECTION_IN); -#endif - - /* pass it on. */ - sppp_input(ifp, m); - } while (cur_rx != start_rx); - - mg->mg_dma_d[channel].rx_prod = cur_rx; - - if ((cur_rx == start_rx && consumed) || forcekick) { - /* send SREQ to signal the new buffers */ - ACCOOM_PRINTF(1, ("%s: rx kick, consumed %d pkts\n", - mg->mg_channels[channel]->cc_ifp->if_xname, consumed)); - mg->mg_group->rx_headp[channel] = htole32( - mg->mg_listmap->dm_segs[0].ds_addr + - (caddr_t)cur_rx - mg->mg_listkva); - musycc_sreq(mg, channel, MUSYCC_SREQ_SET(8), - MUSYCC_SREQ_RX, EV_NULL); - } -} - -/* - * A frame was downloaded to the chip. It's safe for us to clean up - * the list buffers. - */ -void -musycc_txeom(struct musycc_group *mg, int channel, int forcekick) -{ - struct dma_desc *dd, *dd_pend; - struct ifnet *ifp; - - ACCOOM_PRINTF(3, ("musycc_txeom\n")); - - ifp = mg->mg_channels[channel]->cc_ifp; - /* Clear the watchdog timer. */ - ifp->if_timer = 0; - - /* - * Go through our tx list and free mbufs for those - * frames that have been transmitted. - */ - for (dd = mg->mg_dma_d[channel].tx_pend; - dd != mg->mg_dma_d[channel].tx_cur; - dd = dd->nextdesc) { - bus_dmamap_sync(mg->mg_dmat, mg->mg_listmap, - ((caddr_t)dd - mg->mg_listkva), sizeof(struct dma_desc), - BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); - - if (letoh32(dd->status) & MUSYCC_STATUS_OWNER) - /* musycc still owns this descriptor */ - break; - - mg->mg_dma_d[channel].tx_use--; - - dd->status = 0; /* reinit dma status flags */ - /* dd->status |= MUSYCC_STATUS_NOPOLL; *//* disable polling */ - - if (dd->map->dm_nsegs != 0) { - bus_dmamap_sync(mg->mg_dmat, dd->map, 0, - dd->map->dm_mapsize, BUS_DMASYNC_POSTWRITE); - bus_dmamap_unload(mg->mg_dmat, dd->map); - } - if (dd->mbuf != NULL) { - m_freem(dd->mbuf); - dd->mbuf = NULL; - mg->mg_dma_d[channel].tx_pkts--; - ifp->if_opackets++; - } - } - - dd_pend = mg->mg_dma_d[channel].tx_pend; - mg->mg_dma_d[channel].tx_pend = dd; - - if (ifp->if_flags & IFF_OACTIVE && dd_pend != dd) { - ifp->if_flags &= ~IFF_OACTIVE; - musycc_start(ifp); - } - - if (forcekick) { - /* restart */ - ACCOOM_PRINTF(1, ("%s: tx kick forced\n", - mg->mg_channels[channel]->cc_ifp->if_xname)); - mg->mg_group->tx_headp[channel] = - htole32(mg->mg_listmap->dm_segs[0].ds_addr + - (caddr_t)mg->mg_dma_d[channel].tx_pend - mg->mg_listkva); - - musycc_sreq(mg, channel, MUSYCC_SREQ_SET(8), MUSYCC_SREQ_TX, - EV_NULL); - } -} - -int -musycc_intr(void *arg) -{ - struct musycc_softc *mc = arg; - struct musycc_group *mg; - struct ifnet *ifp; - u_int32_t intstatus, id; - int i, n, chan; - - intstatus = bus_space_read_4(mc->mc_st, mc->mc_sh, MUSYCC_INTRSTATUS); - - if (intstatus & MUSYCC_INTCNT_MASK) { - bus_dmamap_sync(mc->mc_dmat, mc->mc_intrmap, - offsetof(struct musycc_intdesc, md_intrq[0]), - MUSYCC_INTLEN * sizeof(u_int32_t), BUS_DMASYNC_POSTREAD); - - ACCOOM_PRINTF(4, ("%s: interrupt status %08x\n", - mc->mc_dev.dv_xname, intstatus)); - - n = MUSYCC_NEXTINT_GET(intstatus); - for (i = 0; i < (intstatus & MUSYCC_INTCNT_MASK); i++) { - id = letoh32(mc->mc_intrd->md_intrq[(n + i) % - MUSYCC_INTLEN]); - chan = MUSYCC_INTD_CHAN(id); - mg = &mc->mc_groups[MUSYCC_INTD_GRP(id)]; - - ACCOOM_PRINTF(4, ("%s: interrupt %s\n", - mc->mc_dev.dv_xname, musycc_intr_print(id))); - - if (id & MUSYCC_INTD_ILOST) - ACCOOM_PRINTF(0, ("%s: interrupt lost\n", - mc->mc_dev.dv_xname)); - - switch (MUSYCC_INTD_EVENT(id)) { - case MUSYCC_INTEV_NONE: - break; - case MUSYCC_INTEV_SACK: - musycc_state_engine(mg, chan, - mg->mg_sreq[mg->mg_sreqpend].event); - mg->mg_sreqpend = - (mg->mg_sreqpend + 1) & MUSYCC_SREQMASK; - if (mg->mg_sreqpend != mg->mg_sreqprod) - musycc_kick(mg); - break; - case MUSYCC_INTEV_EOM: - case MUSYCC_INTEV_EOB: - if (id & MUSYCC_INTD_DIR) - musycc_txeom(mg, chan, 0); - else - musycc_rxeom(mg, chan, 0); - break; - default: - ACCOOM_PRINTF(0, ("%s: unhandled event: %s\n", - mc->mc_dev.dv_xname, - musycc_intr_print(id))); - break; - } - switch (MUSYCC_INTD_ERROR(id)) { - case MUSYCC_INTERR_NONE: - break; - case MUSYCC_INTERR_COFA: - if ((id & MUSYCC_INTD_DIR) == 0) - /* ignore COFA for RX side */ - break; - if (mg->mg_channels[chan]->cc_state != - CHAN_RUNNING) { - /* - * ignore COFA for TX side if card is - * not running - */ - break; - } - ACCOOM_PRINTF(0, ("%s: error: %s\n", - mc->mc_dev.dv_xname, - musycc_intr_print(id))); -#if 0 - /* digest already transmitted packets */ - musycc_txeom(mg, chan); - - /* adjust head pointer */ - musycc_dump_dma(mg); - mg->mg_group->tx_headp[chan] = - htole32(mg->mg_listmap->dm_segs[0].ds_addr + - (caddr_t)mg->mg_dma_d[chan].tx_pend - - mg->mg_listkva); - musycc_dump_dma(mg); - - musycc_sreq(mg, chan, MUSYCC_SREQ_SET(8), - MUSYCC_SREQ_TX, CHAN_RUNNING); -#endif - break; - case MUSYCC_INTERR_BUFF: - /* - * log event as this should not happen, - * indicates PCI bus congestion - */ - log(LOG_ERR, "%s: internal FIFO %s\n", - mg->mg_channels[chan]->cc_ifp->if_xname, - id & MUSYCC_INTD_DIR ? "underflow" : - "overflow"); - - /* digest queue and restarting dma engine */ - ifp = mg->mg_channels[chan]->cc_ifp; - if (id & MUSYCC_INTD_DIR) { - ifp->if_oerrors++; - musycc_txeom(mg, chan, 1); - } else { - ifp->if_ierrors++; - musycc_rxeom(mg, chan, 1); - } - break; - case MUSYCC_INTERR_ONR: - ACCOOM_PRINTF(0, ("%s: error: %s\n", - mc->mc_dev.dv_xname, - musycc_intr_print(id))); - - /* digest queue and restarting dma engine */ - ifp = mg->mg_channels[chan]->cc_ifp; - if (id & MUSYCC_INTD_DIR) { - ifp->if_oerrors++; - musycc_txeom(mg, chan, 1); - } else { - ifp->if_ierrors++; - musycc_rxeom(mg, chan, 1); - } - break; - case MUSYCC_INTERR_OOF: - /* ignore */ - break; - default: - ACCOOM_PRINTF(0, ("%s: unhandled error: %s\n", - mc->mc_dev.dv_xname, - musycc_intr_print(id))); - break; - } - } - bus_space_write_4(mc->mc_st, mc->mc_sh, MUSYCC_INTRSTATUS, - MUSYCC_NEXTINT_SET((n + i) % MUSYCC_INTLEN)); - bus_space_barrier(mc->mc_st, mc->mc_sh, MUSYCC_INTRSTATUS, - sizeof(u_int32_t), BUS_SPACE_BARRIER_WRITE); - return (1); - } else - return (0); -} - -void -musycc_kick(struct musycc_group *mg) -{ - - bus_dmamap_sync(mg->mg_dmat, mg->mg_hdlc->mc_cfgmap, - MUSYCC_GROUPBASE(mg->mg_gnum), sizeof(struct musycc_grpdesc), - BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); - - ACCOOM_PRINTF(4, ("musycc_kick: group %d sreq[%d] req %08x\n", - mg->mg_gnum, mg->mg_sreqpend, mg->mg_sreq[mg->mg_sreqpend].sreq)); - - bus_space_write_4(mg->mg_hdlc->mc_st, mg->mg_hdlc->mc_sh, - MUSYCC_SERREQ(mg->mg_gnum), mg->mg_sreq[mg->mg_sreqpend].sreq); - bus_space_barrier(mg->mg_hdlc->mc_st, mg->mg_hdlc->mc_sh, - MUSYCC_SERREQ(mg->mg_gnum), sizeof(u_int32_t), - BUS_SPACE_BARRIER_WRITE); -} - -void -musycc_sreq(struct musycc_group *mg, int channel, u_int32_t req, int dir, - enum musycc_event event) -{ -#define MUSYCC_SREQINC(x, y) \ - do { \ - (x) = ((x) + 1) & MUSYCC_SREQMASK; \ - if (x == y) \ - panic("%s: sreq queue overflow", \ - mg->mg_hdlc->mc_dev.dv_xname); \ - } while (0) - - struct timeval tv; - int needskick; - - needskick = (mg->mg_sreqpend == mg->mg_sreqprod); - getmicrouptime(&tv); - - ACCOOM_PRINTF(4, ("musycc_sreq: g# %d c# %d req %x dir %x\n", - mg->mg_gnum, channel, req, dir)); - - if (dir & MUSYCC_SREQ_RX) { - req &= ~MUSYCC_SREQ_TXDIR & ~MUSYCC_SREQ_MASK; - req |= MUSYCC_SREQ_CHSET(channel); - mg->mg_sreq[mg->mg_sreqprod].sreq = req; - mg->mg_sreq[mg->mg_sreqprod].timeout = tv.tv_sec + - MUSYCC_SREQTIMEOUT; - if (dir == MUSYCC_SREQ_RX) - mg->mg_sreq[mg->mg_sreqprod].event = event; - else - mg->mg_sreq[mg->mg_sreqprod].event = EV_NULL; - MUSYCC_SREQINC(mg->mg_sreqprod, mg->mg_sreqpend); - } - if (dir & MUSYCC_SREQ_TX) { - req &= ~MUSYCC_SREQ_MASK; - req |= MUSYCC_SREQ_TXDIR; - req |= MUSYCC_SREQ_CHSET(channel); - mg->mg_sreq[mg->mg_sreqprod].timeout = tv.tv_sec + - MUSYCC_SREQTIMEOUT; - mg->mg_sreq[mg->mg_sreqprod].sreq = req; - mg->mg_sreq[mg->mg_sreqprod].event = event; - MUSYCC_SREQINC(mg->mg_sreqprod, mg->mg_sreqpend); - } - - if (needskick) - musycc_kick(mg); - -#undef MUSYCC_SREQINC -} - -void -musycc_tick(struct channel_softc *cc) -{ - struct musycc_group *mg = cc->cc_group; - struct timeval tv; - - if (mg->mg_sreqpend == mg->mg_sreqprod) - return; - - getmicrouptime(&tv); - if (mg->mg_sreq[mg->mg_sreqpend].timeout < tv.tv_sec) { - log(LOG_ERR, "%s: service request timeout\n", - cc->cc_ifp->if_xname); - mg->mg_sreqpend++; - /* digest all timed out SREQ */ - while (mg->mg_sreq[mg->mg_sreqpend].timeout < tv.tv_sec && - mg->mg_sreqpend != mg->mg_sreqprod) - mg->mg_sreqpend++; - - if (mg->mg_sreqpend != mg->mg_sreqprod) - musycc_kick(mg); - } -} - -/* - * Extension Bus API - */ -int -ebus_intr(void *arg) -{ - struct musycc_softc *sc = arg; - - printf("%s: interrupt\n", sc->mc_dev.dv_xname); - return (1); -} - -int -ebus_attach_device(struct ebus_dev *e, struct musycc_softc *mc, - bus_size_t offset, bus_size_t size) -{ - struct musycc_softc *ec = mc->mc_other; - - e->base = offset << 2; - e->size = size; - e->st = ec->mc_st; - return (bus_space_subregion(ec->mc_st, ec->mc_sh, offset << 2, - size, &e->sh)); -} - -u_int8_t -ebus_read(struct ebus_dev *e, bus_size_t offset) -{ - u_int8_t value; - - value = bus_space_read_1(e->st, e->sh, offset << 2); - bus_space_barrier(e->st, e->sh, 0, e->size, - BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); - return (value); -} - -void -ebus_write(struct ebus_dev *e, bus_size_t offset, u_int8_t value) -{ - bus_space_write_1(e->st, e->sh, offset << 2, value); - bus_space_barrier(e->st, e->sh, 0, e->size, - BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); -} - -void -ebus_read_buf(struct ebus_dev *rom, bus_size_t offset, void *buf, size_t size) -{ - u_int8_t *b = buf; - size_t i; - - for (i = 0; i < size; i++) - b[i] = ebus_read(rom, offset + i); -} - -void -ebus_set_led(struct channel_softc *cc, int on, u_int8_t value) -{ - struct musycc_softc *sc = cc->cc_group->mg_hdlc->mc_other; - - value &= MUSYCC_LED_MASK; /* don't write to other ports led */ - value <<= cc->cc_group->mg_gnum * 2; - - if (on) - sc->mc_ledstate |= value; - else - sc->mc_ledstate &= ~value; - - bus_space_write_1(sc->mc_st, sc->mc_sh, sc->mc_ledbase, - sc->mc_ledstate); - bus_space_barrier(sc->mc_st, sc->mc_sh, sc->mc_ledbase, 1, - BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); -} - -/* - * Channel API - */ - -void -musycc_attach_sppp(struct channel_softc *cc, - int (*if_ioctl)(struct ifnet *, u_long, caddr_t)) -{ - struct ifnet *ifp; - - ifp = &cc->cc_ppp.pp_if; - cc->cc_ifp = ifp; - - IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); - IFQ_SET_READY(&ifp->if_snd); - ifp->if_mtu = PP_MTU; - ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST /* | IFF_SIMPLEX */; - cc->cc_ppp.pp_flags |= PP_CISCO; - cc->cc_ppp.pp_flags |= PP_KEEPALIVE; - cc->cc_ppp.pp_framebytes = 3; - - ifp->if_ioctl = if_ioctl; - ifp->if_start = musycc_start; - ifp->if_watchdog = musycc_watchdog; - - if_attach(ifp); - if_alloc_sadl(ifp); - sppp_attach(ifp); -#if NBPFILTER > 0 - bpfattach(&ifp->if_bpf, ifp, DLT_PPP, PPP_HEADER_LEN); -#endif /* NBPFILTER > 0 */ - -} - -struct channel_softc * -musycc_channel_create(const char *name, u_int8_t locked) -{ - struct channel_softc *cc; - - cc = malloc(sizeof(*cc), M_DEVBUF, M_NOWAIT | M_ZERO); - if (!cc) - return (NULL); - - cc->cc_state = CHAN_FLOAT; - cc->cc_locked = locked; - - /* set default timeslot map for E1 */ - cc->cc_tslots = 0xfffffffe; /* all but timeslot 0 */ - strlcpy(cc->cc_ppp.pp_if.if_xname, name, - sizeof(cc->cc_ppp.pp_if.if_xname)); - - cc->cc_ppp.pp_if.if_softc = cc; - - return (cc); -} - -int -musycc_channel_attach(struct musycc_softc *mc, struct channel_softc *cc, - struct device *dev, u_int8_t gnum) -{ - struct musycc_group *mg; - int i; - - if (cc->cc_state != CHAN_FLOAT) - return (-1); /* already attached */ - - if (gnum >= mc->mc_ngroups) { - ACCOOM_PRINTF(0, ("%s: %s tries to attach to nonexistent group", - mc->mc_dev.dv_xname, cc->cc_ifp->if_xname)); - return (-1); - } - - mg = &mc->mc_groups[gnum]; - for (i = 0; i < MUSYCC_NUMCHAN; i++) - if (mg->mg_channels[i] == NULL) { - mg->mg_channels[i] = cc; - cc->cc_state = CHAN_IDLE; - cc->cc_group = mg; - cc->cc_channel = i; - cc->cc_parent = dev; - return (i); - } - return (-1); -} - -void -musycc_channel_detach(struct ifnet *ifp) -{ - struct channel_softc *cc = ifp->if_softc; - - if (cc->cc_state != CHAN_FLOAT) { - musycc_free_channel(cc->cc_group, cc->cc_channel); - cc->cc_group->mg_channels[cc->cc_channel] = NULL; - } - - if_detach(ifp); -} - -#ifdef ACCOOM_DEBUG -const char *musycc_events[] = { - "NONE", "SACK", "EOB", "EOM", "EOP", "CHABT", "CHIC", "FREC", - "SINC", "SDEC", "SFILT", "RFU", "RFU", "RFU", "RFU", "RFU" -}; -const char *musycc_errors[] = { - "NONE", "BUFF", "COFA", "ONR", "PROT", "RFU", "RFU", "RFU", - "OOF", "FCS", "ALIGN", "ABT", "LNG", "SHT", "SUERR", "PERR" -}; -const char *mu_proto[] = { - "trans", "ss7", "hdlc16", "hdlc32", "rsvd4", "rsvd5", "rsvd6", "rsvd7" -}; -const char *mu_mode[] = { - "t1", "e1", "2*e1", "4*e1", "n64", "rsvd5", "rsvd6", "rsvd7" -}; - -char musycc_intrbuf[48]; - -char * -musycc_intr_print(u_int32_t id) -{ - snprintf(musycc_intrbuf, sizeof(musycc_intrbuf), - "ev %s er %s grp %d chan %d dir %s", - musycc_events[MUSYCC_INTD_EVENT(id)], - musycc_errors[MUSYCC_INTD_ERROR(id)], - MUSYCC_INTD_GRP(id), MUSYCC_INTD_CHAN(id), - id & MUSYCC_INTD_DIR ? "T" : "R"); - return (musycc_intrbuf); -} - -void -musycc_dump_group(int level, struct musycc_group *mg) -{ - struct musycc_grpdesc *md = mg->mg_group; - u_int32_t d; - int i; - - if (level > accoom_debug) - return; - - printf("%s: dumping group %d\n", - mg->mg_hdlc->mc_dev.dv_xname, mg->mg_gnum); - printf("===========================================================\n"); - printf("global conf: %08x\n", letoh32(md->global_conf)); - d = letoh32(md->group_conf); - printf("group conf: [%08x] %s %s %s int %s%s inhib BSD %s%s poll %d\n", - d, - d & MUSYCC_GRCFG_TXENBL ? "TX" : "", - d & MUSYCC_GRCFG_RXENBL ? "RX" : "", - d & MUSYCC_GRCFG_SUBDSBL ? "" : "SUB", - d & MUSYCC_GRCFG_MSKOOF ? "" : "O", - d & MUSYCC_GRCFG_MSKCOFA ? "" : "C", - d & MUSYCC_GRCFG_INHTBSD ? "TX" : "", - d & MUSYCC_GRCFG_INHRBSD ? "RX" : "", - (d & MUSYCC_GRCFG_POLL64) == MUSYCC_GRCFG_POLL64 ? 64 : - d & MUSYCC_GRCFG_POLL32 ? 32 : - d & MUSYCC_GRCFG_POLL16 ? 16 : 1); - d = letoh32(md->port_conf); - printf("port conf: [%08x] %s %s %s %s %s %s %s\n", d, - mu_mode[d & MUSYCC_PORT_MODEMASK], - d & MUSYCC_PORT_TDAT_EDGE ? "TXE" : "!TXE", - d & MUSYCC_PORT_TSYNC_EDGE ? "TXS" : "!TXS", - d & MUSYCC_PORT_RDAT_EDGE ? "RXE" : "!RXE", - d & MUSYCC_PORT_RSYNC_EDGE ? "RXS" : "!RXS", - d & MUSYCC_PORT_ROOF_EDGE ? "ROOF" : "!ROOF", - d & MUSYCC_PORT_TRITX ? "!tri-state" : "tri-state"); - printf("message len 1: %d 2: %d\n", - letoh32(md->msglen_conf) & MUSYCC_MAXFRM_MASK, - (letoh32(md->msglen_conf) >> MUSYCC_MAXFRM2_SHIFT) & - MUSYCC_MAXFRM_MASK); - printf("interrupt queue %x len %d\n", letoh32(md->int_queuep), - letoh32(md->int_queuelen)); - printf("memory protection %x\n", letoh32(md->memprot)); - printf("===========================================================\n"); - printf("Timeslot Map:TX\t\tRX\n"); - for (i = 0; i < 128; i++) { - if (md->tx_tsmap[i] & MUSYCC_TSLOT_ENABLED) - printf("%d: %s%s%s[%02d]\t\t", i, - md->tx_tsmap[i] & MUSYCC_TSLOT_ENABLED ? "C" : " ", - md->tx_tsmap[i] & MUSYCC_TSLOT_SUB ? "S" : " ", - md->tx_tsmap[i] & MUSYCC_TSLOT_56K ? "*" : " ", - MUSYCC_TSLOT_CHAN(md->tx_tsmap[i])); - else if (md->rx_tsmap[i] & MUSYCC_TSLOT_ENABLED) - printf("%d: \t\t", i); - if (md->rx_tsmap[i] & MUSYCC_TSLOT_ENABLED) - printf("%s%s%s[%02d]\n", - md->rx_tsmap[i] & MUSYCC_TSLOT_ENABLED ? "C" : " ", - md->rx_tsmap[i] & MUSYCC_TSLOT_SUB ? "S" : " ", - md->rx_tsmap[i] & MUSYCC_TSLOT_56K ? "*" : " ", - MUSYCC_TSLOT_CHAN(md->rx_tsmap[i])); - else - printf("\n"); - } - printf("===========================================================\n"); - printf("Channel config:\nTX\t\t\tRX\n"); - for (i = 0; i < 32; i++) - if (md->tx_cconf[i] != 0) { - d = letoh32(md->tx_cconf[i]); - printf("%s%s%s%s%s%s%s %s [%x]\t", - d & MUSYCC_CHAN_MSKBUFF ? "B" : " ", - d & MUSYCC_CHAN_MSKEOM ? "E" : " ", - d & MUSYCC_CHAN_MSKMSG ? "M" : " ", - d & MUSYCC_CHAN_MSKIDLE ? "I" : " ", - d & MUSYCC_CHAN_FCS ? "F" : "", - d & MUSYCC_CHAN_MAXLEN1 ? "1" : "", - d & MUSYCC_CHAN_MAXLEN2 ? "2" : "", - mu_proto[MUSYCC_CHAN_PROTO_GET(d)], - d); - d = letoh32(md->rx_cconf[i]); - printf("%s%s%s%s%s%s%s %s [%x]\n", - d & MUSYCC_CHAN_MSKBUFF ? "B" : " ", - d & MUSYCC_CHAN_MSKEOM ? "E" : " ", - d & MUSYCC_CHAN_MSKMSG ? "M" : " ", - d & MUSYCC_CHAN_MSKIDLE ? "I" : " ", - d & MUSYCC_CHAN_FCS ? "F" : "", - d & MUSYCC_CHAN_MAXLEN1 ? "1" : "", - d & MUSYCC_CHAN_MAXLEN2 ? "2" : "", - mu_proto[MUSYCC_CHAN_PROTO_GET(d)], - d); - } - printf("===========================================================\n"); - musycc_dump_dma(level, mg, 0); -} - -void -musycc_dump_desc(int level, struct musycc_group *mg) -{ -#define READ4(x) \ - bus_space_read_4(mg->mg_hdlc->mc_st, mg->mg_hdlc->mc_sh, \ - MUSYCC_GROUPBASE(mg->mg_gnum) + (x)) - u_int32_t w; - u_int8_t c1, c2; - int i; - - if (level > accoom_debug) - return; - - printf("%s: dumping descriptor %d at %p kva %08x + %x dma %08x\n", - mg->mg_hdlc->mc_dev.dv_xname, mg->mg_gnum, mg->mg_group, - mg->mg_hdlc->mc_cfgmap->dm_segs[0].ds_addr, - MUSYCC_GROUPBASE(mg->mg_gnum), READ4(0)); - printf("===========================================================\n"); - printf("global conf: %08x\n", READ4(MUSYCC_GLOBALCONF)); - w = READ4(0x060c); - printf("group conf: [%08x] %s %s %s int %s%s inhib BSD %s%s poll %d\n", - w, w & MUSYCC_GRCFG_TXENBL ? "TX" : "", - w & MUSYCC_GRCFG_RXENBL ? "RX" : "", - w & MUSYCC_GRCFG_SUBDSBL ? "" : "SUB", - w & MUSYCC_GRCFG_MSKOOF ? "" : "O", - w & MUSYCC_GRCFG_MSKCOFA ? "" : "C", - w & MUSYCC_GRCFG_INHTBSD ? "TX" : "", - w & MUSYCC_GRCFG_INHRBSD ? "RX" : "", - (w & MUSYCC_GRCFG_POLL64) == MUSYCC_GRCFG_POLL64 ? 64 : - w & MUSYCC_GRCFG_POLL32 ? 32 : - w & MUSYCC_GRCFG_POLL16 ? 16 : 1); - w = READ4(0x0618); - printf("port conf: [%08x] %s %s %s %s %s %s %s\n", w, - mu_mode[w & MUSYCC_PORT_MODEMASK], - w & MUSYCC_PORT_TDAT_EDGE ? "TXE" : "!TXE", - w & MUSYCC_PORT_TSYNC_EDGE ? "TXS" : "!TXS", - w & MUSYCC_PORT_RDAT_EDGE ? "RXE" : "!RXE", - w & MUSYCC_PORT_RSYNC_EDGE ? "RXS" : "!RXS", - w & MUSYCC_PORT_ROOF_EDGE ? "ROOF" : "!ROOF", - w & MUSYCC_PORT_TRITX ? "!tri-state" : "tri-state"); - w = READ4(0x0614); - printf("message len 1: %d 2: %d\n", - w & MUSYCC_MAXFRM_MASK, - (w >> MUSYCC_MAXFRM2_SHIFT) & MUSYCC_MAXFRM_MASK); - printf("interrupt queue %x len %d\n", READ4(0x0604), READ4(0x0608)); - printf("memory protection %x\n", READ4(0x0610)); - printf("===========================================================\n"); - printf("Timeslot Map:TX\t\tRX\n"); - for (i = 0; i < 128; i++) { - c1 = bus_space_read_1(mg->mg_hdlc->mc_st, mg->mg_hdlc->mc_sh, - MUSYCC_GROUPBASE(mg->mg_gnum) + 0x0200 + i); - c2 = bus_space_read_1(mg->mg_hdlc->mc_st, mg->mg_hdlc->mc_sh, - MUSYCC_GROUPBASE(mg->mg_gnum) + 0x0400 + i); - if (c1 & MUSYCC_TSLOT_ENABLED) - printf("%d: %s%s%s[%02d]\t\t", i, - c1 & MUSYCC_TSLOT_ENABLED ? "C" : " ", - c1 & MUSYCC_TSLOT_SUB ? "S" : " ", - c1 & MUSYCC_TSLOT_56K ? "*" : " ", - MUSYCC_TSLOT_CHAN(c1)); - else if (c2 & MUSYCC_TSLOT_ENABLED) - printf("%d: \t\t", i); - if (c2 & MUSYCC_TSLOT_ENABLED) - printf("%s%s%s[%02d]\n", - c2 & MUSYCC_TSLOT_ENABLED ? "C" : " ", - c2 & MUSYCC_TSLOT_SUB ? "S" : " ", - c2 & MUSYCC_TSLOT_56K ? "*" : " ", - MUSYCC_TSLOT_CHAN(c2)); - else - printf("\n"); - } - printf("===========================================================\n"); - printf("Channel config:\nTX\t\t\t\tRX\n"); - for (i = 0; i < 32; i++) { - w = READ4(0x0380 + i * 4); - if (w != 0) { - printf("%s%s%s%s%s%s%s %s [%08x]\t", - w & MUSYCC_CHAN_MSKBUFF ? "B" : " ", - w & MUSYCC_CHAN_MSKEOM ? "E" : " ", - w & MUSYCC_CHAN_MSKMSG ? "M" : " ", - w & MUSYCC_CHAN_MSKIDLE ? "I" : " ", - w & MUSYCC_CHAN_FCS ? "F" : "", - w & MUSYCC_CHAN_MAXLEN1 ? "1" : "", - w & MUSYCC_CHAN_MAXLEN2 ? "2" : "", - mu_proto[MUSYCC_CHAN_PROTO_GET(w)], - w); - w = READ4(0x0580 + i * 4); - printf("%s%s%s%s%s%s%s %s [%08x]\n", - w & MUSYCC_CHAN_MSKBUFF ? "B" : " ", - w & MUSYCC_CHAN_MSKEOM ? "E" : " ", - w & MUSYCC_CHAN_MSKMSG ? "M" : " ", - w & MUSYCC_CHAN_MSKIDLE ? "I" : " ", - w & MUSYCC_CHAN_FCS ? "F" : "", - w & MUSYCC_CHAN_MAXLEN1 ? "1" : "", - w & MUSYCC_CHAN_MAXLEN2 ? "2" : "", - mu_proto[MUSYCC_CHAN_PROTO_GET(w)], - w); - } - } - printf("===========================================================\n"); - musycc_dump_dma(level, mg, 0); - -} - -void -musycc_dump_dma(int level, struct musycc_group *mg, int dir) -{ - struct musycc_grpdesc *md = mg->mg_group; - struct dma_desc *dd; - bus_addr_t base, addr; - int i; - - if (level > accoom_debug) - return; - - printf("DMA Pointers:\n%8s %8s %8s %8s\n", - "tx head", "tx msg", "rx head", "rx msg"); - for (i = 0; i < 32; i++) { - if (md->tx_headp[i] == 0 && md->rx_headp[i] == 0) - continue; - printf("%08x %08x %08x %08x\n", - md->tx_headp[i], md->tx_msgp[i], - md->rx_headp[i], md->rx_msgp[i]); - } - - base = mg->mg_listmap->dm_segs[0].ds_addr; - for (i = 0; dir & MUSYCC_SREQ_TX && i < 32; i++) { - if (md->tx_headp[i] == 0) - continue; - - printf("==================================================\n"); - printf("TX DMA Ring for channel %d\n", i); - printf("pend: %p cur: %p cnt: %d use: %d pkgs: %d\n", - mg->mg_dma_d[i].tx_pend, mg->mg_dma_d[i].tx_cur, - mg->mg_dma_d[i].tx_cnt, mg->mg_dma_d[i].tx_use, - mg->mg_dma_d[i].tx_pkts); - printf(" %10s %8s %8s %8s %8s %10s\n", - "addr", "paddr", "next", "status", "data", "mbuf"); - dd = mg->mg_dma_d[i].tx_pend; - do { - addr = htole32(base + ((caddr_t)dd - mg->mg_listkva)); - printf("%s %p %08x %08x %08x %08x %p\n", - dd == mg->mg_dma_d[i].tx_pend ? ">" : - dd == mg->mg_dma_d[i].tx_cur ? "*" : " ", - dd, addr, dd->next, dd->status, - dd->data, dd->mbuf); - dd = dd->nextdesc; - } while (dd != mg->mg_dma_d[i].tx_pend); - } - for (i = 0; dir & MUSYCC_SREQ_RX && i < 32; i++) { - if (md->rx_headp[i] == 0) - continue; - - printf("==================================================\n"); - printf("RX DMA Ring for channel %d\n", i); - printf("prod: %p cnt: %d\n", - mg->mg_dma_d[i].rx_prod, mg->mg_dma_d[i].rx_cnt); - printf(" %8s %8s %8s %8s %10s\n", - "addr", "paddr", "next", "status", "data", "mbuf"); - dd = mg->mg_dma_d[i].rx_prod; - do { - addr = htole32(base + ((caddr_t)dd - mg->mg_listkva)); - printf("%p %08x %08x %08x %08x %p\n", dd, addr, - dd->next, dd->status, dd->data, dd->mbuf); - dd = dd->nextdesc; - } while (dd != mg->mg_dma_d[i].rx_prod); - } -} -#endif diff --git a/sys/dev/pci/musycc_obsd.c b/sys/dev/pci/musycc_obsd.c deleted file mode 100644 index 44cbe406290..00000000000 --- a/sys/dev/pci/musycc_obsd.c +++ /dev/null @@ -1,287 +0,0 @@ -/* $OpenBSD: musycc_obsd.c,v 1.11 2013/07/04 16:52:22 sf Exp $ */ - -/* - * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Claudio Jeker <jeker@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ - -#include <sys/param.h> -#include <sys/types.h> - -#include <sys/device.h> -#include <sys/malloc.h> -#include <sys/systm.h> -#include <sys/socket.h> - -#include <machine/cpu.h> -#include <machine/bus.h> -#include <machine/intr.h> - -#include <net/if.h> -#include <net/if_media.h> -#include <net/if_sppp.h> - -#include <dev/pci/musyccvar.h> -#include <dev/pci/musyccreg.h> - -#include <dev/pci/pcivar.h> -#include <dev/pci/pcireg.h> -#include <dev/pci/pcidevs.h> - -int musycc_match(struct device *, void *, void *); -void musycc_softc_attach(struct device *, struct device *, void *); -void musycc_ebus_attach(struct device *, struct musycc_softc *, - struct pci_attach_args *); -int musycc_ebus_print(void *, const char *); - -struct cfattach musycc_ca = { - sizeof(struct musycc_softc), musycc_match, musycc_softc_attach -}; - -struct cfdriver musycc_cd = { - NULL, "musycc", DV_DULL -}; - -SLIST_HEAD(, musycc_softc) msc_list = SLIST_HEAD_INITIALIZER(msc_list); - -const struct pci_matchid musycc_pci_devices[] = { - { PCI_VENDOR_CONEXANT, PCI_PRODUCT_CONEXANT_MUSYCC8478 }, - { PCI_VENDOR_CONEXANT, PCI_PRODUCT_CONEXANT_MUSYCC8474 }, - { PCI_VENDOR_CONEXANT, PCI_PRODUCT_CONEXANT_MUSYCC8472 }, - { PCI_VENDOR_CONEXANT, PCI_PRODUCT_CONEXANT_MUSYCC8471 } -}; - -int -musycc_match(struct device *parent, void *match, void *aux) -{ - return (pci_matchbyid((struct pci_attach_args *)aux, musycc_pci_devices, - nitems(musycc_pci_devices))); -} - -void -musycc_softc_attach(struct device *parent, struct device *self, void *aux) -{ - struct musycc_softc *sc = (struct musycc_softc *)self; - struct pci_attach_args *pa = aux; - pci_chipset_tag_t pc = pa->pa_pc; - pci_intr_handle_t ih; - const char *intrstr = NULL; - - if (pci_mapreg_map(pa, MUSYCC_PCI_BAR, - PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 0, - &sc->mc_st, &sc->mc_sh, NULL, &sc->mc_iosize, 0)) { - printf(": can't map mem space\n"); - return; - } - sc->mc_dmat = pa->pa_dmat; - - switch (PCI_PRODUCT(pa->pa_id)) { - case PCI_PRODUCT_CONEXANT_MUSYCC8478: - sc->mc_ngroups = 8; - sc->mc_nports = 8; - break; - case PCI_PRODUCT_CONEXANT_MUSYCC8474: - sc->mc_ngroups = 4; - sc->mc_nports = 4; - break; - case PCI_PRODUCT_CONEXANT_MUSYCC8472: - sc->mc_ngroups = 2; - sc->mc_nports = 2; - break; - case PCI_PRODUCT_CONEXANT_MUSYCC8471: - sc->mc_ngroups = 1; - sc->mc_nports = 1; - break; - } - - if (pa->pa_function == 1) - return (musycc_ebus_attach(parent, sc, pa)); - - sc->bus = parent->dv_unit; - sc->device = pa->pa_device; - SLIST_INSERT_HEAD(&msc_list, sc, list); - - /* - * Allocate our interrupt. - */ - if (pci_intr_map(pa, &ih)) { - printf(": couldn't map interrupt\n"); - bus_space_unmap(sc->mc_st, sc->mc_sh, sc->mc_iosize); - return; - } - - intrstr = pci_intr_string(pc, ih); - sc->mc_ih = pci_intr_establish(pc, ih, IPL_NET, musycc_intr, sc, - self->dv_xname); - if (sc->mc_ih == NULL) { - printf(": couldn't establish interrupt"); - if (intrstr != NULL) - printf(" at %s", intrstr); - printf("\n"); - bus_space_unmap(sc->mc_st, sc->mc_sh, sc->mc_iosize); - return; - } - - printf(": %s\n", intrstr); - - /* soft reset device */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_SERREQ(0), - MUSYCC_SREQ_SET(1)); - bus_space_barrier(sc->mc_st, sc->mc_sh, MUSYCC_SERREQ(0), - sizeof(u_int32_t), BUS_SPACE_BARRIER_WRITE); - - /* - * preload global configuration: set EBUS to sane defaults - * so that the ROM access will work. - * intel mode, elapse = 3, blapse = 3, alapse = 3, disable INTB - */ - sc->mc_global_conf = MUSYCC_CONF_MPUSEL | MUSYCC_CONF_ECKEN | - MUSYCC_CONF_ELAPSE_SET(3) | MUSYCC_CONF_ALAPSE_SET(3) | - MUSYCC_CONF_BLAPSE_SET(3) | MUSYCC_CONF_INTB; - - /* Dual Address Cycle Base Pointer */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_DACB_PTR, 0); - /* Global Configuration Descriptor */ - bus_space_write_4(sc->mc_st, sc->mc_sh, MUSYCC_GLOBALCONF, - sc->mc_global_conf); - - return; -} - -void -musycc_ebus_attach(struct device *parent, struct musycc_softc *esc, - struct pci_attach_args *pa) -{ - struct ebus_dev rom; - struct musycc_attach_args ma; - struct musycc_softc *sc; - pci_chipset_tag_t pc = pa->pa_pc; -#if 0 - pci_intr_handle_t ih; - const char *intrstr = NULL; -#endif - struct musycc_rom baseconf; - struct musycc_rom_framer framerconf; - bus_size_t offset; - int i; - - /* find HDLC controller softc ... */ - SLIST_FOREACH(sc, &msc_list, list) - if (sc->bus == parent->dv_unit && sc->device == pa->pa_device) - break; - if (sc == NULL) { - printf(": corresponding hdlc controller not found\n"); - return; - } - - /* ... and link them together */ - esc->mc_other = sc; - sc->mc_other = esc; - -#if 0 - /* - * Allocate our interrupt. - */ - if (pci_intr_map(pa, &ih)) { - printf(": couldn't map interrupt\n"); - goto failed; - } - - intrstr = pci_intr_string(pc, ih); - esc->mc_ih = pci_intr_establish(pc, ih, IPL_NET, ebus_intr, esc, - esc->mc_dev.dv_xname); - if (esc->mc_ih == NULL) { - printf(": couldn't establish interrupt"); - if (intrstr != NULL) - printf(" at %s", intrstr); - printf("\n"); - goto failed; - } - - /* XXX this printf should actually move to the end of the function */ - printf(": %s\n", intrstr); -#endif - - if (ebus_attach_device(&rom, sc, 0, 0x400) != 0) { - printf(": failed to map rom @ %05x\n", 0); - goto failed; - } - - offset = 0; - ebus_read_buf(&rom, offset, &baseconf, sizeof(baseconf)); - offset += sizeof(baseconf); - - if (baseconf.magic != MUSYCC_ROM_MAGIC) { - printf(": bad rom\n"); - goto failed; - } - - /* Do generic parts of attach. */ - if (musycc_attach_common(sc, baseconf.portmap, baseconf.portmode)) - goto failed; - - /* map and reset leds */ - /* (15 * 0x4000) << 2 */ - esc->mc_ledbase = ntohl(baseconf.ledbase) << 2; - esc->mc_ledmask = baseconf.ledmask; - esc->mc_ledstate = 0; - bus_space_write_1(esc->mc_st, esc->mc_sh, esc->mc_ledbase, 0); - - printf("\n"); - - for (i = 0; i < baseconf.numframer; i++) { - if (offset >= 0x400) { - printf("%s: bad rom\n", sc->mc_dev.dv_xname); - goto failed; - } - ebus_read_buf(&rom, offset, &framerconf, sizeof(framerconf)); - offset += sizeof(framerconf); - - strlcpy(ma.ma_product, baseconf.product, sizeof(ma.ma_product)); - ma.ma_base = ntohl(framerconf.base); - ma.ma_size = ntohl(framerconf.size); - ma.ma_type = ntohl(framerconf.type); - ma.ma_gnum = framerconf.gnum; - ma.ma_port = framerconf.port; - ma.ma_flags = framerconf.flags; - ma.ma_slot = framerconf.slot; - - (void)config_found(&sc->mc_dev, &ma, musycc_ebus_print); - } - - return; -failed: - /* Failed! */ - pci_intr_disestablish(pc, sc->mc_ih); - if (esc->mc_ih != NULL) - pci_intr_disestablish(pc, esc->mc_ih); - bus_space_unmap(sc->mc_st, sc->mc_sh, sc->mc_iosize); - bus_space_unmap(esc->mc_st, esc->mc_sh, esc->mc_iosize); - return; -} - -int -musycc_ebus_print(void *aux, const char *pnp) -{ - struct musycc_attach_args *ma = aux; - - if (pnp) - printf("framer at %s port %d slot %c", - pnp, ma->ma_port, ma->ma_slot); - else - printf(" port %d slot %c", ma->ma_port, ma->ma_slot); - return (UNCONF); -} - diff --git a/sys/dev/pci/musyccreg.h b/sys/dev/pci/musyccreg.h deleted file mode 100644 index c3b39740b1d..00000000000 --- a/sys/dev/pci/musyccreg.h +++ /dev/null @@ -1,255 +0,0 @@ -/* $OpenBSD: musyccreg.h,v 1.3 2005/08/27 12:53:17 claudio Exp $ */ - -/* - * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Claudio Jeker <jeker@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#ifndef __MUSYCCREG_H__ -#define __MUSYCCREG_H__ - -#define MUSYCC_PCI_BAR 0x10 /* offset of Base Address Register */ - -/* Group Base Pointer -- per Group unique */ -#define MUSYCC_GROUPBASE(x) (0x0800 * (x)) -/* Dual Address Cycle Base Pointer */ -#define MUSYCC_DACB_PTR 0x0004 -/* Service Request Descriptor -- per Group unique */ -#define MUSYCC_SERREQ(x) (0x0008 + 0x0800 * (x)) -/* Interrupt Status Descriptor */ -#define MUSYCC_INTRSTATUS 0x000c -#define MUSYCC_INTCNT_MASK 0x00007fff -#define MUSYCC_INTFULL 0x00008000 -#define MUSYCC_NEXTINT_GET(x) (((x) >> 16) & 0x7fff) -#define MUSYCC_NEXTINT_SET(x) (((x) & 0x7fff) << 16) - -/* Global Configuration Descriptor */ -#define MUSYCC_GLOBALCONF 0x0600 -/* Interrupt Queue Descriptor */ -#define MUSYCC_INTQPTR 0x0604 -#define MUSYCC_INTQLEN 0x0608 - -/* group structure [page 5-6], this puppy needs to be 2k aligned */ -struct musycc_grpdesc { - u_int32_t tx_headp[32]; /* transmit head ptr */ - u_int32_t tx_msgp[32]; /* transmit msg ptr */ - u_int32_t rx_headp[32]; /* receive head ptr */ - u_int32_t rx_msgp[32]; /* receive msg ptr */ - u_int8_t tx_tsmap[128]; /* transmit timeslot map */ - u_int8_t tx_submap[256]; /* transmit sub channel map */ - u_int32_t tx_cconf[32]; /* transmit channel config */ - u_int8_t rx_tsmap[128]; /* receive timeslot map */ - u_int8_t rx_submap[256]; /* receive sub channel map */ - u_int32_t rx_cconf[32]; /* receive channel config */ - u_int32_t global_conf; /* global config */ - u_int32_t int_queuep; /* interrupt queue ptr */ - u_int32_t int_queuelen; /* interrupt queue len */ - u_int32_t group_conf; /* group config */ - u_int32_t memprot; /* memory protection */ - u_int32_t msglen_conf; /* message length config */ - u_int32_t port_conf; /* serial port config */ -}; - -/* Global Configuration Descriptor [page 5-10] */ -#define MUSYCC_CONF_PORTMAP 0x00000003 /* group -> port mapping */ -#define MUSYCC_CONF_INTB 0x00000004 /* if set INTB is disabled */ -#define MUSYCC_CONF_INTA 0x00000008 /* if set INTA is disabled */ -#define MUSYCC_CONF_ELAPSE_GET(x) \ - (((x) >> 4) & 0x7) /* get elapse value */ -#define MUSYCC_CONF_ELAPSE_SET(x) \ - ((x & 0x7) << 4) /* set elapse value */ -#define MUSYCC_CONF_ALAPSE_GET(x) \ - (((x) >> 8) & 0x3) /* get alapse value */ -#define MUSYCC_CONF_ALAPSE_SET(x) \ - ((x & 0x3) << 8) /* set alapse value */ -#define MUSYCC_CONF_MPUSEL 0x00000400 /* EBUS mode, 1 = intel style */ -#define MUSYCC_CONF_ECKEN 0x00000800 /* EBUS clock enable */ -#define MUSYCC_CONF_BLAPSE_GET(x) \ - (((x) >> 12) & 0x7) /* get blapse value */ -#define MUSYCC_CONF_BLAPSE_SET(x) \ - ((x & 0x7) << 12) /* set blapse value */ - -/* Interrupt Descriptor [page 5-41] */ -#define MUSYCC_INTD_BLEN 0x00001fff /* size of data on EOB & EOM */ -#define MUSYCC_INTD_ILOST 0x00008000 /* Interrupt Lost */ -#define MUSYCC_INTD_DIR 0x80000000 /* transmit specific int */ -#define MUSYCC_INTD_GRP(x) \ - ((((x) >> 29) & 0x3) | (((x) >> 12) & 0x4)) /* Group Number [0-7] */ -#define MUSYCC_INTD_CHAN(x) \ - (((x) >> 24) & 0x1f) /* Channel Number [0-31] */ -#define MUSYCC_INTD_EVENT(x) \ - (((x) >> 20) & 0xf) /* Event that caused the int */ -#define MUSYCC_INTD_ERROR(x) \ - (((x) >> 16) & 0xf) /* Error that caused the int */ - -/* possible Interrupt Events */ -#define MUSYCC_INTEV_NONE 0 /* No Event to report */ -#define MUSYCC_INTEV_SACK 1 /* Service Request Ack */ -#define MUSYCC_INTEV_EOB 2 /* End of Buffer */ -#define MUSYCC_INTEV_EOM 3 /* End of Message */ -#define MUSYCC_INTEV_EOP 4 /* End of Padfill */ -#define MUSYCC_INTEV_CHABT 5 /* Change to Abort Code */ -#define MUSYCC_INTEV_CHIC 6 /* Change to Idle Code */ -#define MUSYCC_INTEV_FREC 7 /* Frame Recovery */ -#define MUSYCC_INTEV_SINC 8 /* SS7 SUERM Octet Count inc */ -#define MUSYCC_INTEV_SDEC 9 /* SS7 SUERM Octet Count dec */ -#define MUSYCC_INTEV_SFILT 10 /* SS7 Filtered Message */ - -/* possible Interrupt Errors */ -#define MUSYCC_INTERR_NONE 0 /* No Error to report */ -#define MUSYCC_INTERR_BUFF 1 /* Buffer Error */ -#define MUSYCC_INTERR_COFA 2 /* Change of Frame Alignment */ -#define MUSYCC_INTERR_ONR 3 /* Owner-Bit Error */ -#define MUSYCC_INTERR_PROT 4 /* Mem Protection Violation */ -#define MUSYCC_INTERR_OOF 8 /* Out of Frame */ -#define MUSYCC_INTERR_FCS 9 /* Frame Check Sequence Error */ -#define MUSYCC_INTERR_ALIGN 10 /* Octet Alignment Error */ -#define MUSYCC_INTERR_ABT 11 /* Abort Termination */ -#define MUSYCC_INTERR_LNG 12 /* Long Message */ -#define MUSYCC_INTERR_SHT 13 /* Short Message */ -#define MUSYCC_INTERR_SUERR 14 /* SS7 Signal Unit Error */ -#define MUSYCC_INTERR_PERR 15 /* PCI Bus Parity Error */ - -/* Service Request Descriptor [page 5-14] */ -#define MUSYCC_SREQ_MASK 0x001f /* Generic SREQ/Channel Mask */ -#define MUSYCC_SREQ_CHSET(x) \ - ((x) & MUSYCC_SREQ_MASK) /* shortcut */ -#define MUSYCC_SREQ_TXDIR 0x0020 /* Transmit Direction */ -#define MUSYCC_SREQ_SET(x) \ - (((x) & MUSYCC_SREQ_MASK) << 8) /* Service Request */ - -#define MUSYCC_SREQ_RX 0x1 /* Receive Request */ -#define MUSYCC_SREQ_TX 0x2 /* Transmit Request */ -#define MUSYCC_SREQ_BOTH 0x3 /* both directions */ -#define MUSYCC_SREQ_NOWAIT 0x8 -#define MUSYCC_SREQ_NONE 0xffffffff - -/* Group Configuration Descriptor [page 5-16] */ -#define MUSYCC_GRCFG_RXENBL 0x0001 /* Receiver Enabled */ -#define MUSYCC_GRCFG_TXENBL 0x0002 /* Transmitter Enabled */ -#define MUSYCC_GRCFG_SUBDSBL 0x0004 /* Subchanneling Disabled */ -#define MUSYCC_GRCFG_OOFABT 0x0008 /* OOF Message Processing */ -#define MUSYCC_GRCFG_MSKOOF 0x0010 /* OOF Interrupt Disabled */ -#define MUSYCC_GRCFG_MSKCOFA 0x0020 /* COFA Interrupt Disabled */ -#define MUSYCC_GRCFG_MCENBL 0x0040 /* Msg Config Bits Copy */ -#define MUSYCC_GRCFG_INHRBSD 0x0100 /* Inihibit RX Buf Stat Desc */ -#define MUSYCC_GRCFG_INHTBSD 0x0200 /* Inihibit TX Buf Stat Desc */ -#define MUSYCC_GRCFG_POLL16 0x0400 /* Poll at all 16 frame sync */ -#define MUSYCC_GRCFG_POLL32 0x0800 /* Poll at all 32 frame sync */ -#define MUSYCC_GRCFG_POLL64 0x0C00 /* Poll at all 64 frame sync */ -#define MUSYCC_GRCFG_SFALIGN 0x8000 /* Super Frame Alignment */ -#define MUSYCC_GRCFG_SUETMASK 0x3f0000 /* SS7 SUERR Threshold */ - -/* Port Configuration Descriptor [page 5-19] */ -#define MUSYCC_PORT_MODEMASK 0x007 /* Port Mode Mask */ -#define MUSYCC_PORT_MODE_T1 0 /* T1 - 24 time slots */ -#define MUSYCC_PORT_MODE_E1 1 /* E1 - 32 time slots */ -#define MUSYCC_PORT_MODE_2E1 2 /* 2*E1 - 64 time slots */ -#define MUSYCC_PORT_MODE_4E1 3 /* 4*E1 - 128 time slots */ -#define MUSYCC_PORT_MODE_N64 4 /* N*64 mode */ -#define MUSYCC_PORT_TDAT_EDGE 0x010 /* TX Data on rising Edge */ -#define MUSYCC_PORT_TSYNC_EDGE 0x020 /* TX Frame Sync on rising E */ -#define MUSYCC_PORT_RDAT_EDGE 0x040 /* RX Data on rising Edge */ -#define MUSYCC_PORT_RSYNC_EDGE 0x080 /* RX Frame Sync on rising E */ -#define MUSYCC_PORT_ROOF_EDGE 0x100 /* RX OOF on rising Edge */ -#define MUSYCC_PORT_TRITX 0x200 /* TX Three-state disabled */ - -/* Message Length Descriptor [page 5-20] */ -#define MUSYCC_MAXFRM_MAX 4094 /* maximum message length */ -#define MUSYCC_MAXFRM_MASK 0x0fff -#define MUSYCC_MAXFRM2_SHIFT 16 - -/* Time Slot Descriptor [page 5-23] */ -#define MUSYCC_TSLOT_ENABLED 0x80 /* timeslot enabled */ -#define MUSYCC_TSLOT_56K 0x20 /* 56kbps timeslots */ -#define MUSYCC_TSLOT_SUB 0x40 /* subchannel timeslots */ -#define MUSYCC_TSLOT_MASK 0x1f /* channel number mask */ -#define MUSYCC_TSLOT_CHAN(x) \ - ((x) & MUSYCC_TSLOT_MASK) /* masked channel number */ - -/* Channel Configuration Descriptor [page 5-27] */ -#define MUSYCC_CHAN_MSKBUFF 0x00000002 /* BUFF & ONR Intr disabled */ -#define MUSYCC_CHAN_MSKEOM 0x00000004 /* EOM Interrupt disabled */ -#define MUSYCC_CHAN_MSKMSG 0x00000008 /* LNG, FCS, ALIGN, ABT mask */ -#define MUSYCC_CHAN_MSKIDLE 0x00000010 /* CHABT, CHIC, SHT Intr mask */ -#define MUSYCC_CHAN_MSKSFILT 0x00000020 /* SS7 SFILT Interrupt mask */ -#define MUSYCC_CHAN_MSKSDEC 0x00000040 /* SS7 SDEC Interrupt mask */ -#define MUSYCC_CHAN_MSKSINC 0x00000080 /* SS7 SINC Interrupt mask */ -#define MUSYCC_CHAN_MSKSUERR 0x00000100 /* SS7 SUERR Interrupt mask */ -#define MUSYCC_CHAN_FCS 0x00000200 /* FCS checksum disable */ -#define MUSYCC_CHAN_MAXLEN1 0x00000400 /* Msg Len Max via MAXFRM1 */ -#define MUSYCC_CHAN_MAXLEN2 0x00000800 /* Msg Len Max via MAXFRM1 */ -#define MUSYCC_CHAN_EOPI 0x00008000 /* End of Padfill Int enable */ -#define MUSYCC_CHAN_INV 0x00800000 /* Data Inversion */ -#define MUSYCC_CHAN_PADJ 0x80000000 /* Pad Count Adjust enabled */ - -#define MUSYCC_CHAN_PROTO_GET(x) \ - (((x) >> 12) & 0x7) /* get line protocol */ -#define MUSYCC_CHAN_PROTO_SET(x) \ - ((x & 0x7) << 12) /* set line protocol */ -#define MUSYCC_PROTO_TRANSPARENT 0 /* raw stream */ -#define MUSYCC_PROTO_SS7HDLC 1 /* SS7 HDLC messages */ -#define MUSYCC_PROTO_HDLC16 2 /* basic HDLC with 16 bit FCS */ -#define MUSYCC_PROTO_HDLC32 3 /* basic HDLC with 32 bit FCS */ - -#define MUSYCC_CHAN_BUFLEN_GET(x) \ - (((x) >> 16) & 0x3f) /* get FIFO Buffer Length */ -#define MUSYCC_CHAN_BUFLEN_SET(x) \ - (((x) & 0x3F) << 16) /* set FIFO Buffer Length */ -#define MUSYCC_CHAN_BUFIDX_GET(x) \ - (((x) >> 24) & 0x3f) /* get FIFO Buffer Index */ -#define MUSYCC_CHAN_BUFIDX_SET(x) \ - (((x) & 0x3F) << 24) /* set FIFO Buffer Index */ - - -/* Tx / Rx Buffer Descriptor [page 5-33] */ -#define MUSYCC_STATUS_LEN(x) \ - ((x) & 0x3fff) /* length of dma buffer */ -#define MUSYCC_STATUS_REPEAT 0x00008000 /* repeat buffer */ -#define MUSYCC_STATUS_ERROR 0x000f0000 -#define MUSYCC_STATUS_EOBI 0x10000000 /* end of buffer interrupt */ -#define MUSYCC_STATUS_EOM 0x20000000 /* end of message */ -#define MUSYCC_STATUS_NOPOLL 0x40000000 /* don't poll for new descr */ -#define MUSYCC_STATUS_OWNER 0x80000000 - - -/* - * ROM data structures - */ - -struct musycc_rom { - u_int16_t magic; -#define MUSYCC_ROM_MAGIC (htons(0xacc0)) - u_int8_t rev; /* rev. of the card */ - u_int8_t vers; /* version of the rom */ - char product[64]; - u_int8_t portmap; /* portmap config */ - u_int8_t portmode; /* port mode e.g. 2*E1 */ - u_int8_t numframer; /* # of sub-configs */ - u_int8_t ledmask; /* mask for led register */ - u_int32_t ledbase; /* base of the led register */ - u_int32_t rfu[2]; /* RFU */ -}; - -struct musycc_rom_framer { - u_int32_t type; - u_int32_t base; - u_int32_t size; - u_int8_t gnum; - u_int8_t port; - char slot; - u_int8_t flags; - u_int32_t rfu[2]; /* RFU */ -}; -#endif diff --git a/sys/dev/pci/musyccvar.h b/sys/dev/pci/musyccvar.h deleted file mode 100644 index 305fedbf89f..00000000000 --- a/sys/dev/pci/musyccvar.h +++ /dev/null @@ -1,231 +0,0 @@ -/* $OpenBSD: musyccvar.h,v 1.9 2006/02/06 17:29:11 jmc Exp $ */ - -/* - * Copyright (c) 2004,2005 Internet Business Solutions AG, Zurich, Switzerland - * Written by: Claudio Jeker <jeker@accoom.net> - * - * Permission to use, copy, modify, and distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. - * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. - */ -#ifndef __MUSYCCVAR_H__ -#define __MUSYCCVAR_H__ - -#include <sys/queue.h> - -#define PPP_HEADER_LEN 4 /* should be globaly defined by sppp */ - -/* some defaults */ -#define MUSYCC_NUMCHAN 32 /* 32 channels per group */ -#define MUSYCC_NUMPORT 8 /* max 8 ports per controller */ -#define MUSYCC_SREQNUM 16 /* pending SREQ */ -#define MUSYCC_SREQMASK (MUSYCC_SREQNUM - 1) -#define MUSYCC_SREQTIMEOUT 2 - -/* dma ring sizes */ -#define MUSYCC_DMA_CNT 256 -#define MUSYCC_DMA_MAPSIZE (MUSYCC_DMA_CNT * sizeof(struct dma_desc)) -#define MUSYCC_DMA_SIZE 32 - -struct musycc_softc; -struct ebus_softc; - -/* DMA descriptor for data */ -struct dma_desc { - u_int32_t status; - u_int32_t data; - u_int32_t next; - /* Software only */ - struct mbuf *mbuf; - struct dma_desc *nextdesc; - bus_dmamap_t map; -}; - -#define MUSYCC_INTLEN 512 /* 512 pending interrupts is enough */ -struct musycc_intdesc { - u_int32_t md_intrq[MUSYCC_INTLEN]; -}; - -struct musycc_dma_data { - /* - * received dma ring. rx_prod points to the frist descriptors that - * is under musycc control (first empty). - */ - struct dma_desc *rx_prod; - int rx_cnt; - - struct dma_desc *tx_pend; /* finished pointer */ - struct dma_desc *tx_cur; /* current insertion pointer */ - int tx_cnt; /* number of descriptors */ - int tx_use; /* number of used descriptors */ - int tx_pkts; /* number of packets in queue */ -}; - -enum musycc_state { - CHAN_FLOAT, /* unconnected channel */ - CHAN_IDLE, - CHAN_RUNNING, - CHAN_FAULT, - CHAN_TRANSIENT /* dummy state to protect ongoing state changes */ -}; - -enum musycc_event { - EV_NULL, /* null event, ignore */ - EV_ACTIVATE, /* activate channel go to running state */ - EV_STOP, /* stop dma engine */ - EV_IDLE, /* free timeslots et al. and go to idle state */ - EV_WATCHDOG /* watchdog event, stop dma engine */ -}; - -/* group structure */ -struct musycc_group { - struct musycc_softc *mg_hdlc; /* main controller */ - struct musycc_grpdesc *mg_group; /* group descriptor */ - u_int8_t mg_gnum; /* group number */ - u_int8_t mg_port; /* port number */ - u_int8_t mg_loaded; /* sreq(5) done? */ - u_int64_t mg_fifomask; /* fifo allocation mask */ - - struct channel_softc *mg_channels[MUSYCC_NUMCHAN]; - struct musycc_dma_data mg_dma_d[MUSYCC_NUMCHAN]; - struct dma_desc *mg_freelist; - int mg_freecnt; - - struct { - long timeout; - u_int32_t sreq; - enum musycc_event event; - } mg_sreq[MUSYCC_SREQNUM]; - int mg_sreqpend; - int mg_sreqprod; - - struct dma_desc *mg_dma_pool; - bus_dma_tag_t mg_dmat; /* bus dma tag */ - caddr_t mg_listkva; - bus_dmamap_t mg_listmap; - bus_dma_segment_t mg_listseg[1]; - int mg_listnseg; - bus_dmamap_t mg_tx_sparemap; - bus_dmamap_t mg_rx_sparemap; -}; - -/* attach arguments for framer devices */ -struct musycc_attach_args { - char ma_product[64]; - bus_size_t ma_base; - bus_size_t ma_size; - u_int32_t ma_type; - u_int8_t ma_gnum; - u_int8_t ma_port; - u_int8_t ma_flags; - char ma_slot; -}; - -/* generic ebus device handle */ -struct ebus_dev { - bus_size_t base; - bus_size_t size; - bus_space_tag_t st; - bus_space_handle_t sh; -}; - -/* Softc for each HDLC channel config */ -struct channel_softc { - struct sppp cc_ppp; /* sppp network attachement */ - struct ifnet *cc_ifp; /* pointer to the active ifp */ - struct musycc_group *cc_group; - struct device *cc_parent; /* parent framer */ - - u_int32_t cc_tslots; /* timeslot map */ - int cc_unit; - enum musycc_state cc_state; /* state machine info */ - u_int8_t cc_channel; /* HDLC channel */ - u_int8_t cc_locked; -}; - -/* Softc for the HDLC Controller (function 0) */ -struct musycc_softc { - struct device mc_dev; /* generic device structures */ - void *mc_ih; /* interrupt handler cookie */ - bus_space_tag_t mc_st; /* bus space tag */ - bus_space_handle_t mc_sh; /* bus space handle */ - bus_dma_tag_t mc_dmat; /* bus dma tag */ - bus_size_t mc_iosize; /* size of bus space */ - - caddr_t mc_groupkva; /* group configuration mem */ - bus_dmamap_t mc_cfgmap; - bus_dma_segment_t mc_cfgseg[1]; - bus_dmamap_t mc_intrmap; - bus_dma_segment_t mc_intrseg[1]; - int mc_cfgnseg; - int mc_intrnseg; - - struct musycc_group *mc_groups; /* mc_ngroups groups */ - struct musycc_intdesc *mc_intrd; - u_int32_t mc_global_conf; /* global config descriptor */ - u_int32_t mc_intrqptr; /* interrupt queue pointer */ - int mc_ngroups; - int mc_nports; - - struct musycc_softc *mc_other; /* the other EBUS/HDLC dev */ - bus_size_t mc_ledbase; - u_int8_t mc_ledmask; - u_int8_t mc_ledstate; /* current state of the LEDs */ - int bus, device; /* location of card */ - SLIST_ENTRY(musycc_softc) list; /* list of all hdlc ctrls */ -}; - -int musycc_attach_common(struct musycc_softc *, u_int32_t, u_int32_t); -void musycc_set_port(struct musycc_group *, int); -int musycc_init_channel(struct channel_softc *, char); -void musycc_stop_channel(struct channel_softc *); -void musycc_free_channel(struct musycc_group *, int); -void musycc_start(struct ifnet *); -void musycc_watchdog(struct ifnet *); -void musycc_tick(struct channel_softc *); - -int musycc_intr(void *); -int ebus_intr(void *); - -/* EBUS API */ -int ebus_attach_device(struct ebus_dev *, struct musycc_softc *, - bus_size_t, bus_size_t); -u_int8_t ebus_read(struct ebus_dev *, bus_size_t); -void ebus_write(struct ebus_dev *, bus_size_t, u_int8_t); -void ebus_read_buf(struct ebus_dev *, bus_size_t, void *, size_t); -void ebus_set_led(struct channel_softc *, int, u_int8_t); - -#define MUSYCC_LED_GREEN 0x1 -#define MUSYCC_LED_RED 0x2 -#define MUSYCC_LED_MASK 0x3 - -/* channel API */ -struct channel_softc *musycc_channel_create(const char *, u_int8_t); -void musycc_attach_sppp(struct channel_softc *, - int (*)(struct ifnet *, u_long, caddr_t)); -int musycc_channel_attach(struct musycc_softc *, - struct channel_softc *, struct device *, u_int8_t); -void musycc_channel_detach(struct ifnet *); - - -#ifndef ACCOOM_DEBUG -#define ACCOOM_PRINTF(n, x) -#else -extern int accoom_debug; - -#define ACCOOM_PRINTF(n, x) \ - do { \ - if (accoom_debug >= n) \ - printf x; \ - } while (0) -#endif - -#endif |