diff options
| author |   jsg <jsg@openbsd.org> | 2012-03-19 00:49:08 +0000 |
|---|---|---|
| committer | jsg <jsg@openbsd.org> | 2012-03-19 00:49:08 +0000 |
| commit | e7e3a2604558c3c04f33d902e5cc0f941262bd0e (patch) | |
| tree | 2d172a8f78dbd17878b4159d1426a56a652bc869 | |
| parent | clarify the nwkey text; requested by Doug Fordham (diff) | |
| download | wireguard-openbsd-e7e3a2604558c3c04f33d902e5cc0f941262bd0e.tar.xz wireguard-openbsd-e7e3a2604558c3c04f33d902e5cc0f941262bd0e.zip | |
more intel cpu models, though the low/high est method is largely
irrelevant with acpi machines
| -rw-r--r-- | sys/arch/amd64/amd64/est.c | 18 | ||||
| -rw-r--r-- | sys/arch/i386/i386/machdep.c | 18 |
2 files changed, 22 insertions, 14 deletions
diff --git a/sys/arch/amd64/amd64/est.c b/sys/arch/amd64/amd64/est.c index 621e16461df..88ebe98cdfe 100644 --- a/sys/arch/amd64/amd64/est.c +++ b/sys/arch/amd64/amd64/est.c @@ -1,4 +1,4 @@ -/* $OpenBSD: est.c,v 1.26 2012/02/25 00:19:20 haesbaert Exp $ */ +/* $OpenBSD: est.c,v 1.27 2012/03/19 00:49:08 jsg Exp $ */ /* * Copyright (c) 2003 Michael Eriksson. * All rights reserved. @@ -167,6 +167,7 @@ p3_get_bus_clock(struct cpu_info *ci) case 0xf: /* Core Xeon */ case 0x16: /* 65nm Celeron */ case 0x17: /* Core 2 Extreme/45nm Xeon */ + case 0x1d: /* Xeon MP 7400 */ msr = rdmsr(MSR_FSB_FREQ); bus = (msr >> 0) & 0x7; switch (bus) { @@ -195,6 +196,8 @@ p3_get_bus_clock(struct cpu_info *ci) } break; case 0x1c: /* Atom */ + case 0x26: /* Atom Z6xx */ + case 0x36: /* Atom [DN]2xxx */ msr = rdmsr(MSR_FSB_FREQ); bus = (msr >> 0) & 0x7; switch (bus) { @@ -216,19 +219,20 @@ p3_get_bus_clock(struct cpu_info *ci) break; } break; + /* nehalem */ case 0x1a: /* Core i7, Xeon 3500/5500 */ case 0x1e: /* Core i5/i7, Xeon 3400 */ case 0x1f: /* Core i5/i7 */ + case 0x2e: /* Xeon 6500/7500 */ + /* westmere */ case 0x25: /* Core i3/i5, Xeon 3400 */ case 0x2c: /* Core i7, Xeon 3600/5600 */ - /* BUS133 */ - break; + case 0x2f: /* Xeon E7 */ + /* sandy bridge */ case 0x2a: /* Core i5/i7 2nd Generation */ case 0x2d: /* Xeon E5 */ - /* BUS100 */ - break; - case 0x1d: /* Xeon MP 7400 */ - case 0x2e: /* Xeon 6500/7500 */ + /* ivy bridge */ + case 0x3a: /* Core i3/i5/i7 3rd Generation */ break; default: printf("%s: unknown i686 model 0x%x, can't get bus clock\n", diff --git a/sys/arch/i386/i386/machdep.c b/sys/arch/i386/i386/machdep.c index a4f411ac0b9..1e07d7bc885 100644 --- a/sys/arch/i386/i386/machdep.c +++ b/sys/arch/i386/i386/machdep.c @@ -1,4 +1,4 @@ -/* $OpenBSD: machdep.c,v 1.506 2011/11/02 23:53:44 jsg Exp $ */ +/* $OpenBSD: machdep.c,v 1.507 2012/03/19 00:49:08 jsg Exp $ */ /* $NetBSD: machdep.c,v 1.214 1996/11/10 03:16:17 thorpej Exp $ */ /*- @@ -2047,6 +2047,7 @@ p3_get_bus_clock(struct cpu_info *ci) case 0xf: /* Core Xeon */ case 0x16: /* 65nm Celeron */ case 0x17: /* Core 2 Extreme/45nm Xeon */ + case 0x1d: /* Xeon MP 7400 */ msr = rdmsr(MSR_FSB_FREQ); bus = (msr >> 0) & 0x7; switch (bus) { @@ -2075,6 +2076,8 @@ p3_get_bus_clock(struct cpu_info *ci) } break; case 0x1c: /* Atom */ + case 0x26: /* Atom Z6xx */ + case 0x36: /* Atom [DN]2xxx */ msr = rdmsr(MSR_FSB_FREQ); bus = (msr >> 0) & 0x7; switch (bus) { @@ -2122,19 +2125,20 @@ p3_get_bus_clock(struct cpu_info *ci) goto print_msr; } break; + /* nehalem */ case 0x1a: /* Core i7, Xeon 3500/5500 */ case 0x1e: /* Core i5/i7, Xeon 3400 */ case 0x1f: /* Core i5/i7 */ + case 0x2e: /* Xeon 6500/7500 */ + /* westmere */ case 0x25: /* Core i3/i5, Xeon 3400 */ case 0x2c: /* Core i7, Xeon 3600/5600 */ - /* BUS133 */ - break; + case 0x2f: /* Xeon E7 */ + /* sandy bridge */ case 0x2a: /* Core i5/i7 2nd Generation */ case 0x2d: /* Xeon E5 */ - /* BUS100 */ - break; - case 0x1d: /* Xeon MP 7400 */ - case 0x2e: /* Xeon 6500/7500 */ + /* ivy bridge */ + case 0x3a: /* Core i3/i5/i7 3rd Generation */ break; default: printf("%s: unknown i686 model 0x%x, can't get bus clock", |