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authorbriggs <briggs@openbsd.org>1996-06-15 21:27:17 +0000
committerbriggs <briggs@openbsd.org>1996-06-15 21:27:17 +0000
commite8138b1823e3d449738872793fbdb6ffb09178c0 (patch)
tree2c7b2df631377585a16c351b10570039a59191f5
parentComment industries non use of EM_486. (diff)
downloadwireguard-openbsd-e8138b1823e3d449738872793fbdb6ffb09178c0.tar.xz
wireguard-openbsd-e8138b1823e3d449738872793fbdb6ffb09178c0.zip
NetBSD PR #2547: wrong bus error detection from is@beverly.rhein.de.
-rw-r--r--sys/arch/mac68k/mac68k/locore.s32
1 files changed, 26 insertions, 6 deletions
diff --git a/sys/arch/mac68k/mac68k/locore.s b/sys/arch/mac68k/mac68k/locore.s
index 184c1f40433..b16fc931af4 100644
--- a/sys/arch/mac68k/mac68k/locore.s
+++ b/sys/arch/mac68k/mac68k/locore.s
@@ -1,4 +1,4 @@
-/* $OpenBSD: locore.s,v 1.9 1996/06/09 00:47:25 briggs Exp $ */
+/* $OpenBSD: locore.s,v 1.10 1996/06/15 21:27:17 briggs Exp $ */
/* $NetBSD: locore.s,v 1.64 1996/06/09 01:53:42 briggs Exp $ */
/*
@@ -216,18 +216,38 @@ Lbe10:
cmpw #12,d0 | address error vector?
jeq Lisaerr | yes, go to it
movl d1,a0 | fault address
- ptestr #1,a0@,#7 | do a table search
+ movl sp@,d0 | function code from ssw
+ btst #8,d0 | data fault?
+ jne Lbe10a
+ movql #1,d0 | user program access FC
+ | (we dont seperate data/program)
+ btst #5,a1@ | supervisor mode?
+ jeq Lbe10a | if no, done
+ movql #5,d0 | else supervisor program access
+Lbe10a:
+ ptestr d0,a0@,#7 | do a table search
pmove psr,sp@ | save result
- btst #7,sp@ | bus error bit set?
- jeq Lismerr | no, must be MMU fault
- clrw sp@ | yes, re-clear pad word
- jra Lisberr | and process as normal bus error
+ movb sp@,d1
+ btst #2,d1 | invalid (incl. limit viol. and berr)?
+ jeq Lmightnotbemerr | no -> wp check
+ btst #7,d1 | is it MMU table berr?
+ jeq Lismerr | no, must be fast
+ jra Lisberr1 | real bus err needs not be fast.
+Lmightnotbemerr:
+ btst #3,d1 | write protect bit set?
+ jeq Lisberr1 | no: must be bus error
+ movl sp@,d0 | ssw into low word of d0
+ andw #0xc0,d0 | Write protect is set on page:
+ cmpw #0x40,d0 | was it read cycle?
+ jeq Lisberr1 | yes, was not WPE, must be bus err
Lismerr:
movl #T_MMUFLT,sp@- | show that we are an MMU fault
jra Ltrapnstkadj | and deal with it
Lisaerr:
movl #T_ADDRERR,sp@- | mark address error
jra Ltrapnstkadj | and deal with it
+Lisberr1:
+ clrw sp@ | re-clear pad word
Lisberr:
movl #T_BUSERR,sp@- | mark bus error
Ltrapnstkadj: