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authorderaadt <deraadt@openbsd.org>2020-09-14 13:30:33 +0000
committerderaadt <deraadt@openbsd.org>2020-09-14 13:30:33 +0000
commite9ee0c60d109a95de4010941646f5f4701676699 (patch)
tree2bc0d52ee5f9eb8a0d37d59e95cd58011340b763
parentDocument "pki" option for relay delivery too; from Nick Gasson (diff)
downloadwireguard-openbsd-e9ee0c60d109a95de4010941646f5f4701676699.tar.xz
wireguard-openbsd-e9ee0c60d109a95de4010941646f5f4701676699.zip
Delete some emulator code which has never been used on 64 bit sparc
ok kettenis, test compile by kmos
-rw-r--r--sys/arch/sparc64/sparc64/emul.c210
1 files changed, 1 insertions, 209 deletions
diff --git a/sys/arch/sparc64/sparc64/emul.c b/sys/arch/sparc64/sparc64/emul.c
index d33047d1111..565df915b24 100644
--- a/sys/arch/sparc64/sparc64/emul.c
+++ b/sys/arch/sparc64/sparc64/emul.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: emul.c,v 1.25 2020/08/19 10:10:58 mpi Exp $ */
+/* $OpenBSD: emul.c,v 1.26 2020/09/14 13:30:33 deraadt Exp $ */
/* $NetBSD: emul.c,v 1.8 2001/06/29 23:58:40 eeh Exp $ */
/*-
@@ -47,216 +47,8 @@
# define DPRINTF(a)
#endif
-#define GPR(tf, i) ((int32_t *)(u_long)&tf->tf_global)[i]
-#define IPR(tf, i) ((int32_t *)(u_long)tf->tf_out[6])[i - 16]
-
-static __inline int readgpreg(struct trapframe64 *, int, void *);
-static __inline int writegpreg(struct trapframe64 *, int, const void *);
-static __inline int decodeaddr(struct trapframe64 *, union instr *, void *);
-static int muldiv(struct trapframe64 *, union instr *, int32_t *, int32_t *,
- int32_t *);
void swap_quad(int64_t *);
-#define REGNAME(i) "goli"[i >> 3], i & 7
-
-
-static __inline int
-readgpreg(tf, i, val)
- struct trapframe64 *tf;
- int i;
- void *val;
-{
- int error = 0;
- if (i == 0)
- *(int32_t *) val = 0;
- else if (i < 16)
- *(int32_t *) val = GPR(tf, i);
- else
- error = copyin(&IPR(tf, i), val, sizeof(int32_t));
-
- return error;
-}
-
-static __inline int
-writegpreg(tf, i, val)
- struct trapframe64 *tf;
- int i;
- const void *val;
-{
- int error = 0;
-
- if (i == 0)
- return error;
- else if (i < 16)
- GPR(tf, i) = *(int32_t *) val;
- else
- /* XXX: Fix copyout prototype */
- error = copyout((caddr_t) val, &IPR(tf, i), sizeof(int32_t));
-
- return error;
-}
-
-static __inline int
-decodeaddr(tf, code, val)
- struct trapframe64 *tf;
- union instr *code;
- void *val;
-{
- if (code->i_simm13.i_i)
- *((int32_t *) val) = code->i_simm13.i_simm13;
- else {
- int error;
-
- if (code->i_asi.i_asi)
- return EINVAL;
- if ((error = readgpreg(tf, code->i_asi.i_rs2, val)) != 0)
- return error;
- }
- return 0;
-}
-
-
-static int
-muldiv(tf, code, rd, rs1, rs2)
- struct trapframe64 *tf;
- union instr *code;
- int32_t *rd, *rs1, *rs2;
-{
- /*
- * We check for {S,U}{MUL,DIV}{,cc}
- *
- * [c = condition code, s = sign]
- * Mul = 0c101s
- * Div = 0c111s
- */
- union {
- struct {
- unsigned unused:26; /* padding */
- unsigned zero:1; /* zero by opcode */
- unsigned cc:1; /* one to send condition code */
- unsigned one1:1; /* one by opcode */
- unsigned div:1; /* one if divide */
- unsigned one2:1; /* one by opcode */
- unsigned sgn:1; /* sign bit */
- } bits;
- int num;
- } op;
-
- op.num = code->i_op3.i_op3;
-
-#ifdef DEBUG_EMUL
- printf("muldiv 0x%x: %c%s%s %c%d, %c%d, ", code->i_int,
- "us"[op.bits.sgn], op.bits.div ? "div" : "mul",
- op.bits.cc ? "cc" : "", REGNAME(code->i_op3.i_rd),
- REGNAME(code->i_op3.i_rs1));
- if (code->i_loadstore.i_i)
- printf("0x%x\n", *rs2);
- else
- printf("%c%d\n", REGNAME(code->i_asi.i_rs2));
-#endif
-
- if (op.bits.div) {
- if (*rs2 == 0) {
- /*
- * XXX: to be 100% correct here, on sunos we need to
- * ignore the error and return *rd = *rs1.
- * It should be easy to fix by passing struct
- * proc in here.
- */
- DPRINTF(("muldiv: avoid zerodivide\n"));
- return EINVAL;
- }
- *rd = *rs1 / *rs2;
- DPRINTF(("muldiv: %d / %d = %d\n", *rs1, *rs2, *rd));
- }
- else {
- *rd = *rs1 * *rs2;
- DPRINTF(("muldiv: %d * %d = %d\n", *rs1, *rs2, *rd));
- }
-
- if (op.bits.cc) {
- /* Set condition codes */
- tf->tf_tstate &= ~(TSTATE_CCR);
-
- if (*rd == 0)
- tf->tf_tstate |= (u_int64_t)(ICC_Z|XCC_Z) << TSTATE_CCR_SHIFT;
- else {
- if (op.bits.sgn && *rd < 0)
- tf->tf_tstate |= (u_int64_t)(ICC_N|XCC_N) << TSTATE_CCR_SHIFT;
- if (op.bits.div) {
- if (*rd * *rs2 != *rs1)
- tf->tf_tstate |= (u_int64_t)(ICC_V|XCC_V) << TSTATE_CCR_SHIFT;
- }
- else {
- if (*rd / *rs2 != *rs1)
- tf->tf_tstate |= (u_int64_t)(ICC_V|XCC_V) << TSTATE_CCR_SHIFT;
- }
- }
- }
-
- return 0;
-}
-
-/*
- * Emulate unimplemented instructions on earlier sparc chips.
- */
-int
-emulinstr(pc, tf)
- vaddr_t pc;
- struct trapframe64 *tf;
-{
- union instr code;
- int32_t rs1, rs2, rd;
- int error;
-
- /* fetch and check the instruction that caused the fault */
- error = copyin((caddr_t) pc, &code.i_int, sizeof(code.i_int));
- if (error != 0) {
- DPRINTF(("emulinstr: Bad instruction fetch\n"));
- return (SIGILL);
- }
-
- /* Only support format 2 */
- if (code.i_any.i_op != 2) {
- DPRINTF(("emulinstr: Not a format 2 instruction\n"));
- return (SIGILL);
- }
-
- write_user_windows();
-
- if ((error = readgpreg(tf, code.i_op3.i_rs1, &rs1)) != 0) {
- DPRINTF(("emulinstr: read rs1 %d\n", error));
- return (SIGILL);
- }
-
- if ((error = decodeaddr(tf, &code, &rs2)) != 0) {
- DPRINTF(("emulinstr: decode addr %d\n", error));
- return (SIGILL);
- }
-
- switch (code.i_op3.i_op3) {
- case IOP3_FLUSH:
-/* cpuinfo.cache_flush((caddr_t)(rs1 + rs2), 4); XXX */
- return (0);
-
- default:
- if ((code.i_op3.i_op3 & 0x2a) != 0xa) {
- DPRINTF(("emulinstr: Unsupported op3 0x%x\n",
- code.i_op3.i_op3));
- return (SIGILL);
- }
- else if ((error = muldiv(tf, &code, &rd, &rs1, &rs2)) != 0)
- return (SIGFPE);
- }
-
- if ((error = writegpreg(tf, code.i_op3.i_rd, &rd)) != 0) {
- DPRINTF(("muldiv: write rd %d\n", error));
- return (SIGILL);
- }
-
- return (0);
-}
-
#define SIGN_EXT13(v) (((int64_t)(v) << 51) >> 51)
void