diff options
| author |   kettenis <kettenis@openbsd.org> | 2019-09-20 22:42:05 +0000 |
|---|---|---|
| committer | kettenis <kettenis@openbsd.org> | 2019-09-20 22:42:05 +0000 |
| commit | ea5e035f4d57ede9f18c82c5c9decc5f46c1925a (patch) | |
| tree | 273f759f13d156bb8de0dd5d337baf5f60e744a0 | |
| parent | Extend the identification and validation of elantech-v4 packets to the (diff) | |
| download | wireguard-openbsd-ea5e035f4d57ede9f18c82c5c9decc5f46c1925a.tar.xz wireguard-openbsd-ea5e035f4d57ede9f18c82c5c9decc5f46c1925a.zip | |
Add A20 GMAC clocks.
| -rw-r--r-- | sys/dev/fdt/sxiccmu.c | 17 | ||||
| -rw-r--r-- | sys/dev/fdt/sxiccmu_clocks.h | 4 |
2 files changed, 18 insertions, 3 deletions
diff --git a/sys/dev/fdt/sxiccmu.c b/sys/dev/fdt/sxiccmu.c index a19f505042c..60c83ac5a35 100644 --- a/sys/dev/fdt/sxiccmu.c +++ b/sys/dev/fdt/sxiccmu.c @@ -1,4 +1,4 @@ -/* $OpenBSD: sxiccmu.c,v 1.24 2019/09/08 16:45:21 kettenis Exp $ */ +/* $OpenBSD: sxiccmu.c,v 1.25 2019/09/20 22:42:05 kettenis Exp $ */ /* * Copyright (c) 2007,2009 Dale Rahn <drahn@openbsd.org> * Copyright (c) 2013 Artturi Alm @@ -887,12 +887,15 @@ sxiccmu_ccu_get_frequency(void *cookie, uint32_t *cells) #define A10_CPU_CLK_SRC_SEL_OSC24M (0x1 << 16) #define A10_CPU_CLK_SRC_SEL_PLL1 (0x2 << 16) #define A10_CPU_CLK_SRC_SEL_200MHZ (0x3 << 16) +#define A10_AHB_CLK_DIV_RATIO(x) (((x) >> 8) & 0x3) +#define A10_AXI_CLK_DIV_RATIO(x) (((x) >> 0) & 0x3) uint32_t sxiccmu_a10_get_frequency(struct sxiccmu_softc *sc, uint32_t idx) { uint32_t parent; - uint32_t reg, k, m, n, p; + uint32_t reg, div; + uint32_t k, m, n, p; switch (idx) { case A10_CLK_LOSC: @@ -927,6 +930,16 @@ sxiccmu_a10_get_frequency(struct sxiccmu_softc *sc, uint32_t idx) return 200000000; } return sxiccmu_ccu_get_frequency(sc, &parent); + case A10_CLK_AXI: + reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG); + div = 1 << A10_AXI_CLK_DIV_RATIO(reg); + parent = A10_CLK_CPU; + return sxiccmu_ccu_get_frequency(sc, &parent) / div; + case A10_CLK_AHB: + reg = SXIREAD4(sc, A10_CPU_AHB_APB0_CFG_REG); + div = 1 << A10_AHB_CLK_DIV_RATIO(reg); + parent = A10_CLK_AXI; + return sxiccmu_ccu_get_frequency(sc, &parent) / div; case A10_CLK_APB1: /* XXX Controlled by a MUX. */ return 24000000; diff --git a/sys/dev/fdt/sxiccmu_clocks.h b/sys/dev/fdt/sxiccmu_clocks.h index 558c9a66f32..cc545f40b9b 100644 --- a/sys/dev/fdt/sxiccmu_clocks.h +++ b/sys/dev/fdt/sxiccmu_clocks.h @@ -13,6 +13,8 @@ #define A10_CLK_PLL_PERIPH 15 #define A10_CLK_CPU 20 +#define A10_CLK_AXI 21 +#define A10_CLK_AHB 23 #define A10_CLK_APB1 25 #define A10_CLK_AHB_EHCI0 27 @@ -63,7 +65,7 @@ struct sxiccmu_ccu_bit sun4i_a10_gates[] = { [A10_CLK_AHB_MMC3] = { 0x0060, 11 }, [A10_CLK_AHB_EMAC] = { 0x0060, 17 }, [A10_CLK_AHB_SATA] = { 0x0060, 25 }, - [A10_CLK_AHB_GMAC] = { 0x0064, 17 }, + [A10_CLK_AHB_GMAC] = { 0x0064, 17, A10_CLK_AHB }, [A10_CLK_APB0_PIO] = { 0x0068, 5 }, [A10_CLK_APB1_I2C0] = { 0x006c, 0, A10_CLK_APB1 }, [A10_CLK_APB1_I2C1] = { 0x006c, 1, A10_CLK_APB1 }, |