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authorvisa <visa@openbsd.org>2017-11-01 14:43:01 +0000
committervisa <visa@openbsd.org>2017-11-01 14:43:01 +0000
commitf4fee9bee8e910d99350ef3819cb9150a0663c43 (patch)
tree49d68770228873853d9fc0c7dc29d506f8763609
parentFix the addressing of CVMSEG. The base address already points to (diff)
downloadwireguard-openbsd-f4fee9bee8e910d99350ef3819cb9150a0663c43.tar.xz
wireguard-openbsd-f4fee9bee8e910d99350ef3819cb9150a0663c43.zip
Add readiness to utilize LMTDMA operations.
-rw-r--r--sys/arch/octeon/dev/cn30xxcorereg.h7
-rw-r--r--sys/arch/octeon/include/octeonvar.h31
-rw-r--r--sys/arch/octeon/octeon/machdep.c17
3 files changed, 52 insertions, 3 deletions
diff --git a/sys/arch/octeon/dev/cn30xxcorereg.h b/sys/arch/octeon/dev/cn30xxcorereg.h
index b4e12114a07..63ab6108dec 100644
--- a/sys/arch/octeon/dev/cn30xxcorereg.h
+++ b/sys/arch/octeon/dev/cn30xxcorereg.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: cn30xxcorereg.h,v 1.1 2014/03/13 02:17:13 yasuoka Exp $ */
+/* $OpenBSD: cn30xxcorereg.h,v 1.2 2017/11/01 14:43:01 visa Exp $ */
/*
* Copyright (c) 2014 YASUOKA Masahiko <yasuoka@openbsd.org>
@@ -52,4 +52,9 @@
#define COP_0_CVMCTL_LE 0x00000002
#define COP_0_CVMCTL_USELY 0x00000001
+/* CvmMemCtl register */
+#define COP_0_CVMMEMCTL_LMTENA 0x0008000000000000ull
+#define COP_0_CVMMEMCTL_LMTLINE_M 0x0007e00000000000ull
+#define COP_0_CVMMEMCTL_LMTLINE_S 45
+
#endif /* _CN30XXCOREREG_H_ */
diff --git a/sys/arch/octeon/include/octeonvar.h b/sys/arch/octeon/include/octeonvar.h
index fd25d378260..d28a259d08e 100644
--- a/sys/arch/octeon/include/octeonvar.h
+++ b/sys/arch/octeon/include/octeonvar.h
@@ -1,4 +1,4 @@
-/* $OpenBSD: octeonvar.h,v 1.38 2017/11/01 14:29:04 visa Exp $ */
+/* $OpenBSD: octeonvar.h,v 1.39 2017/11/01 14:43:01 visa Exp $ */
/* $NetBSD: maltavar.h,v 1.3 2002/03/18 10:10:16 simonb Exp $ */
/*-
@@ -360,6 +360,12 @@ octeon_iobdma_write_8(uint64_t value)
*(volatile uint64_t *)addr = value;
}
+static inline void
+octeon_lmtdma_write_8(off_t offset, uint64_t value)
+{
+ *(volatile uint64_t *)(0xffffffffffffa400ULL + offset) = value;
+}
+
static inline uint64_t
octeon_cvmseg_read_8(size_t offset)
{
@@ -385,6 +391,29 @@ octeon_get_cycles(void)
return tmp;
}
+static inline uint64_t
+octeon_get_cvmmemctl(void)
+{
+ uint64_t tmp;
+
+ __asm volatile (
+ _ASM_PROLOGUE_OCTEON
+ " dmfc0 %[tmp], $11, 7 \n"
+ _ASM_EPILOGUE
+ : [tmp]"=r"(tmp));
+ return tmp;
+}
+
+static inline void
+octeon_set_cvmmemctl(uint64_t val)
+{
+ __asm volatile (
+ _ASM_PROLOGUE_OCTEON
+ " dmtc0 %[tmp], $11, 7 \n"
+ _ASM_EPILOGUE
+ : : [tmp]"r"(val) : "memory");
+}
+
static inline void
octeon_synciobdma(void)
{
diff --git a/sys/arch/octeon/octeon/machdep.c b/sys/arch/octeon/octeon/machdep.c
index b4ee447d9ac..433ff9ec2ca 100644
--- a/sys/arch/octeon/octeon/machdep.c
+++ b/sys/arch/octeon/octeon/machdep.c
@@ -1,4 +1,4 @@
-/* $OpenBSD: machdep.c,v 1.100 2017/09/17 06:10:53 visa Exp $ */
+/* $OpenBSD: machdep.c,v 1.101 2017/11/01 14:43:01 visa Exp $ */
/*
* Copyright (c) 2009, 2010 Miodrag Vallat.
@@ -80,6 +80,7 @@
#include <dev/cons.h>
#include <dev/ofw/fdt.h>
+#include <octeon/dev/cn30xxcorereg.h>
#include <octeon/dev/cn30xxipdreg.h>
#include <octeon/dev/iobusvar.h>
#include <machine/octeonreg.h>
@@ -638,8 +639,22 @@ octeon_ioclock_speed(void)
void
octeon_tlb_init(void)
{
+ uint64_t cvmmemctl;
uint32_t hwrena = 0;
uint32_t pgrain = 0;
+ int chipid;
+
+ chipid = octeon_get_chipid();
+ switch (octeon_model_family(chipid)) {
+ case OCTEON_MODEL_FAMILY_CN73XX:
+ /* Enable LMTDMA/LMTST transactions. */
+ cvmmemctl = octeon_get_cvmmemctl();
+ cvmmemctl |= COP_0_CVMMEMCTL_LMTENA;
+ cvmmemctl &= ~COP_0_CVMMEMCTL_LMTLINE_M;
+ cvmmemctl |= 2ull << COP_0_CVMMEMCTL_LMTLINE_S;
+ octeon_set_cvmmemctl(cvmmemctl);
+ break;
+ }
/*
* If the UserLocal register is available, let userspace