diff options
author | 2013-03-17 21:15:55 +0000 | |
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committer | 2013-03-17 21:15:55 +0000 | |
commit | f669f536d0d85f13c475e3ebec7247a1e43e2617 (patch) | |
tree | 40cbb1a03ec478676c3d67e7f6db35c84a09b4c7 | |
parent | - Remove the reserved number of TX descriptors. No limitation is mentioned in (diff) | |
download | wireguard-openbsd-f669f536d0d85f13c475e3ebec7247a1e43e2617.tar.xz wireguard-openbsd-f669f536d0d85f13c475e3ebec7247a1e43e2617.zip |
- Mention the VT6102 chipset
- Add PC Engines boards; Requested by chris@
- Move section BUGS to CAVEATS and change the alignment comment
to mention that this is only used for the VT3043 and VT86C100A
chips
ok chris@
-rw-r--r-- | share/man/man4/vr.4 | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/share/man/man4/vr.4 b/share/man/man4/vr.4 index 5a8c340cf05..707e6219c9b 100644 --- a/share/man/man4/vr.4 +++ b/share/man/man4/vr.4 @@ -1,4 +1,4 @@ -.\" $OpenBSD: vr.4,v 1.30 2013/03/17 18:37:57 brad Exp $ +.\" $OpenBSD: vr.4,v 1.31 2013/03/17 21:15:55 brad Exp $ .\" .\" Copyright (c) 1997, 1998 .\" Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. @@ -48,8 +48,8 @@ The .Nm driver provides support for PCI Ethernet adapters and embedded controllers based on the VIA Technologies VT3043 Rhine I, -VT86C100A Rhine II, and VT6105/VT6105M Rhine III Fast Ethernet -controller chips, including the following: +VT86C100A Rhine II, VT6102 Rhine II, and VT6105/VT6105M Rhine III +Fast Ethernet controller chips, including the following: .Pp .Bl -bullet -compact .It @@ -59,6 +59,8 @@ D-Link DFE-520TX, DFE-530TX .It Hawking Technologies PN102TX .It +PC Engines alix1d, alix2d2, alix2d3, alix2d13, alix3d2, alix3d3, and alix6f2 +.It Soekris Engineering net5501, and lan1741 .El .Pp @@ -193,11 +195,11 @@ The .Nm driver was written by .An Bill Paul Aq wpaul@ctr.columbia.edu . -.Sh BUGS +.Sh CAVEATS The .Nm -driver always copies transmit mbuf chains into longword-aligned -buffers prior to transmission in order to pacify the Rhine chips. +driver copies transmit mbuf chains into longword-aligned buffers prior +to transmission in order to pacify the VT3043 and VT86C100A chips. If buffers are not aligned correctly, the chip will round the supplied buffer address and begin DMAing from the wrong location. This buffer copying impairs transmit performance on slower systems but can't |