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| author |   kettenis <kettenis@openbsd.org> | 2018-06-16 15:27:28 +0000 |
|---|---|---|
| committer | kettenis <kettenis@openbsd.org> | 2018-06-16 15:27:28 +0000 |
| commit | f984b70872f9867c55962c1bcd1a122b7673d1ed (patch) | |
| tree | 8443f668da0df35d8c30450879eec474b35342fc | |
| parent | Enable imxrtc(4). (diff) | |
| download | wireguard-openbsd-f984b70872f9867c55962c1bcd1a122b7673d1ed.tar.xz wireguard-openbsd-f984b70872f9867c55962c1bcd1a122b7673d1ed.zip | |
Fix some i.MX7D clocks.
| -rw-r--r-- | sys/dev/fdt/imxccm_clocks.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/sys/dev/fdt/imxccm_clocks.h b/sys/dev/fdt/imxccm_clocks.h index 112cf838b9c..0a6bee3847f 100644 --- a/sys/dev/fdt/imxccm_clocks.h +++ b/sys/dev/fdt/imxccm_clocks.h @@ -83,10 +83,12 @@ struct imxccm_gate imx6ul_gates[] = { #define IMX7D_ENET_AXI_ROOT_SRC 0x53 #define IMX7D_ENET_AXI_ROOT_CG 0x54 #define IMX7D_ENET_AXI_ROOT_DIV 0x55 +#define IMX7D_ENET1_IPG_ROOT_CLK 0x9e #define IMX7D_ENET1_TIME_ROOT_CLK 0xa2 #define IMX7D_ENET1_TIME_ROOT_SRC 0xa3 #define IMX7D_ENET1_TIME_ROOT_CG 0xa4 #define IMX7D_ENET1_TIME_ROOT_DIV 0xa5 +#define IMX7D_ENET2_IPG_ROOT_CLK 0xa6 #define IMX7D_ENET2_TIME_ROOT_CLK 0xaa #define IMX7D_ENET2_TIME_ROOT_SRC 0xab #define IMX7D_ENET2_TIME_ROOT_CG 0xac @@ -193,15 +195,16 @@ struct imxccm_gate imx7d_gates[] = { [IMX7D_UART6_ROOT_CG] = { 0xb200, 28, IMX7D_UART6_ROOT_SRC }, [IMX7D_UART7_ROOT_CG] = { 0xb280, 28, IMX7D_UART7_ROOT_SRC }, [IMX7D_ENET_AXI_ROOT_CLK] = { 0x4060, 0, IMX7D_ENET_AXI_ROOT_DIV }, - [IMX7D_ENET1_TIME_ROOT_CLK] = { 0x44f0, 0, IMX7D_ENET1_TIME_ROOT_DIV }, - [IMX7D_ENET2_TIME_ROOT_CLK] = { 0x4510, 0, IMX7D_ENET2_TIME_ROOT_DIV }, - [IMX7D_ENET_PHY_REF_ROOT_CLK] = { 0x4520, 0, IMX7D_ENET_PHY_REF_ROOT_DIV }, [IMX7D_USB_CTRL_CLK] = { 0x4680, 0 }, [IMX7D_USB_PHY1_CLK] = { 0x46a0, 0 }, [IMX7D_USB_PHY2_CLK] = { 0x46b0, 0 }, [IMX7D_USDHC1_ROOT_CLK] = { 0x46c0, 0, IMX7D_USDHC1_ROOT_DIV }, [IMX7D_USDHC2_ROOT_CLK] = { 0x46d0, 0, IMX7D_USDHC2_ROOT_DIV }, [IMX7D_USDHC3_ROOT_CLK] = { 0x46e0, 0, IMX7D_USDHC3_ROOT_DIV }, + [IMX7D_ENET1_IPG_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET_AXI_ROOT_DIV }, + [IMX7D_ENET1_TIME_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET1_TIME_ROOT_DIV }, + [IMX7D_ENET2_IPG_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET_AXI_ROOT_DIV }, + [IMX7D_ENET2_TIME_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET1_TIME_ROOT_DIV }, [IMX7D_I2C1_ROOT_CLK] = { 0x4880, 0, IMX7D_I2C1_ROOT_DIV }, [IMX7D_I2C2_ROOT_CLK] = { 0x4890, 0, IMX7D_I2C2_ROOT_DIV }, [IMX7D_I2C3_ROOT_CLK] = { 0x48a0, 0, IMX7D_I2C3_ROOT_DIV }, @@ -237,7 +240,7 @@ struct imxccm_divider imx7d_divs[] = { [IMX7D_ENET_AXI_ROOT_DIV] = { 0x8900, 0, 0x3f, IMX7D_ENET_AXI_ROOT_PRE_DIV }, [IMX7D_ENET1_TIME_ROOT_DIV] = { 0xa780, 0, 0x3f, IMX7D_ENET1_TIME_ROOT_PRE_DIV }, [IMX7D_ENET2_TIME_ROOT_DIV] = { 0xa880, 0, 0x3f, IMX7D_ENET2_TIME_ROOT_PRE_DIV }, - [IMX7D_ENET_PHY_REF_ROOT_DIV] = { 0xa900, 0, 0x3f, IMX7D_ENET_PHY_REF_ROOT_PRE_DIV }, + [IMX7D_ENET_PHY_REF_ROOT_CLK] = { 0xa900, 0, 0x3f, IMX7D_ENET_PHY_REF_ROOT_PRE_DIV }, [IMX7D_USDHC1_ROOT_DIV] = { 0xab00, 0, 0x3f, IMX7D_USDHC1_ROOT_PRE_DIV }, [IMX7D_USDHC2_ROOT_DIV] = { 0xab80, 0, 0x3f, IMX7D_USDHC2_ROOT_PRE_DIV }, [IMX7D_USDHC3_ROOT_DIV] = { 0xac00, 0, 0x3f, IMX7D_USDHC3_ROOT_PRE_DIV }, |