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| author | 2020-08-03 15:06:44 +0000 | |
|---|---|---|
| committer | 2020-08-03 15:06:44 +0000 | |
| commit | b64793999546ed8adebaeebd9d8345d18db8927d (patch) | |
| tree | 4357c27b561d73b0e089727c6ed659f2ceff5f47 /gnu/llvm/lib/CodeGen/AllocationOrder.cpp | |
| parent | Add support for UTF-8 DISPLAY-HINTs with octet length. For now only (diff) | |
| download | wireguard-openbsd-b64793999546ed8adebaeebd9d8345d18db8927d.tar.xz wireguard-openbsd-b64793999546ed8adebaeebd9d8345d18db8927d.zip | |
Remove LLVM 8.0.1 files.
Diffstat (limited to 'gnu/llvm/lib/CodeGen/AllocationOrder.cpp')
| -rw-r--r-- | gnu/llvm/lib/CodeGen/AllocationOrder.cpp | 55 |
1 files changed, 0 insertions, 55 deletions
diff --git a/gnu/llvm/lib/CodeGen/AllocationOrder.cpp b/gnu/llvm/lib/CodeGen/AllocationOrder.cpp deleted file mode 100644 index 37dcb0be824..00000000000 --- a/gnu/llvm/lib/CodeGen/AllocationOrder.cpp +++ /dev/null @@ -1,55 +0,0 @@ -//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements an allocation order for virtual registers. -// -// The preferred allocation order for a virtual register depends on allocation -// hints and target hooks. The AllocationOrder class encapsulates all of that. -// -//===----------------------------------------------------------------------===// - -#include "AllocationOrder.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterClassInfo.h" -#include "llvm/CodeGen/VirtRegMap.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -#define DEBUG_TYPE "regalloc" - -// Compare VirtRegMap::getRegAllocPref(). -AllocationOrder::AllocationOrder(unsigned VirtReg, - const VirtRegMap &VRM, - const RegisterClassInfo &RegClassInfo, - const LiveRegMatrix *Matrix) - : Pos(0), HardHints(false) { - const MachineFunction &MF = VRM.getMachineFunction(); - const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo(); - Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); - if (TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix)) - HardHints = true; - rewind(); - - LLVM_DEBUG({ - if (!Hints.empty()) { - dbgs() << "hints:"; - for (unsigned I = 0, E = Hints.size(); I != E; ++I) - dbgs() << ' ' << printReg(Hints[I], TRI); - dbgs() << '\n'; - } - }); -#ifndef NDEBUG - for (unsigned I = 0, E = Hints.size(); I != E; ++I) - assert(is_contained(Order, Hints[I]) && - "Target hint is outside allocation order."); -#endif -} |
