diff options
| author | 2019-01-27 16:42:12 +0000 | |
|---|---|---|
| committer | 2019-01-27 16:42:12 +0000 | |
| commit | b773203fb58f3ef282fb69c832d8710cab5bc82d (patch) | |
| tree | e75913f147570fbd75169647b144df85b88a038c /gnu/llvm/lib/CodeGen/RegAllocBasic.cpp | |
| parent | tweak errno in previous (diff) | |
| download | wireguard-openbsd-b773203fb58f3ef282fb69c832d8710cab5bc82d.tar.xz wireguard-openbsd-b773203fb58f3ef282fb69c832d8710cab5bc82d.zip | |
Import LLVM 7.0.1 release including clang, lld and lldb.
Diffstat (limited to 'gnu/llvm/lib/CodeGen/RegAllocBasic.cpp')
| -rw-r--r-- | gnu/llvm/lib/CodeGen/RegAllocBasic.cpp | 13 |
1 files changed, 6 insertions, 7 deletions
diff --git a/gnu/llvm/lib/CodeGen/RegAllocBasic.cpp b/gnu/llvm/lib/CodeGen/RegAllocBasic.cpp index 1125d2c62be..daeff3fc396 100644 --- a/gnu/llvm/lib/CodeGen/RegAllocBasic.cpp +++ b/gnu/llvm/lib/CodeGen/RegAllocBasic.cpp @@ -219,8 +219,8 @@ bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, Intfs.push_back(Intf); } } - DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) - << " interferences with " << VirtReg << "\n"); + LLVM_DEBUG(dbgs() << "spilling " << printReg(PhysReg, TRI) + << " interferences with " << VirtReg << "\n"); assert(!Intfs.empty() && "expected interference"); // Spill each interfering vreg allocated to PhysReg or an alias. @@ -292,7 +292,7 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, } // No other spill candidates were found, so spill the current VirtReg. - DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); + LLVM_DEBUG(dbgs() << "spilling: " << VirtReg << '\n'); if (!VirtReg.isSpillable()) return ~0u; LiveRangeEdit LRE(&VirtReg, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats); @@ -304,9 +304,8 @@ unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, } bool RABasic::runOnMachineFunction(MachineFunction &mf) { - DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" - << "********** Function: " - << mf.getName() << '\n'); + LLVM_DEBUG(dbgs() << "********** BASIC REGISTER ALLOCATION **********\n" + << "********** Function: " << mf.getName() << '\n'); MF = &mf; RegAllocBase::init(getAnalysis<VirtRegMap>(), @@ -323,7 +322,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) { postOptimization(); // Diagnostic output before rewriting - DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); + LLVM_DEBUG(dbgs() << "Post alloc VirtRegMap:\n" << *VRM << "\n"); releaseMemory(); return true; |
