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| author | 2019-06-23 21:36:31 +0000 | |
|---|---|---|
| committer | 2019-06-23 21:36:31 +0000 | |
| commit | 23f101f37937a1bd4a29726cab2f76e0fb038b35 (patch) | |
| tree | f7da7d6b32c2e07114da399150bfa88d72187012 /gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp | |
| parent | sort previous; ok deraadt (diff) | |
| download | wireguard-openbsd-23f101f37937a1bd4a29726cab2f76e0fb038b35.tar.xz wireguard-openbsd-23f101f37937a1bd4a29726cab2f76e0fb038b35.zip | |
Import LLVM 8.0.0 release including clang, lld and lldb.
Diffstat (limited to 'gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp')
| -rw-r--r-- | gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp | 47 |
1 files changed, 23 insertions, 24 deletions
diff --git a/gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp b/gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp index f1c442ac38a..66c7c5cd7db 100644 --- a/gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp +++ b/gnu/llvm/lib/CodeGen/RegUsageInfoCollector.cpp @@ -81,7 +81,7 @@ FunctionPass *llvm::createRegUsageInfoCollector() { bool RegUsageInfoCollector::runOnMachineFunction(MachineFunction &MF) { MachineRegisterInfo *MRI = &MF.getRegInfo(); const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); - const TargetMachine &TM = MF.getTarget(); + const LLVMTargetMachine &TM = MF.getTarget(); LLVM_DEBUG(dbgs() << " -------------------- " << getPassName() << " -------------------- \n"); @@ -166,28 +166,27 @@ computeCalleeSavedRegs(BitVector &SavedRegs, MachineFunction &MF) { } // Insert any register fully saved via subregisters. - for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) { - if (SavedRegs.test(PReg)) - continue; - - // Check if PReg is fully covered by its subregs. - bool CoveredBySubRegs = false; - for (const TargetRegisterClass *RC : TRI.regclasses()) - if (RC->CoveredBySubRegs && RC->contains(PReg)) { - CoveredBySubRegs = true; - break; - } - if (!CoveredBySubRegs) - continue; - - // Add PReg to SavedRegs if all subregs are saved. - bool AllSubRegsSaved = true; - for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR) - if (!SavedRegs.test(*SR)) { - AllSubRegsSaved = false; - break; - } - if (AllSubRegsSaved) - SavedRegs.set(PReg); + for (const TargetRegisterClass *RC : TRI.regclasses()) { + if (!RC->CoveredBySubRegs) + continue; + + for (unsigned PReg = 1, PRegE = TRI.getNumRegs(); PReg < PRegE; ++PReg) { + if (SavedRegs.test(PReg)) + continue; + + // Check if PReg is fully covered by its subregs. + if (!RC->contains(PReg)) + continue; + + // Add PReg to SavedRegs if all subregs are saved. + bool AllSubRegsSaved = true; + for (MCSubRegIterator SR(PReg, &TRI, false); SR.isValid(); ++SR) + if (!SavedRegs.test(*SR)) { + AllSubRegsSaved = false; + break; + } + if (AllSubRegsSaved) + SavedRegs.set(PReg); + } } } |
