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| author | 2019-01-27 16:42:12 +0000 | |
|---|---|---|
| committer | 2019-01-27 16:42:12 +0000 | |
| commit | b773203fb58f3ef282fb69c832d8710cab5bc82d (patch) | |
| tree | e75913f147570fbd75169647b144df85b88a038c /gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | |
| parent | tweak errno in previous (diff) | |
| download | wireguard-openbsd-b773203fb58f3ef282fb69c832d8710cab5bc82d.tar.xz wireguard-openbsd-b773203fb58f3ef282fb69c832d8710cab5bc82d.zip | |
Import LLVM 7.0.1 release including clang, lld and lldb.
Diffstat (limited to 'gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h')
| -rw-r--r-- | gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 56 |
1 files changed, 42 insertions, 14 deletions
diff --git a/gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h b/gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h index 9e7c2bc6821..4b5dda982f1 100644 --- a/gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h +++ b/gnu/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h @@ -21,7 +21,6 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/ISDOpcodes.h" -#include "llvm/CodeGen/MachineValueType.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/CodeGen/TargetLowering.h" @@ -33,6 +32,7 @@ #include "llvm/Support/BranchProbability.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MachineValueType.h" #include <algorithm> #include <cassert> #include <cstdint> @@ -116,9 +116,12 @@ class SelectionDAGBuilder { unsigned getSDNodeOrder() { return SDNodeOrder; } }; + /// DanglingDebugInfoVector - Helper type for DanglingDebugInfoMap. + typedef std::vector<DanglingDebugInfo> DanglingDebugInfoVector; + /// DanglingDebugInfoMap - Keeps track of dbg_values for which we have not /// yet seen the referent. We defer handling these until we do see it. - DenseMap<const Value*, DanglingDebugInfo> DanglingDebugInfoMap; + DenseMap<const Value*, DanglingDebugInfoVector> DanglingDebugInfoMap; public: /// PendingLoads - Loads are not emitted to the program immediately. We bunch @@ -671,6 +674,12 @@ public: /// emit CopyFromReg of the specified type Ty. Return empty SDValue() otherwise. SDValue getCopyFromRegs(const Value *V, Type *Ty); + /// If we have dangling debug info that describes \p Variable, or an + /// overlapping part of variable considering the \p Expr, then this method + /// weill drop that debug info as it isn't valid any longer. + void dropDanglingDebugInfo(const DILocalVariable *Variable, + const DIExpression *Expr); + // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, // generate the debug data structures now that we've seen its definition. void resolveDanglingDebugInfo(const Value *V, SDValue Val); @@ -678,6 +687,13 @@ public: SDValue getValue(const Value *V); bool findValue(const Value *V) const; + /// Return the SDNode for the specified IR value if it exists. + SDNode *getNodeForIRValue(const Value *V) { + if (NodeMap.find(V) == NodeMap.end()) + return nullptr; + return NodeMap[V].getNode(); + } + SDValue getNonRegisterValue(const Value *V); SDValue getValueImpl(const Value *V); @@ -696,13 +712,13 @@ public: void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, - Instruction::BinaryOps Opc, BranchProbability TW, - BranchProbability FW, bool InvertCond); + Instruction::BinaryOps Opc, BranchProbability TProb, + BranchProbability FProb, bool InvertCond); void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, - BranchProbability TW, BranchProbability FW, + BranchProbability TProb, BranchProbability FProb, bool InvertCond); bool ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases); bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB); @@ -774,11 +790,11 @@ public: }; /// Lower \p SLI into a STATEPOINT instruction. - SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SLI); + SDValue LowerAsSTATEPOINT(StatepointLoweringInfo &SI); // This function is responsible for the whole statepoint lowering process. // It uniformly handles invoke and call statepoints. - void LowerStatepoint(ImmutableStatepoint Statepoint, + void LowerStatepoint(ImmutableStatepoint ISP, const BasicBlock *EHPadBB = nullptr); void LowerCallSiteWithDeoptBundle(ImmutableCallSite CS, SDValue Callee, @@ -838,7 +854,7 @@ private: void visitInvoke(const InvokeInst &I); void visitResume(const ResumeInst &I); - void visitBinary(const User &I, unsigned OpCode); + void visitBinary(const User &I, unsigned Opcode); void visitShift(const User &I, unsigned Opcode); void visitAdd(const User &I) { visitBinary(I, ISD::ADD); } void visitFAdd(const User &I) { visitBinary(I, ISD::FADD); } @@ -881,7 +897,7 @@ private: void visitExtractValue(const User &I); void visitInsertValue(const User &I); - void visitLandingPad(const LandingPadInst &I); + void visitLandingPad(const LandingPadInst &LP); void visitGetElementPtr(const User &I); void visitSelect(const User &I); @@ -926,7 +942,7 @@ private: const BasicBlock *EHPadBB = nullptr); // These two are implemented in StatepointLowering.cpp - void visitGCRelocate(const GCRelocateInst &I); + void visitGCRelocate(const GCRelocateInst &Relocate); void visitGCResult(const GCResultInst &I); void visitVectorReduce(const CallInst &I, unsigned Intrinsic); @@ -999,14 +1015,18 @@ struct RegsForValue { /// Records if this value needs to be treated in an ABI dependant manner, /// different to normal type legalization. - bool IsABIMangled = false; + Optional<CallingConv::ID> CallConv; RegsForValue() = default; RegsForValue(const SmallVector<unsigned, 4> ®s, MVT regvt, EVT valuevt, - bool IsABIMangledValue = false); + Optional<CallingConv::ID> CC = None); RegsForValue(LLVMContext &Context, const TargetLowering &TLI, const DataLayout &DL, unsigned Reg, Type *Ty, - bool IsABIMangledValue = false); + Optional<CallingConv::ID> CC); + + bool isABIMangled() const { + return CallConv.hasValue(); + } /// Add the specified values to this one. void append(const RegsForValue &RHS) { @@ -1036,9 +1056,17 @@ struct RegsForValue { /// Add this value to the specified inlineasm node operand list. This adds the /// code marker, matching input operand index (if applicable), and includes /// the number of values added into it. - void AddInlineAsmOperands(unsigned Kind, bool HasMatching, + void AddInlineAsmOperands(unsigned Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector<SDValue> &Ops) const; + + /// Check if the total RegCount is greater than one. + bool occupiesMultipleRegs() const { + return std::accumulate(RegCount.begin(), RegCount.end(), 0) > 1; + } + + /// Return a list of registers and their sizes. + SmallVector<std::pair<unsigned, unsigned>, 4> getRegsAndSizes() const; }; } // end namespace llvm |
