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| author | 2017-01-24 08:32:59 +0000 | |
|---|---|---|
| committer | 2017-01-24 08:32:59 +0000 | |
| commit | 53d771aafdbe5b919f264f53cba3788e2c4cffd2 (patch) | |
| tree | 7eca39498be0ff1e3a6daf583cd9ca5886bb2636 /gnu/llvm/lib/CodeGen/TargetSubtargetInfo.cpp | |
| parent | In preparation of compiling our kernels with -ffreestanding, explicitly map (diff) | |
| download | wireguard-openbsd-53d771aafdbe5b919f264f53cba3788e2c4cffd2.tar.xz wireguard-openbsd-53d771aafdbe5b919f264f53cba3788e2c4cffd2.zip | |
Import LLVM 4.0.0 rc1 including clang and lld to help the current
development effort on OpenBSD/arm64.
Diffstat (limited to 'gnu/llvm/lib/CodeGen/TargetSubtargetInfo.cpp')
| -rw-r--r-- | gnu/llvm/lib/CodeGen/TargetSubtargetInfo.cpp | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/gnu/llvm/lib/CodeGen/TargetSubtargetInfo.cpp b/gnu/llvm/lib/CodeGen/TargetSubtargetInfo.cpp new file mode 100644 index 00000000000..c74707d95b9 --- /dev/null +++ b/gnu/llvm/lib/CodeGen/TargetSubtargetInfo.cpp @@ -0,0 +1,54 @@ +//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +/// \file This file describes the general parts of a Subtarget. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Target/TargetSubtargetInfo.h" +using namespace llvm; + +//--------------------------------------------------------------------------- +// TargetSubtargetInfo Class +// +TargetSubtargetInfo::TargetSubtargetInfo( + const Triple &TT, StringRef CPU, StringRef FS, + ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetFeatureKV> PD, + const SubtargetInfoKV *ProcSched, const MCWriteProcResEntry *WPR, + const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA, + const InstrStage *IS, const unsigned *OC, const unsigned *FP) + : MCSubtargetInfo(TT, CPU, FS, PF, PD, ProcSched, WPR, WL, RA, IS, OC, FP) { +} + +TargetSubtargetInfo::~TargetSubtargetInfo() {} + +bool TargetSubtargetInfo::enableAtomicExpand() const { + return true; +} + +bool TargetSubtargetInfo::enableMachineScheduler() const { + return false; +} + +bool TargetSubtargetInfo::enableJoinGlobalCopies() const { + return enableMachineScheduler(); +} + +bool TargetSubtargetInfo::enableRALocalReassignment( + CodeGenOpt::Level OptLevel) const { + return true; +} + +bool TargetSubtargetInfo::enablePostRAScheduler() const { + return getSchedModel().PostRAScheduler; +} + +bool TargetSubtargetInfo::useAA() const { + return false; +} |
