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| author | 2018-04-06 14:26:03 +0000 | |
|---|---|---|
| committer | 2018-04-06 14:26:03 +0000 | |
| commit | bdabc2f19ffb9e20600dad6e8a300842a7bda50e (patch) | |
| tree | c50e7b2e5449b074651bb82a58517a8ebc4a8cf7 /gnu/llvm/lib/Target/ARC/ARCTargetMachine.cpp | |
| parent | Print a 'p' flag for file descriptors that were opened after pledge(2). (diff) | |
| download | wireguard-openbsd-bdabc2f19ffb9e20600dad6e8a300842a7bda50e.tar.xz wireguard-openbsd-bdabc2f19ffb9e20600dad6e8a300842a7bda50e.zip | |
Import LLVM 6.0.1 release including clang, lld and lldb.
"where is the kaboom?" deraadt@
Diffstat (limited to 'gnu/llvm/lib/Target/ARC/ARCTargetMachine.cpp')
| -rw-r--r-- | gnu/llvm/lib/Target/ARC/ARCTargetMachine.cpp | 94 |
1 files changed, 94 insertions, 0 deletions
diff --git a/gnu/llvm/lib/Target/ARC/ARCTargetMachine.cpp b/gnu/llvm/lib/Target/ARC/ARCTargetMachine.cpp new file mode 100644 index 00000000000..1acae3a8887 --- /dev/null +++ b/gnu/llvm/lib/Target/ARC/ARCTargetMachine.cpp @@ -0,0 +1,94 @@ +//===- ARCTargetMachine.cpp - Define TargetMachine for ARC ------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// +//===----------------------------------------------------------------------===// + +#include "ARCTargetMachine.h" +#include "ARC.h" +#include "ARCTargetTransformInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/Support/TargetRegistry.h" + +using namespace llvm; + +static Reloc::Model getRelocModel(Optional<Reloc::Model> RM) { + if (!RM.hasValue()) + return Reloc::Static; + return *RM; +} + +static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { + if (CM) + return *CM; + return CodeModel::Small; +} + +/// ARCTargetMachine ctor - Create an ILP32 architecture model +ARCTargetMachine::ARCTargetMachine(const Target &T, const Triple &TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Optional<Reloc::Model> RM, + Optional<CodeModel::Model> CM, + CodeGenOpt::Level OL, bool JIT) + : LLVMTargetMachine(T, + "e-m:e-p:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" + "f32:32:32-i64:32-f64:32-a:0:32-n32", + TT, CPU, FS, Options, getRelocModel(RM), + getEffectiveCodeModel(CM), OL), + TLOF(make_unique<TargetLoweringObjectFileELF>()), + Subtarget(TT, CPU, FS, *this) { + initAsmInfo(); +} + +ARCTargetMachine::~ARCTargetMachine() = default; + +namespace { + +/// ARC Code Generator Pass Configuration Options. +class ARCPassConfig : public TargetPassConfig { +public: + ARCPassConfig(ARCTargetMachine &TM, PassManagerBase &PM) + : TargetPassConfig(TM, PM) {} + + ARCTargetMachine &getARCTargetMachine() const { + return getTM<ARCTargetMachine>(); + } + + bool addInstSelector() override; + void addPreEmitPass() override; + void addPreRegAlloc() override; +}; + +} // end anonymous namespace + +TargetPassConfig *ARCTargetMachine::createPassConfig(PassManagerBase &PM) { + return new ARCPassConfig(*this, PM); +} + +bool ARCPassConfig::addInstSelector() { + addPass(createARCISelDag(getARCTargetMachine(), getOptLevel())); + return false; +} + +void ARCPassConfig::addPreEmitPass() { addPass(createARCBranchFinalizePass()); } + +void ARCPassConfig::addPreRegAlloc() { addPass(createARCExpandPseudosPass()); } + +// Force static initialization. +extern "C" void LLVMInitializeARCTarget() { + RegisterTargetMachine<ARCTargetMachine> X(getTheARCTarget()); +} + +TargetTransformInfo +ARCTargetMachine::getTargetTransformInfo(const Function &F) { + return TargetTransformInfo(ARCTTIImpl(this, F)); +} |
