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authorpatrick <patrick@openbsd.org>2017-12-24 23:15:17 +0000
committerpatrick <patrick@openbsd.org>2017-12-24 23:15:17 +0000
commit34091ed6d5747c7d4acdc1ef6af75ce9b7a8adba (patch)
tree53479f738fa2c63ce6cf95113985510e3653de23 /gnu/llvm/lib/Target/ARM/ARMFastISel.cpp
parentConsolidate printf(3) calls at the end of main(). (diff)
downloadwireguard-openbsd-34091ed6d5747c7d4acdc1ef6af75ce9b7a8adba.tar.xz
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Import LLVM 5.0.1 release including clang, lld and lldb.
Diffstat (limited to 'gnu/llvm/lib/Target/ARM/ARMFastISel.cpp')
-rw-r--r--gnu/llvm/lib/Target/ARM/ARMFastISel.cpp5
1 files changed, 3 insertions, 2 deletions
diff --git a/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp b/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp
index bf00ef61c2d..5dc93734ab5 100644
--- a/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp
+++ b/gnu/llvm/lib/Target/ARM/ARMFastISel.cpp
@@ -1332,6 +1332,8 @@ bool ARMFastISel::SelectIndirectBr(const Instruction *I) {
if (AddrReg == 0) return false;
unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX;
+ assert(isThumb2 || Subtarget->hasV4TOps());
+
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
TII.get(Opc)).addReg(AddrReg));
@@ -2168,9 +2170,8 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
RetRegs.push_back(VA.getLocReg());
}
- unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
- TII.get(RetOpc));
+ TII.get(Subtarget->getReturnOpcode()));
AddOptionalDefs(MIB);
for (unsigned R : RetRegs)
MIB.addReg(R, RegState::Implicit);